CONTROL CIRCUIT FOR A POWER CONVERTER

Abstract

The invention provides a control circuit for controlling the operation of a power converter having a switch connected to an output of the power converter, said control circuit comprising a first amplifier for sensing an output voltage of the power converter and a second amplifier configured to derive a frequency compensated error signal output, to provide a frequency control compensation loop to an input of the power converter and the output of the second amplifier is connected to the switch of the power converter.

Claims

1. A control circuit for controlling the operation of a power converter having a switch connected to an output of the power converter, said control circuit comprising: a first amplifier configured to sense an output voltage of the power converter; and a second amplifier configured to derive a frequency compensated error signal output, V.sub.f1, to provide a frequency control compensation loop to an input of the power converter and an output, V.sub.g, of the second amplifier is connected to the switch of the power converter.

2. The control circuit for controlling the operation of a power converter as claimed in claim 1 comprising a resistor element connected between the output V.sub.g of the second amplifier and the switch.

3. The control circuit for controlling the operation of a power converter as claimed in claim 1 wherein the switch is a MOSFET switch and connected in series with the output of an isolated ac/dc converter.

4. The control circuit for controlling the operation of a power converter as claimed in claim 1 comprising a current limit protection module configured to differentially amplify a voltage across a current sense resistor, V.sub.cs, using a third amplifier.

5. The control circuit of claim 4 wherein the current limit protection module is configured to subtract the signal from a reference and integrate and frequency compensate the resultant error signal using a fourth amplifier.

6. The control circuit for controlling the operation of a power converter as claimed in claim 1 comprising a short circuit protection switch connected to a resistor element and configured to receive control signals from a digital controller.

7. The control circuit for controlling the operation of a power converter as claimed in claim 1 comprising a microcontroller configured to communicate and enable the output voltage and current limit references to be varied.

8. The control circuit for controlling the operation of a power converter as claimed in claim 7 wherein the microcontroller is programmed to enable one or more of the following features: allows the output voltage to be adjusted; the output voltage to be turned off; control of the primary LLC switching frequency by the secondary to be disabled at light load or with the output turned off; and/or output short circuit and overvoltage protection.

9. The control circuit for controlling the operation of a power converter as claimed in claim 1 wherein a microcontroller comprises a PWM module driven by a digital supervision scheme and configured with a finer resolution of the output voltage adjustment by the addition of a filtered PWM signal with an ADC output signal.

10. The control circuit for controlling the operation of a power converter as claimed in claim 1 comprising a resistor R.sub.1, connected between a source of the switch and ground, said resistor is configured to act as a current sense resistor

11. The control circuit for controlling the operation of a power converter as claimed in claim 1 wherein an output filter inductor L.sub.1 connected to the switch is configured to limit ripple current through an output capacitor C.sub.2 and limits the rate of rise in the current.

12. The control circuit for controlling the operation of a power converter as claimed in claim 11 wherein a diode circulates current from the output filter inductor, L.sub.1 on turn-off of the switch to prevent avalanche breakdown.

13. The control circuit for controlling the operation of a power converter as claimed in claim 1 wherein a primary side microcontroller is interfaced with the control circuit.

14. The control circuit for controlling the operation of a power converter as claimed in claim 13 wherein the primary controller microcontroller is configured to control a primary switching frequency that can be disabled by delivering a logic signal derived from a transistor switch connected in series with the collector of a feedback optocoupler.

15. The control circuit for controlling the operation of a power converter as claimed in claim 13 wherein the primary side microcontroller is connected to an operational amplifier where the output of the operational amplifier is connected to an Analogue-to Digital Converter of the primary side microcontroller and configured to sense a variation in an input voltage for monitoring feedforward compensation in the primary side microcontroller,

16. The control circuit for controlling the operation of a power converter as claimed in claim 1 wherein a series FET linear regulator/control switch is controlled with the output of the output voltage error amplifier connected to the gate of the series FET linear regulator/control switch through a resistor.

17. A power converter comprising a switch connected to an output of the power converter and a control circuit, said control circuit comprising: a first amplifier configured to sense an output voltage of the power converter; and a second amplifier configured to derive a frequency compensated error signal output, V.sub.f1, to provide a frequency control compensation loop to an input of the power converter and an output, V.sub.g, of the second amplifier is connected to the switch of the power converter.

18. A method for controlling the operation of a power converter having a switch connected to an output of the power converter, the method comprising the steps of: configuring a first amplifier to sense an output voltage of the power converter; and configuring a second amplifier to derive a frequency compensated error signal output, V.sub.f1, to provide a frequency control compensation loop to an input of the power converter and an output, V.sub.g, of the second amplifier is connected to the switch of the power converter.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The invention will be more clearly understood from the following description of an embodiment thereof, given by way of example only, with reference to the accompanying drawings, in which:

[0024] FIG. 1 illustrates a resonant dc/dc converter with multiple transformers providing multiple isolated buck post-regulated outputs;

[0025] FIG. 2 illustrates an alternative post regulation with MOSFET connected in series with the output return path;

[0026] FIG. 3 illustrates a separate resonant converter frequency and series connected MOSFET gate voltage controllers;

[0027] FIG. 4 illustrates an integration of resonant converter frequency and series connected MOSFET gate voltage controller, according to one embodiment;

[0028] FIG. 5 illustrates a secondary controller incorporating output current limit circuit;

[0029] FIG. 6 illustrates a secondary controller incorporating digital supervision, according to one embodiment;

[0030] FIG. 7 illustrates a digitally supervised secondary controller with fine and coarse resolution output voltage references, according to one embodiment;

[0031] FIG. 8 illustrates a primary controller with automatic feedback pull-up on secondary feedback optocoupler enable, according to one embodiment;

[0032] FIG. 9 illustrates a primary controller incorporating automatic feedback pull-up and input voltage ripple feedforward, according to one embodiment; and

[0033] FIG. 10 illustrates a primary controller incorporating automatic feedback pull-up and input voltage ripple feedforward, according to another embodiment.

DETAILED DESCRIPTION OF THE DRAWINGS

[0034] FIG. 1 shows an isolated dc/dc converter topology comprising a single primary switching stage connected to a resonant tank circuit which provides the primary voltage to several transformers, T.sub.A . . . T.sub.N, all of which have their primary windings connected in parallel. Each transformer secondary is rectified and cascaded with a buck converter to deliver an output voltage. The transformers, secondary rectifiers and buck converters can be embodied as individual modules to maximize the configurability of the system. The resonant dc/dc secondary rectifiers D.sub.1A . . . N and D.sub.2A . . . N can represent diodes or MOSFET synchronous rectifiers. The inclusion of a buck converter post-regulation facilitates a wide output voltage adjustment range, individual output enable/disable and independent output protection but compromises power density, cost, complexity, efficiency and radiated electromagnetic interference.

[0035] FIG. 2 shows a circuit design to provide a bulk power range of output modules designed by replacing the buck post-regulation stage, shown in FIG. 1, with a MOSFET, Q.sub.1 connected in series with the output return. Q.sub.1 is not subjected to Pulse Width Modulation (PWM), instead it is either fully off with the output disabled, fully on with the output delivering heavy load current (>5% of rated load current) or linearly regulating with the output delivering light load current. The output filter inductor L.sub.1 limits the ripple current through the output capacitor C.sub.2 which typically has an electrolytic dielectric. L.sub.1 also serves to limit the rate of rise in the current through Q.sub.1 on application of output short circuit. Catch diode, D.sub.3 circulates the current of the output filter inductor, L.sub.1 on turn-off of Q.sub.1 which would otherwise be subjected to avalanche breakdown. The connection of Q.sub.1 in the return path allows the gate drive circuit for Q.sub.1 can be referenced to the same return as that of the synchronous rectifiers D.sub.1,2. R.sub.1, which is connected between the source of Q.sub.1 and ground acts as a current sense resistor.

[0036] A principal objective of the secondary controller of FIG. 2 is to set the current in the feedback optocoupler U.sub.1 to a level proportional to the required primary inverter switching frequency so as to maintain the output voltage, V.sub.o at the reference level. This is achieved by sensing V.sub.o using opamp U.sub.1, configured differentially as shown in FIG. 3 and deriving a frequency compensated error signal using opamp U.sub.2 which is configured as an integrator where the reference level is derived from the Zener diode D.sub.1. One of the main challenges of controlling resonant converters is that at light load current (<1% of rated output), the output increases by over 50% relative to that at heavy loads (>5% of rated output). This can be addressed by running the inverter in burst mode if the deterioration in load step response and increased audible noise is acceptable. In this topology, the series connected MOSFET can be used to keep the output voltage down at light load by operating it as a linear regulator as shown in FIG. 3 where V.sub.g is connected to the output of an integrator/error amplifier configured opamp U.sub.4. V.sub.g is clamped to the upper rail of U.sub.4 for heavy loads where the output is under the direct control of V.sub.f1 because while both compensation opamps have the sensed output voltage, V.sub.os connected to their negative inputs, the positive input to U.sub.4 is set up to be slightly higher than that of U.sub.2. Thus for heavy loads, the series connected MOSFET is turned fully on assuming V.sub.cc1 is greater than the gate source threshold voltage of the series connected MOSFET. At light loads, where the frequency cannot keep V.sub.o at the reference level and the output of U.sub.2 is clamped to the lower rail, U.sub.4 acts to decrease V.sub.g to the level where the voltage difference between the reference output voltage and the rectified output of the resonant converter, V.sub.bus in FIG. 2, is dropped across Q.sub.1 of FIG. 2.

[0037] FIG. 4 shows a control circuit according to a first aspect of the invention for controlling the series connected MOSFET switch Q.sub.1 using only two op-amps compared to the embodiment of FIG. 3. By tying the output of the frequency control loop opamp U.sub.2 to V.sub.g, automatic transfer of control between the frequency control loop and the linear regulation one is achieved. The optocoupler series resistance and the bias level V.sub.cc1 should be selected so that for heavy loads, V.sub.f1 must be greater than the gate source threshold voltage of the series connected MOSFET.

[0038] Current limit protection can be added as shown in FIG. 5 by differentially amplifying the voltage across the current sense resistor, V.sub.cs using U.sub.3, and then subtracting it from a reference and integrating and frequency compensating the resultant error signal using U.sub.4. The transfer of control between the current and voltage loops is realized by the diodes D.sub.2 and D.sub.3 connected in series with each opamp output ensuring that whichever loop is demanding the highest frequency dictates V.sub.f1. Here the fixed reference for the control loops, V.sub.cc3 is shown as derived directly from the linear regulator U.sub.5. In current limit mode, the voltage control opamp U.sub.2 is clamped to its upper rail ensuring the series connected MOSFET is turned fully on.

[0039] The addition of a digital circuit, such as a microcontroller, to supervise the secondary controller and communicate externally allows the output voltage and current limit references to be varied is shown in Error! Reference source not found. where they are generated by digital-to-analogue converters (ADC). Short circuit protection is implemented by comparing the positive output terminal voltage to a threshold to avoid any delay due to opamp slew rates and directly turning off the gate of the series connected MOSFET using logic output SD which turns on MOSFET Q.sub.1 bringing V.sub.g to ground. At light load, the output of U.sub.2 drops towards the gate threshold voltage of the series-connected MOSFET as it transitions to linear regulating mode. If the output of U.sub.2 is kept connected to V.sub.f1, the resonant converter frequency is increased to its maximum level which limits the power throughput of the primary resonant tank thereby limiting the power which can be drawn from other outputs. This is avoided by monitoring the load current sense signal, V.sub.lo using an analogue-to-digital converter. If it drops below a threshold equivalent to light load, an optocoupler feedback is disconnected by toggling the logic output signal, FB to zero. This turns off the npn Q.sub.3 off thereby turning the pnp Q.sub.2 off effectively disconnecting the output of U.sub.2 from V.sub.f1. The primary controller is designed to respond to the cutoff of the feedback optocoupler current by taking over control of the primary switching frequency. The series-connected MOSFET has sufficient power dissipation capability to drop the difference between the V.sub.bus and V.sub.o at load currents below the load current threshold for secondary frequency control. The negative output terminal voltage is monitored by potential divider, V.sub.o-S which, in combination with the load current, V.sub.lo allows the series-connected MOSFET to be turned off in the event that it is subjected to excessive dissipation.

[0040] FIG. 7, similar to FIG. 6, shows a digital supervision scheme with a finer resolution of the output voltage adjustment achieved by the addition of a filtered PWM signal with an ADC output signal.

[0041] FIG. 8 shows how the primary digital controller can interface with a feedback optocoupler. The primary optocoupler emitter voltage is input to an ADC which dictates the primary inverter switching frequency. The pnp transistor Q.sub.1 is turned on when the optocoupler collector passes current. The base resistor R.sub.3 is selected so that when FB of Error! Reference source not found. is high to enable optocoupler feedback, the current which passes through the feedback optocoupler diode, into the emitter of Q.sub.2 and out its base is sufficient to turn on Q.sub.1 of Error! Reference source not found. Thus, even with U.sub.2 of Error! Reference source not found. clamped to its upper rail, Q.sub.1 of Error! Reference source not found. is turned on with FB at high logic level thereby raising V.sub.f2 of Error! Reference source not found. to a level that can be detected by the primary controller as a indication that control of the primary switching frequency is to be dictated by V.sub.f2.

[0042] Feedforward of changes to the inverter input voltage, V.sub.in can be implemented as shown in Error! Reference source not found. or FIG. 10. V.sub.in is typically generated by a power factor correction stage in which case it has significant ripple at twice the line frequency. The ac coupled amplifier based on opamp U.sub.2 is designed to transfer frequencies in this range to its output so as to impose changes on V.sub.f2 which correct for the changes in V.sub.in. This can be done either by resistor summation as in FIG. 9 or in code in the microcontroller as in FIG. 10 where the input voltage ripple and the optocoupled feedback are separately monitored by ADC's. The primary controller microcontroller is configured to control a primary switching frequency that can be disabled by delivering a logic signal derived from a transistor switch connected in series with the collector of a feedback optocoupler. The the primary side microcontroller is connected to an operational amplifier U.sub.2 where the output of the operational amplifier is connected to an Analogue-to Digital Converter of the primary side microcontroller and configured to sense a variation in an input voltage for monitoring feedforward compensation in the primary side microcontroller.

[0043] For the analogue feedforward approach of FIG. 9, U.sub.2 is biased from the collector of Q.sub.1 to minimize the offset imposed on V.sub.f2 when the feedback optocoupler is disabled.

[0044] In the specification the terms comprise, comprises, comprised and comprising or any variation thereof and the terms include, includes, included and including or any variation thereof are considered to be totally interchangeable and they should all be afforded the widest possible interpretation and vice versa.

[0045] The invention is not limited to the embodiments hereinbefore described but may be varied in both construction and detail.