CAPACITIVE DISPLACEMENT SENSOR SYSTEM WITH INTERDIGITATED COMBS

Abstract

A capacitive displacement sensor system with interdigitated combs, includes capacitive detection in a direction perpendicular to the surfaces of the combs facing one another, the combs being subjected to a sinusoidal movement in the direction, comprising: a device for converting the capacitance delivered by the sensor into a voltage; an analog/digital converter configured to digitize the voltage delivered by the conversion device, and supply a digitized signal; and a control unit comprising: a harmonic estimator configured to estimate the amplitudes of the harmonics of order less than or equal to a maximum order based on the digitized signal and a reference angle corresponding to the instantaneous angle of the input angular frequency; and a signal reconstruction module for reconstructing the signal from the amplitudes and the reference angle that are supplied by the harmonic estimator and from the digitized signal delivered by the analog/digital converter.

Claims

1. A capacitive displacement sensor system with interdigitated combs, comprising capacitive detection in a direction (y) perpendicular to the surfaces of the combs facing one another, the combs being subjected to a sinusoidal movement (A.sub.0.sin(ωt)) in said direction (y), comprising: a device for converting the capacitance delivered by the sensor into a voltage; an analog/digital converter configured to digitize the voltage delivered by the conversion device, and supply a digitized signal (Vadc); and a control unit comprising: a harmonic estimator configured to estimate the amplitudes of the harmonics of order less than or equal to a maximum order based on the digitized signal (Vadc) and a reference angle (α) corresponding to the instantaneous angle of the input angular frequency (ωt); and a signal reconstruction module for reconstructing the signal from the amplitudes and the reference angle that are supplied by the harmonic estimator and from the digitized signal delivered by the analog/digital converter.

2. The system as claimed in claim 1, wherein the harmonic estimator comprises a phase-locked loop, locked to the digitized signal (Vadc) delivered by the analog/digital converter, delivering the reference angle (α), and an estimation module for estimating the amplitudes (k2, k3) of the harmonics of order less than or equal to the maximum order.

3. The system as claimed in claim 2, wherein the phase-locked loop comprises a phase comparator, a low-pass filter and loop corrector module and a phase accumulator, all arranged in series, the phase comparator receiving, at input, the digitized signal (Vadc) and the reference angle (α) delivered at the output of the phase accumulator, and delivering, at output, a phase error signal (EP) to the low-pass filter and loop corrector module, the low-pass filter and loop corrector module filtering the terms with high frequencies greater than a threshold and correcting the reference angle, delivering, at output, a frequency setpoint to the phase accumulator determining the reference angle by summing of elementary phase steps.

4. The system as claimed in claim 2, wherein the estimation module for estimating the amplitudes (k2, k3) of the harmonics of order less than or equal to the maximum order comprises, for each harmonic amplitude, a first multiplier multiplying the reference angle (α) by the order of the harmonic amplitude, a cosine module if the order is even or a sine module if the order is odd, receiving the output of the first multiplier at input, a second multiplier multiplying the output of the cosine or sine module by the digitized signal (Vadc), and a low-pass filter having a static gain inverse to the trigonometric expansion coefficient, delivering the harmonic amplitude (ki) of the order (i).

5. The system as claimed in claim 1, wherein the signal reconstruction module comprises: a sine module receiving the reference angle (α) delivered by the harmonic estimator at input, and delivering its sine at output; for each harmonic amplitude of order less than or equal to the maximum order, an increase module for increasing the sine of the reference angle to the power of the order, a third multiplier multiplying the output delivered by the increase module by the harmonic amplitude (k2, k3) of the order delivered by the harmonic estimator; an adder receiving the outputs of the third multipliers at input; and a subtractor configured to subtract the sum delivered by the adder from the digitized signal (Vadc).

6. The system as claimed in claim 1, operating in closed-loop mode, comprising a feedback loop feeding back the reconstructed signal (A0sin(ωt)) at output of the reconstruction module to the harmonic estimator.

7. The system as claimed in claim 4, operating in closed-loop mode, comprising a feedback loop feeding back the reconstructed signal (A0sin(ωt)) at output of the reconstruction module to the harmonic estimator, wherein the reconstructed signal replaces the input signal at input of the second multipliers and wherein correctors having an integral function replace the low-pass filters.

8. The system as claimed in claim 1, wherein the maximum order is 3.

Description

[0042] The invention will be better understood on studying a few embodiments that are described by way of completely non-limiting examples and illustrated by the appended drawing, in which:

[0043] FIG. 1 schematically illustrates the elementary capacitance of a fixed surface facing a mobile surface, according to the prior art;

[0044] FIG. 2 schematically illustrates a capacitive displacement sensor with interdigitated combs, according to the prior art;

[0045] FIG. 3 schematically illustrates a capacitive displacement sensor system with interdigitated combs, according to one aspect of the invention;

[0046] FIG. 4 schematically illustrates a capacitive displacement sensor system with interdigitated combs, according to one aspect of the invention;

[0047] FIG. 5 schematically illustrates a capacitive displacement sensor system with interdigitated combs, according to one aspect of the invention; and

[0048] FIG. 6 schematically illustrates a capacitive displacement sensor system with interdigitated combs, according to one aspect of the invention.

[0049] Throughout the figures, elements having identical references are similar.

[0050] FIG. 3 illustrates, according to one aspect of the invention, a capacitive displacement sensor system 1 with interdigitated combs, comprising capacitive detection in a direction y perpendicular to the surfaces of the combs facing one another, the combs being subjected to a sinusoidal movement A.sub.0.sin(ωt) in said direction y, comprising [0051] a device 2 for converting the capacitance delivered by the sensor 1 into a voltage; [0052] an analog/digital converter 3, or ADC in acronym form, configured to digitize the voltage V delivered by the conversion device 2, and supply
a digitized signal Vadc; and [0053] a control unit 4 comprising: [0054] a harmonic estimator 5 configured to estimate the amplitudes of the harmonics of order less than or equal to a maximum order based on the digitized signal Vadc and a reference angle a corresponding to the instantaneous angle of the input angular frequency α=ωt; and [0055] a signal reconstruction module 6 for reconstructing the signal from the amplitudes and the reference angle α that are supplied by the harmonic estimator 5 and from the digitized signal Vadc delivered by the converter 3.

[0056] Consideration will be given to capacitive detection operating along the y axis and subjected to a sinusoidal mechanical movement A.sub.0.sin(ωt). The electrical signal that is the image of the capacitance variation is affected by harmonic defects, as presented above. Other harmonic defects may be added by the device for converting capacitance C into voltage V (such as a charge amplifier). The information processing chain may be summarized as follows: [0057] the combs are subjected to a sinusoidal movement along the y axis; [0058] the capacitance delivered by the sensor 1 (charge amplifier, switched capacitors or other similar devices) is converted 2 into a voltage, followed by an analog/digital conversion 3; [0059] the digital information Vadc is then processed in an electronic control unit 4 comprising the harmonic estimator 5 and the signal reconstruction module 6.

[0060] The idea is to estimate the harmonic terms in order to be able to recover the initial displacement signal from the sensor combs. In the remainder of the description, consideration will be given to the harmonics of order 2 and of order 3, but without limitation, since the invention may be applied to higher harmonics in the same way.

[0061] It is considered that converting (with amplification) a capacitance into a voltage eliminates the DC component (DC being the acronym for direct current, corresponding to the term k0).

[0062] The higher-order terms encompass the transfer function of the conversion device 2 and of the converter 3, and A.sub.0=1 is adopted to simplify the equations, but without limitation.

[0063] The digitized signal Vadc, due to the non-linearities of the combs, is of the following form:

Vadc=k1.sin(ωt)+k2.[sin(ωt)].sup.2+k3.[sin(ωt)].sup.3

[0064] However, since sin.sup.2(ωt)=[1−cos(2ωt)]/2 and sin.sup.3(ωt)=[3sin(ωt)−sin(3ωt)]/4, the following relationship is obtained:

Vadc=[k1+¾.k3].sin(ωt)+[−½.k2].cos(2ωt)+[−¼k3].sin(3ωt)

[0065] The DC component term relating to the coefficient k2 is not retained as it has been assumed that the capacitance to voltage conversion (C.fwdarw.V) does not retain the DC component.

[0066] Terms in cos(2ωt) and sin(3ωt) appear, these being weighted by non-linearities of orders 2 and 3. A first embodiment of the estimation of the harmonics could be a DFT or FFT that makes it possible, based on the three lines at ωt, 2ωt and 3ωt, to return to the coefficients k2 and k3. Although this approach may be adopted, it exhibits the drawback of requiring performing a DFT or FFT that, if precision is desirable, may prove to be greedy from an implementation viewpoint (silicon surface, computing time).

[0067] As illustrated in FIG. 4, the harmonic estimator 5 comprises a phase-locked loop 7, locked to the digitized signal Vadc delivered by the analog/digital converter 3, delivering the reference angle α, and an estimation module 8 for estimating the amplitudes of the harmonics of order less than or equal to the maximum order.

[0068] The approach that is adopted is to use a phase-locked loop 7, or PLL in acronym form, locked to the signal coming from the analog/digital converter 3.

[0069] The phase-locked loop 7 comprises a phase comparator 9, a low-pass filter and loop corrector module 10, and a phase accumulator 11, all arranged in series, the phase comparator 9 receiving, at input, the digitized signal Vadc and the reference angle a delivered at the output of the phase accumulator 11, and delivering, at output, a phase error signal EP to the low-pass filter and loop corrector module 10, the low-pass filter and loop corrector module 10 filtering the terms with high frequencies greater than a threshold and correcting the reference angle, delivering, at output, a frequency setpoint to the phase accumulator determining the reference angle by summing of elementary phase steps.

[0070] The output of the phase accumulator is therefore the instantaneous angle of the input angular frequency α=ωt.

[0071] With the presence of the PLL 7, it is possible to carry out a coherent demodulation of the input signal Vadc, this being equivalent to carrying out the discrete Fourier transform, or DFT in acronym form, only for the frequencies of interest. The amplitude ratio of the fundamental, in combination with the loop filter of the PLL, allows the PLL to be phase-locked to the fundamental.

[0072] Moreover, the locked angle α is taken as a basis for easily creating the signals 2α and 3α, and then the terms cos(2ωt) and sin(3ωt).

[0073] The estimation module 8 for estimating the amplitudes of the harmonics of order less than or equal to the maximum order comprises, for each harmonic amplitude (in this case of order 2 and of order 3), a first multiplier 12 multiplying the reference angle a by the order of the harmonic amplitude, a cosine module 13 if the order is even or a sine module if the order is odd, receiving the output of the first multiplier 12 at input, a second multiplier 14 multiplying the output of the cosine or sine module 13 by the digitized signal Vadc, and a low-pass filter 15 having a static gain inverse to the trigonometric expansion coefficient, delivering the harmonic amplitude ki of the order i.

[0074] This harmonic estimator 5 constitutes the part estimating the harmonics. Its principle is not limited to orders 2 and 3; it may be extended to higher orders.

[0075] In the case of a harmonic estimation of the terms of orders 2 and 3, the reference signals cos(2ωt) and sin(3ωt) are multiplied by the digitized input signal Vadc. This is equivalent to estimating the power of the terms of order 2 and 3 by returning these levels to DC current: [0076] low-pass filtering makes it possible to retain the DC portion and to filter the high-frequency terms; [0077] a gain of 2 makes it possible to compensate for the factor ½ due to the multiplication of the two sinusoidal terms; and the gains of −2 or −4 make it possible to compensate for the harmonic gains (cf. equation Vadc=[k1+¾.k3].sin(ωt)+[−½k2].cos(2ωt)+[−¼.k3].sin(3ωt)).

[0078] This method makes it possible to dynamically estimate the terms k2 and k3 of the harmonic levels.

[0079] As illustrated in FIG. 5, the signal reconstruction module comprises: [0080] a sine module 16 receiving the reference angle α delivered by the harmonic estimator 5 at input, and delivering its sine at output; [0081] for each harmonic amplitude of order less than or equal to the maximum order, an increase module 17 for increasing the sine of the reference angle to the power of the order, a third multiplier 18 multiplying the output delivered by the increase module 17 by the harmonic amplitude k2, k3 of the order delivered by the harmonic estimator 5; [0082] an adder 19 receiving the outputs of the third multipliers 18 at input; and [0083] a subtractor 20 configured to subtract the sum delivered by the adder 19 from the digitized signal Vadc.

[0084] The outputs of the harmonic estimator 5 are then used by the reconstruction module 6 intended to reconstruct the linearized signal, as illustrated in FIG. 5.

[0085] The reference angle α makes it possible to recreate the terms [sin(ωt)].sup.2 and [sin(ωt)].sup.3. The principle of inverse harmonic correction consists in weighting these terms by the harmonic estimates k2 and k3 in order to subtract them from the input signal. This thus reconstructs the original movement signal Ao.sin(ωt), which may be utilized in the rest of the signal processing. This principle may easily be extended to higher harmonic orders, or limited to a particular harmonic order.

[0086] It should be noted that such a method is based on a ½ and ¾ weighting of the harmonic terms (Vadc=[k1+¾.k3].sin(ωt)+[−½k2].cos(2ωt)+[−¼.k3].sin(3ωt)). This weighting is reused inversely by the harmonic estimator 5 to obtain the coefficients k2 and k3.

[0087] More generally, this device may be considered to be in “open-loop mode”, with a bias or an imperfection in the processing stages possibly leading to an error in the estimation of the terms k2 and k3 (quantization imperfections, computation resolutions, etc.). This is all the more true when the manipulated amplitudes remain low with respect to the fundamental signal.

[0088] It is then possible to contemplate, as illustrated in FIG. 6, an alternative in “closed-loop mode”, comprising a feedback loop feeding back the reconstructed signal A0sin(ωt) at output of the reconstruction module 6 to the harmonic estimator 5.

[0089] This alternative implements two integrators 21 in the harmonic estimation portion and uses the linearized output information. The harmonic estimator 5 thus seeks directly to cancel out the harmonic terms on the output signal, and makes it possible to dynamically eliminate the targeted harmonic terms.

[0090] In the same way, this device in “closed-loop mode” may be extended to higher harmonic orders, or limited to a particular harmonic order, for example order 3.

[0091] The system makes it possible to totally eliminate the chosen harmonic terms due to the fact that it may be implemented in the form of a looped system: in this regard, this system makes the entire detection chain totally linear, including the electronic signal formatting stages, which may also add non-linearities resulting in harmonic terms: the performance of the detection stage as a whole is thus improved.

[0092] Another advantage of the present invention consists in directly utilizing the main signal, without requiring the addition of complementary signals and formatting thereof.