CIRCUIT AND METHOD FOR DAMPING SUPPLY-VOLTAGE-INDUCED OSCILLATIONS IN THE INPUT CIRCUIT OF A DC-TO-DC CONVERTER

Abstract

A circuit having a DC-to-DC converter and an input circuit connected on the line side of the DC-to-DC converter, having a first terminal and a second terminal for connection to a power supply and a third terminal and a fourth terminal for connection to the DC-to-DC converter. Between the first and third terminals, the input circle has a semiconductor element, wherein a first component terminal of the semiconductor element is connected via at least a first capacitor and a second capacitor to a second component terminal of the semiconductor element, wherein a resistance of the semiconductor element is controllable by a voltage between the first component terminal and the second component terminal.

Claims

1. A circuit, comprising: a DC-to-DC converter; and an input circuit connected on the line side of the DC-to-DC converter, which has a first terminal and a second terminal for connection to a power supply and a third terminal and a fourth terminal for connection to the DC-to-DC converter; wherein the input circuit has a semiconductor element arranged between the first terminal and the third terminal, wherein a first component terminal of the semiconductor element is connected to a second component terminal of the semiconductor element at least by a first capacitor and a second capacitor, and wherein a resistance of the semiconductor element is controllable by a voltage between the first component terminal and the second component terminal.

2. The circuit according to claim 1, wherein the semiconductor element is a field effect transistor (FET) or as a reverse polarity protection semiconductor switch.

3. The circuit according to claim 2, wherein a gate terminal of the FET is connected to a first component terminal of the first capacitor and is connected to a source terminal of the FET by a resistor of a voltage divider circuit connected in parallel with the first capacitor, wherein a second component terminal of the first capacitor and a second component terminal of a second capacitor are connected to the second terminal, and wherein a source terminal of the FET is connected to a first component terminal of the second capacitor.

4. The circuit according to claim 2, wherein the FET is configured as a metal oxide semiconductor field effect transistor (MOSFET).

5. A system, comprising: a circuit according to claim 1; and an impulse voltage generator, which has decoupling inductances, wherein the first terminal is connected to a first pole of the impulse voltage generator and the second terminal is connected to a second pole of the impulse voltage generator.

6. The system according to claim 5, wherein the first capacitor and the second capacitor are configured to dampen an oscillation generated by applying a voltage to a DC-to-DC converter in a resonant circuit comprising the decoupling inductances by increasing the resistance of the semiconductor element as a function of the voltage fluctuation, wherein the damping is configured to avoid an undervoltage shut-off of the DC-to-DC converter and/or an overload at an input protection diode.

7. A method for testing a circuit for robustness against impulse voltages, comprising: applying a voltage to an input circuit of the circuit, wherein the input circuit has a semiconductor element; and damping an oscillation generated by the application of voltage in the input circuit, which causes a voltage fluctuation in the input circuit, wherein the damping comprises an increase in the resistance of the semiconductor element controlled by the voltage fluctuation.

8. The method according to claim 7, wherein the semiconductor element is configured as a field effect transistor or as a reverse polarity protection semiconductor switch.

9. The method according to claim 8, wherein the increase in the resistance controlled by the voltage fluctuation comprises a voltage fluctuation-dependent reduction of a gate-source voltage applied to the FET.

10. The method according to claim 9, wherein a drain terminal of the FET is connected to a first pole of a voltage source; and a gate terminal of the FET is connected by a capacitor to a second pole of the voltage source, wherein a temporal acceleration of the drop in the gate potential is brought about by discharging the capacitor via a resistor.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus, are not limitive of the present invention, and wherein:

[0023] FIG. 1 is a diagram of an exemplary testing setup (according to the prior art) for impulse voltage testing;

[0024] FIG. 2 is a circuit diagram of an input circuit which can be connected on the line side of a DC-to-DC converter with reverse polarity protection and a filter for wired interference emission (according to the prior art);

[0025] FIG. 3 shows oscillations occurring during impulse voltage testing in the input circuit of FIG. 2;

[0026] FIG. 4 shows an input circuit for damping/avoiding the oscillations which can be connected on the line side of a DC-to-DC converter;

[0027] FIG. 5 shows voltages occurring during robustness testing in the input circuit of FIG. 4 and at the output of a DC-to-DC converter connected downstream of the input circuit;

[0028] FIG. 6 shows an input circuit modified in comparison to the input circuit shown in FIG. 4;

[0029] FIG. 7 shows a flowchart of a method for robustness testing of a circuit comprising a DC-to-DC converter.

DETAILED DESCRIPTION

[0030] FIG. 2 schematically illustrates a possible embodiment of an input circuit 12 of a DC-to-DC converter. The input circuit 12 comprises a first terminal 14 and a second terminal 16 for connection to a power supply (for example, 24 V). The input circuit 12 further comprises a third terminal 18 and a fourth terminal 20 for connection to the DC-to-DC converter. The first terminal 14 is connected to the third terminal 18 by means of the drain terminal 22b and the source terminal 22a of a semiconductor element 22 (FET or reverse polarity protection MOSFET).

[0031] As shown in FIG. 2, the gate terminal 22c is connected by means of the voltage divider circuit 24 to the first terminal 14 and to the second terminal 16, so that the gate potential (in quasistationary operation) is applied between the potential at the first terminal 14 and the potential at the second terminal 16 (and thus between the source potential and the ground potential). If the difference in voltage between the first terminal 14 and the second terminal 16 is sufficiently high, the channel between the source terminal 22a and the drain terminal 22b becomes conductive. In the event of wrong polarity of the first terminal 14 and the second terminal 16, the current flow through the channel and the diode 26 on the other hand is prevented. In addition, an input protection diode circuit is arranged between the first terminal 14 and the second terminal 16 for limiting the input voltage, which for example, as shown in FIG. 2, may include two Zener diodes connected in anti-series.

[0032] FIG. 3 shows a start-up behavior suitable for the input circuit 12 shown in FIG. 2 and for a DC-to-DC converter connected to the input circuit 12 when carrying out impulse voltage testing. After switching on the supply test voltage (input voltage of the input circuit 10) 28, starting from an input voltage 30 of 18 V, the DC-to-DC converter clocks the output voltage 32 from 0 V to 5 V.

[0033] Due to the decoupling inductances in the impulse voltage generator 10, the capacitances in the input circuit 12 and the negative input resistance of the DC-to-DC converter, an onset of oscillation of the input voltage 30 can be observed. In the negative half-wave of the oscillation amplitude, the input voltage 30 drops below 12 V and thus below the undervoltage cut-off threshold of the DC-to-DC converter. As a consequence, the output voltage 32 of the DC-to-DC converter breaks down and testing cannot continue.

[0034] A modified input circuit 34 for damping/avoiding such oscillations is shown in FIG. 4. The input circuit 34 comprises, as the input circuit 12 shown in FIG. 2, a first terminal 14 and a second terminal 16 for connection to a power supply and a third terminal 18 and a fourth terminal 20 for connection to the DC-to-DC converter.

[0035] The first terminal 14 is, as shown in FIG. 2, connected to the third terminal 18 by means of the drain terminal 22b and the source terminal 22a of a reverse polarity protection MOSFET 22. Similarly, the gate terminal 22c is connected to the first terminal 14 and to the second terminal 16 by means of the voltage divider circuit 24, so that the gate potential 42 (in the quasistationary operation) lies between the potential at the first terminal 14 and the potential at the second terminal 16 (and thus between the source potential 40 and the ground potential).

[0036] However, compared to the input circuit 12 shown in FIG. 2, the modified input circuit 34 is expanded by two capacitors, a first capacitor 36 between the gate terminal 22c and the second terminal 16 and a second capacitor 38 between the source terminal 22a and the second terminal 16. As shown in FIG. 4, the gate terminal 22c of the reverse polarity protection MOSFET 22 is thus connected to the source terminal 22a of the reverse polarity protection MOSFET 22 by means of the first capacitor 36 and the second capacitor 38. This creates an additional discharge path between the source terminal 22a and the gate terminal 22c by means of the capacitors 36, 38.

[0037] As shown in FIG. 5, the source potential 40 drops during the transition of the oscillation amplitude from the positive to the negative half-wave. However, the equally decreasing gate potential 42 is supported by the first capacitor 36 that is to be discharged, whereby the gate potential 42 drops more slowly as compared to the input circuit 12 shown in FIG. 2.

[0038] In other words, the voltage drop across the resistor R2 of the voltage divider circuit 24 is delayed by the time constant R1*C1, which accelerates the voltage drop across R1. If, for example, the input voltage 30 drops by 5 V within one millisecond, then at the same time R2 sees a voltage drop of 1.8 V; The voltage drop across R1 is then: R1=5 V1.8 V=3.2 V.

[0039] If the source-gate voltage was originally 5 V, it amounts to only 5 V3.2 V=1.8 V, due to the drop in the input voltage 30. As a result, the drain-source path has become significantly more resistive. During the transition of the oscillation amplitude from the positive to the negative half-wave, the source-gate voltage 44 of the reverse polarity protection MOSFET 22 drops, as shown in FIG. 5, approximately with the same slope as the input voltage 30.

[0040] As a result, the source-gate voltage is reduced and the volume resistance of the reverse polarity protection MOSFET 22 increases between the source terminal 22a and the drain terminal 22b. By increasing the volume resistance of the reverse polarity protection MOSFET 22, the drop in the source potential is curbed, as a result of which the source gate voltage 44 again stabilizes.

[0041] This has the effect that the volume resistance is again reduced, and the source potential again drops. In FIG. 5, this behavior is outlined by the wavy portions of the input voltage 30 and the source-gate voltage 44, which indicate at what point the pinch-off behavior of the reverse polarity protection MOSFET 22 begins (or ends).

[0042] The volume resistance of the reverse polarity protection MOSFET 22 acts in this area as a damping resistor in the LC resonant circuit. In the example shown in FIG. 5, the damping is sufficient to maintain the negative half-wave of the input voltage 30 above 20 V. This way, the input voltage 30 of the DC-to-DC converter remains above the undervoltage cut-off threshold of 12 V, and the output voltage 32 of the DC-to-DC converter is continuously 5 V.

[0043] Thus, an undervoltage cut-off of the DC-to-DC converter can be avoided and testing continued. Once the oscillation transitions back into the positive half-wave, the source-gate voltage 44 is recharged and the volume resistance of the reverse polarity protection MOSFET 22 drops. The intensity of the damping can thus be set to the expected oscillation frequencies and amplitudes by means of suitable dimensioning of the resistance of the voltage divider circuit 24 and the capacitors 36, 38.

[0044] In normal operation (without any testing system with decoupling inductances), as desired, the input circuit is not affected.

[0045] Further, it is understood that, as shown in FIG. 6, the reverse polarity protection MOSFET 22 could also be arranged between the second terminal 16 and the fourth terminal 20 instead of being arranged between the first terminal 14 and the third terminal 18. In addition, it is understood that instead of the reverse polarity protection MOSFET 22, other semiconductor elements whose volume resistance can be controlled by means of voltage between two component terminals may also be used, wherein the use of FETs is only one possible embodiment of the inventive teaching.

[0046] FIG. 7 shows a flow chart of a method for testing a circuit for robustness against impulse voltages. The method starts with a step 46 of applying a voltage to the input circuit 34 of the circuit. The application of the voltage comprises, for example, as shown in FIG. 5, an increase in voltage between the first terminal 14 and the second terminal 16 from 0 V to a predetermined nominal value (e.g., 24 V).

[0047] The method proceeds with a step 48 of damping an oscillation generated by applying the voltage in the input circuit 34, which causes a voltage fluctuation in the input circuit 34. As described in connection with FIGS. 3 and 5, the damping serves to avoid a drop in the input voltage 30 below an undervoltage shut-off threshold of a device switched downstream of the input circuit 34 (e.g. a DC-to-DC converter) as well as to avoid reaching the input protection diode voltage.

[0048] The damping includes in particular the temporary increase in the volume resistance of a semiconductor element arranged in the input circuit 34 when the input voltage 30 drops, e.g., by ensuring that the drop of the gate-source voltage is accelerated with respect to the circuit shown in FIG. 2, so that the source-drain-path becomes highly resistive if the source potential 40 drops.

[0049] The method concludes with the step 50 of carrying out impulse voltage robustness testing by applying an impulse voltage to the input circuit 34.

[0050] The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are to be included within the scope of the following claims.