RADIATION EMITTING SEMICONDUCTOR CHIP

Abstract

A radiation emitting semiconductor chip may include a first semiconductor layer sequence, a second semiconductor layer sequence arranged on the first semiconductor layer sequence, a first contact structure configured to inject charge carriers into the first semiconductor layer sequence, and a contact layer sequence configured to inject charge carriers into the second semiconductor layer sequence. The first contact structure and the contact layer sequence may be formed without overlapping in lateral directions in plan view. The contact layer sequence may have a sheet resistance, which increases in the direction of the first contact structure.

Claims

1. A radiation emitting semiconductor chip comprising: a first semiconductor layer sequence; a second semiconductor layer sequence arranged on the first semiconductor layer sequence; a first contact structure configured to inject charge carriers into the first semiconductor layer sequence; and a contact layer sequence configured to inject charge carriers into the second semiconductor layer sequence; wherein: the first contact structure and the contact layer sequence are formed without overlapping in lateral directions in plan view; and the contact layer sequence has a sheet resistance, which increases in direction of the first contact structure.

2. The emitting semiconductor chip according to claim 1, wherein: a second contact structure is arranged on the contact layer sequence; an electrically insulating layer is arranged in regions between the second contact structure and the contact layer sequence; and the electrically insulating layer has at least one first recess in which the second contact structure and the contact layer sequence are in electrically conductive contact.

3. The emitting semiconductor chip according to claim 2, wherein the second contact structure comprises a first sublayer and a second sublayer.

4. The emitting semiconductor chip according to claim 1, wherein the contact layer sequence comprises a first current spreading layer in direct contact with the second semiconductor layer sequence.

5. The emitting semiconductor chip according to claim 1, wherein the contact layer sequence comprises a second current spreading layer which is in regions in direct contact with the second contact structure.

6. The emitting semiconductor chip according to claim 4, wherein a height in vertical direction of the first current spreading layer is smaller than a height in vertical direction of a second current spreading layer.

7. The emitting semiconductor chip according to claim 5, wherein a cross-sectional area in vertical direction of the second current spreading layer decreases towards the first contact structure.

8. The emitting semiconductor chip according to claim 5, wherein a cross-sectional area in lateral directions of the second current spreading layer decreases towards the first contact structure.

9. The emitting semiconductor chip according to claim 4, wherein the contact layer sequence comprises a dielectric layer which is arranged in regions between the first current spreading layer and the second current spreading layer.

10. The emitting semiconductor chip according to claim 9, wherein: the dielectric layer has second recesses; and the first current spreading layer is in direct contact with the second current spreading layer in the second recesses.

11. The emitting semiconductor chip according to claim 1, wherein: the contact layer sequence comprises at least two metallic subsegments and at least one connecting layer; the connecting layer electrically conductively connects the metallic subsegments; and a resistance of the connecting layer is larger than each resistance of the metallic subsegments.

12. The emitting semiconductor chip according to claim 11, wherein the first contact structure is completely enclosed by each metallic subsegment in lateral directions.

13. The emitting semiconductor chip according to claim 11, wherein all metallic subsegments are completely enclosed by the first contact structure in lateral directions.

14. The emitting semiconductor chip according to claim 11, wherein a further dielectric layer is arranged in lateral directions between the metallic subsegments.

15. The emitting semiconductor chip according to claim 14, wherein the connecting layer is arranged between the further dielectric layer and the electrically insulating layer.

16. The emitting semiconductor chip according to claim 15, wherein a length of the connecting layer between the metallic subsegments predetermines a sheet resistance of the contact layer sequence.

17. The emitting semiconductor chip according to claim 2, wherein the first contact structure and the first recess extend parallel to one another.

18. The emitting semiconductor chip according to claim 1, wherein: an active region is arranged between the first semiconductor layer sequence and the second semiconductor layer sequence; the active region is configured to generate electromagnetic radiation; and the sheet resistance of the contact layer sequence is predetermined such that an average current density in the active region does not deviate by more than 10% from a predetermined average current density.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0089] In the following, the radiation emitting semiconductor chip will be explained in more detail with reference to the Figures by means of exemplary embodiments.

[0090] FIGS. 1, 2, 3, 4, 5, 6, 7, 8, 9, and 10 schematic sectional views of a radiation emitting semiconductor chip, each according to an exemplary embodiment,

[0091] FIGS. 11, 12, and 13 schematic top view of a radiation emitting semiconductor chip, each according to an exemplary embodiment,

[0092] FIG. 14 schematic sectional view of a radiation emitting semiconductor chip, each according to an exemplary embodiment,

[0093] FIGS. 15, 16, 17, 18, 19, and 20 schematic diagrams of a radiation emitting semiconductor chip in plan view, each according to an exemplary embodiment,

[0094] FIGS. 21, 22, 23, 24, and 25 schematic sectional views of a region of a radiation emitting semiconductor chip, each according to an exemplary embodiment, and

[0095] FIGS. 26 and 27 exemplary view of current densities for different ranges for different radiation emitting semiconductor chips.

[0096] Elements that are identical, similar or have the same effect are given the same reference signs in the Figures. The Figures and the proportions of the elements shown in the Figures are not to be regarded as to scale. Rather, individual elements can be shown exaggeratedly large for better representability and/or for better comprehensibility.

DETAILED DESCRIPTION

[0097] The radiation emitting semiconductor chip 1 according to the exemplary embodiment of FIG. 1 comprises a first epitaxial semiconductor layer sequence 2 of a first conductivity type and a second epitaxial semiconductor layer sequence 3 of a second conductivity type different from the first conductivity type. In this exemplary embodiment, the first semiconductor layer sequence 2 is formed n-doped. Furthermore, the second semiconductor layer sequence 3 is formed p-doped here. In this exemplary embodiment, the first semiconductor layer sequence 2 comprises a nitride compound semiconductor material such as GaN, with a height in vertical direction of approximately 1 μm.

[0098] An active region 4 is arranged between the first semiconductor layer sequence 2 and the second semiconductor layer sequence 3, which is configured to generate electromagnetic radiation emitted from a radiation exit surface 20 of the semiconductor chip 1 during operation. A top surface of the first semiconductor layer sequence 2 is patterned. Advantageously, electromagnetic radiation generated in the active region 4 can be coupled out particularly well in this way.

[0099] A contact layer sequence 7, an electrically insulating layer 8 and a second contact structure 6 are arranged on the second semiconductor layer sequence 3, in particular in the order indicated.

[0100] The second contact structure 6 comprises a first sublayer 10 and a second sublayer 11. The first sublayer 10 is a reflective layer, such as silver, which is arranged between the second semiconductor layer sequence 3 and the second sublayer 11. The second sublayer 11 is a metallic layer, which is formed to be solderable, for example.

[0101] Furthermore, an electrically insulating layer 8 is arranged in regions between the contact layer sequence 7 and the first sublayer 10. The electrically insulating layer 8 is in direct contact with the first sublayer 10 and the contact layer sequence 7. The electrically insulating layer 8 has a first recess 9. The first recess 9 completely penetrates the electrically insulating layer 8. The contact layer sequence 7 is in direct and electrically conductive contact with the first sublayer 10 in the first recess 9.

[0102] In this exemplary embodiment, the contact layer sequence 7 exclusively comprises a second current spreading layer 13. The second current spreading layer 13 is arranged here in direct contact with a bottom surface of the second semiconductor layer sequence 3. Furthermore, the second current spreading layer 13 is formed with ITO, for example.

[0103] A cross-sectional area in vertical direction of the second current spreading layer 13 has a step shape in the direction of the first contact structure 5. The step shape here comprises three steps 24. In the region of the step 24 closest to the first contact structure 5, the cross-sectional area in the vertical direction of the second current spreading layer 13 has a height of approximately 50 nm. In the region of the middle step 24, the cross-sectional area in vertical direction of the second current spreading layer 13 has a height of approximately 167 nm. Furthermore, the cross-sectional area in vertical direction of the second current spreading layer 13 has a height of approximately 300 nm in the region of the step 24 farthest from the first contact structure 5. That is, a cross-sectional area in vertical direction of the second current spreading layer 13 decreases in direction of the first contact structure 5. In this case, the sheet resistance of the contact layer sequence 7 increases in discrete steps in direction of the first contact structure 5.

[0104] In lateral direction spaced apart from the second contact structure 6, a third recess 21 extends through the second semiconductor layer sequence 3 to the first semiconductor layer sequence 2. The third recess 21 extends in vertical direction partly into the first semiconductor layer sequence 2 and exposes the first semiconductor layer sequence 2 partly. A first contact structure 5 is arranged in this third recess 21, which is configured to impress charge carriers into the first semiconductor layer sequence 2.

[0105] An electrically insulating separation layer 22 is arranged between the first contact structure 5 and the second contact structure 6, as well as between the first contact structure 5 and the second semiconductor layer sequence 3 and the contact layer sequence 7. In this exemplary embodiment, the separation layer 22 comprises two layers, one of the layers having Al.sub.2O.sub.3 and the other of the layers having SiO.sub.2. Furthermore, a contact enhancement layer 23 is arranged between the first contact structure 5 and the first semiconductor layer sequence 2. In this embodiment, the first contact structure 5 and the second contact structure 6 do not overlap in lateral directions in plan view. Alternatively, it is possible that the first contact structure 5 and the second contact structure 6 overlap in lateral directions in plan view.

[0106] In contrast to the exemplary embodiment of FIG. 1, the contact layer sequence 7 according to the exemplary embodiment of FIG. 2 comprises a first current spreading layer 12. The first current spreading layer 12 is arranged here in direct contact with a bottom surface of the second semiconductor layer sequence 3. Furthermore, the first current spreading layer 12 and the second current spreading layer 13 are formed with ITO, for example. The first current spreading layer 12 comprises a height in vertical direction of approximately 20 nm.

[0107] In addition, the contact layer sequence 7 includes a dielectric layer 14 arranged in regions between the first current spreading layer 12 and the second current spreading layer 13. The dielectric layer 14 is in direct contact with the first current spreading layer 12 and the second current spreading layer 13. Furthermore, the dielectric layer 14 has second recesses 15. The second recesses 15 completely penetrate the dielectric layer 14. The first current spreading layer 12 is in direct and electrically conductive contact with the second current spreading layer 13 in the second recesses 15. The dielectric layer 14 with the second recesses 15 is completely arranged between the first current spreading layer 12 and the second current spreading layer 13.

[0108] In contrast to FIG. 1, the first semiconductor layer sequence 2 in the exemplary embodiment of FIG. 3 has a step shape. The step shape here comprises two steps 24. In the region of step 24, which is arranged above the first contact structure 5, the first semiconductor layer sequence 2 has a height of approximately 1.33 μm. In the region of step 24, which is not arranged above the first contact structure 5, the first semiconductor layer sequence 2 has a height of approximately 0.67 μm. That is, a height of the first semiconductor layer sequence 2 increases towards the first contact structure 5.

[0109] By such a structured first semiconductor layer sequence 2, the number of steps 24 in the second current spreading layer 13 can be reduced. In contrast to FIG. 1, the second current spreading layer 13 comprises only two steps 24. The step 24 of the second current spreading layer 13 closest to the first contact structure 5 has a height in the vertical direction of 133 nm. The step 24 of the second current spreading layer 13 furthest away from the first contact structure 5 has a height in the vertical direction of 267 nm.

[0110] The radiation emitting semiconductor chip 1 of the exemplary embodiment of FIG. 4 does not have a third recess 21, in contrast to the semiconductor chip 1 of FIG. 2. The first contact structure 5 is arranged in direct contact on the first semiconductor layer sequence 2, in particular the radiation exit surface 20. In this exemplary embodiment, the first semiconductor layer sequence 2 is n-doped GaN and the second semiconductor layer sequence 3 is p-doped GaN.

[0111] Furthermore, the second contact structure 6 completely covers the second semiconductor layer sequence 3. Thus, the first contact structure 5 and the second contact structure 6 overlap in lateral directions in top view.

[0112] In contrast to FIG. 4, the first semiconductor layer sequence 2 according to the exemplary embodiment of FIG. 5 is n-doped InAlP with a height in vertical direction of 3 μm. In this exemplary embodiment, the second semiconductor layer sequence 3 comprises two subregions. The subregion adjacent to the first semiconductor layer sequence 2 comprises, for example, p-doped InAlP. The subregion adjacent to the contact layer sequence 7 comprises, for example, p-doped GaP.

[0113] The radiation emitting semiconductor chip 1 of the exemplary embodiment of FIG. 6 comprises, in contrast to the semiconductor chip 1 of FIG. 2, a substrate 25 which is, for example, a growth substrate for the first semiconductor layer sequence 2. The substrate 25 is, for example, a sapphire substrate and has a height in vertical direction of greater than 100 μm.

[0114] Furthermore, the first contact structure 5 is arranged in the third recess 21 in direct contact on the first semiconductor layer sequence 2. Furthermore, the first contact structure 6 does not comprise a reflective layer, such as the semiconductor chip in FIG. 2. Moreover, the second contact structure 6 extends along a main extension direction in lateral directions.

[0115] The second current spreading layer 13 of the radiation emitting semiconductor chip 1 according to the exemplary embodiment of FIG. 7 has a constant cross-sectional area in vertical direction, unlike the exemplary embodiment of FIG. 2.

[0116] A height of the first current spreading layer 12 in this exemplary embodiment is smaller than a height of the second current spreading layer 13. The height of the first current spreading layer 12 in this exemplary embodiment is approximately 20 nm. The height of the second current spreading layer 13 is approximately 200 nm in this exemplary embodiment.

[0117] A cross-sectional area in lateral directions of the second current spreading layer 13 decreases in size towards the first contact structure 5, which is described in more detail in connection with FIGS. 11 and 12.

[0118] In contrast to FIG. 7, the first semiconductor layer sequence 2 according to the exemplary embodiment of FIG. 8 is n-doped InAlP with a height in vertical direction of 3 μm. In this exemplary embodiment, the second semiconductor layer sequence 3 comprises two subregions. The subregion adjacent to the first semiconductor layer sequence 2 comprises, for example, p-doped InAlP. The subregion adjacent to the contact layer sequence 7 comprises, for example, p-doped GaP.

[0119] Further, the radiation emitting semiconductor chip 1 is free of the first current spreading layer 12. In this case, the second current spreading layer 13 is in direct contact with the second semiconductor layer sequence 3 within the second recesses 15 in the dielectric layer 14.

[0120] The contact layer sequence 7 of the radiation emitting semiconductor chip 1 according to the exemplary embodiment of FIG. 9 comprises the first current spreading layer 12 in contrast to the semiconductor chip 1 of FIG. 8.

[0121] The second current spreading layer 13 of the radiation emitting semiconductor chip 1 according to the exemplary embodiment of FIG. 10 has a constant cross-sectional area in vertical direction in contrast to the exemplary embodiment of FIG. 6, as explained for example in more detail in connection with FIG. 7.

[0122] The first current spreading layer 12 extends between the first recess 9 and the first contact structure 5 according to the exemplary embodiment of FIG. 11. In plan view, the first current spreading layer 12 overlaps with the first recess 9 in lateral directions. The dielectric layer 14 is arranged on the first current spreading layer 12, which has second recesses 15. The second current spreading layer 13 is arranged on the dielectric layer 14, which is in direct contact with the first current spreading layer 12 in the second recesses 15.

[0123] Furthermore, the second current spreading layer 13 and the dielectric layer 14 are structured so that a cross-sectional area in lateral directions of the second current spreading layer 13 is reduced in direction of the first contact structure 5. For this purpose, openings 19 are formed in the second current spreading layer 13 and the dielectric layer 14.

[0124] For example, the openings 19 are shaped such that the cross-sectional area in lateral directions of the second current spreading layer 13 tapers towards the first contact structure 5. In this embodiment, the second current spreading layer 13 structured by the openings 19 has, in plan view, a shape of a plurality of pyramids whose tops are directed towards the first contact structure 5. A base of each pyramid has, for example, a length in lateral directions of at least 10 μm and at most 30 μm. The first recess 9 and the first contact structure 5 have, for example, a minimum distance in lateral directions of at least 10 μm and at most 30 μm.

[0125] Furthermore, a region in plan view in lateral directions starting from the first contact structure 5 to the first recess 9 is free of the second current spreading layer 13. This region has a width in lateral directions of at least 10 μm and at most 30 μm.

[0126] The second recesses 15 are in addition arranged at grid points of a grid. The grid is in particular a regular hexagonal grid.

[0127] In contrast to the exemplary embodiment of FIG. 11, the openings 19 according to FIG. 12 are arranged at further grid points of a further grid. The grid is in particular a stretched hexagonal grid. Furthermore, a cross-sectional area in lateral directions of the openings 19 increases in direction of the first contact structure 5.

[0128] In the radiation emitting semiconductor chip 1 according to the exemplary embodiment of FIG. 13, the first contact structure 5 and the first recess 9 extend parallel to one another. The first contact structure 5 and the first recess 9 each have a length. In particular, the lengths are formed to be equal in size.

[0129] According to the exemplary embodiment of FIG. 14, the contact layer sequence 7 of the radiation emitting semiconductor chip 1 has, in contrast to the contact layer sequence 7 of FIG. 1, several metallic subsegments 16. Furthermore, the contact layer sequence 7 comprises at least one connecting layer 17 between directly adjacent metallic subsegments 16. The metallic subsegments 16 are in direct contact with the second semiconductor layer sequence 3. In each case, an area in lateral directions of the metallic subsegments 16 that is in direct contact with the second semiconductor layer sequence 3 decreases in size from the first recess 9 towards the first contact structure 5.

[0130] The metallic subsegments 16 are formed with silver, for example. In addition, the connecting layers 17 are formed with ITO, for example.

[0131] In the exemplary embodiment shown in FIG. 15, two metallic subsegments 16 of the same size are electrically conductively connected to one another by six connecting layers 17. A trench 26 is arranged between the metallic subsegments 16. The trench 26 has a width in lateral directions of approximately 2 μm. The first recess 9 and the first contact structure 5 are approximately 100 μm apart.

[0132] Furthermore, the connecting layers 17 each have a height in lateral directions of approximately 50 nm. In this case, the connecting layers 17 have an area portion of approximately 20% of an area of the trench 26 in plan view in lateral directions.

[0133] The radiation emitting semiconductor chip 1 according to the exemplary embodiment of FIG. 16 has four metallic subsegments 16, each of which has an area being equal in size in lateral directions. Directly adjacent subsegments 16 have a distance in lateral directions of approximately 2 μm. The first recess 9 and the first contact structure 5 have a distance of approximately 100 μm.

[0134] The connecting layers 17 arranged closest to the first contact structure 5 have, for example, an area in lateral directions that is approximately six times smaller than the connecting layers 17 arranged closest to the first recess 9. For example, the connecting layers 17 arranged in the center have an area in lateral directions that is approximately two times smaller than the connecting layers 17 arranged closest to the first recess 9. Thus, a sheet resistance of the contact layer sequence 7 effectively increases from the first recess 9 towards the first contact structure 5.

[0135] In contrast to FIG. 16, the radiation emitting semiconductor chip 1 according to the exemplary embodiments of FIGS. 17 and 18 has metallic subsegments 16 of different sizes. An area in lateral directions of the metallic subsegments 16 decreases in direction of the first contact structure 5.

[0136] According to the exemplary embodiment of FIG. 19, the first contact structure 5 extends in plan view in lateral directions along a closed shape. The closed shape is a hexagon.

[0137] The outer metallic subsegment 16 also extends in plan view in lateral directions along a closed shape corresponding to a hexagon. In this embodiment, the inner metallic subsegment 16 extends in plan view in lateral directions along a simple connected surface having a shape corresponding to a hexagon.

[0138] In this embodiment, the second contact structure 5 and/or the first recess 9 extend/extends in plan view in lateral directions along a simple connected surface having a shape of a quadrilateral.

[0139] In addition, all metallic subsegments 16 are completely enclosed by the first contact structure 5 in lateral directions.

[0140] In contrast to the first contact structure 5 of FIG. 19, the first contact structure 5 according to the exemplary embodiment of FIG. 20 is completely enclosed by each metallic subsegment 16 in lateral directions. Here, in plan view, the first contact structure 5 extends in lateral directions along a simple connected surface which has a shape of a circle.

[0141] In the embodiments of FIGS. 21, 22, 23, 24, and 25, a sectional view of a section in a region between directly adjacent metallic subsegments 16 is shown in each case.

[0142] In the embodiments of FIGS. 21, 23 and 26, a sectional view in vertical direction from the first contact structure 5 to the first recess 9 through a connecting layer 17 between directly adjacent metallic subsegments 16 is shown in each case. FIGS. 22 and 24 each show a sectional view in vertical direction from the first contact structure 5 to the first recess 9 between directly adjacent metallic subsegments 16, where the connecting layer 17 is not arranged.

[0143] Directly adjacent metallic subsegments 16 are electrically conductively connected by the connecting layer 17, as shown in FIG. 21. The connecting layer 17 between directly adjacent metallic subsegments 16 is arranged between the second semiconductor layer 3 and the electrically insulating layer 8. Furthermore, the connecting layer 17 between directly adjacent metallic subsegments 16 is in direct contact with the second semiconductor layer 3.

[0144] A trench 26 between directly adjacent metallic subsegments 16 is completely covered by the electrically insulating layer 8 in the region where the connecting layer 17 is not arranged, as shown in FIG. 22.

[0145] According to FIG. 23, a further dielectric layer 18 is arranged in lateral directions between the subsegments 16. In this case, the further dielectric layer 18 is arranged completely in regions between the metallic subsegments 16. The connecting layer 17 is further arranged between the further dielectric layer 18 and the electrically insulating layer 8.

[0146] According to FIG. 24, the further dielectric layer 18 is in direct contact with the electrically insulating layer 8, in the region where the connecting layer 17 is not arranged.

[0147] In contrast to FIG. 23, the connecting layer 17 according to FIG. 25 extends in regions in lateral directions and in regions in vertical directions. Due to such an extension, the connecting layer 17 is extended in comparison to an connecting layer 17 extending only in lateral directions between the subsegments 16, as shown for example in FIG. 23.

[0148] A current density J in the active region 4 is shown in FIG. 26 as an example for a radiation emitting semiconductor chip with only a single metallic subsegment 16. Here x indicates a position in lateral directions from the first contact structure 5 to the first recess 9. The current density J has a parabolic shape. In this case, the current density J can differ by a factor of approximately 2 to 5.

[0149] FIG. 26 shows a current density J in the active region 4 as an example of a radiation emitting semiconductor chip 1 described here, in which several metallic subsegments 16 are electrically conductively connected to one another by connecting layers 17. In this case, the current density J differs by a factor smaller than 1.5.

[0150] The features and exemplary embodiments described in connection with the Figures can be combined with each other according to further exemplary embodiments, even if not all combinations are explicitly described. Furthermore, the exemplary embodiments described in connection with the Figures can alternatively or additionally have further features according to the description in the general part.

[0151] The invention is not limited to these exemplary embodiments by the description based on the exemplary embodiments. Rather, the invention encompasses any new feature as well as any combination of features, which in particular includes any combination of features in the patent claims, even if this feature or combination itself is not explicitly stated in the patent claims or exemplary embodiments.

[0152] This patent application claims the priority of the German patent application 10 2020 114 772.4, the disclosure content of which is hereby incorporated by reference.

LIST OF REFERENCE SIGNS

[0153] 1 radiation emitting semiconductor chip [0154] 2 first semiconductor layer sequence [0155] 3 second semiconductor layer sequence [0156] 4 active region [0157] 5 first contact structure [0158] 6 second contact structure [0159] 7 contact layer sequence [0160] 8 electrically insulating layer [0161] 9 first recess [0162] 10 first sublayer [0163] 11 second sublayer [0164] 12 first current spreading layer [0165] 13 second current spreading layer [0166] 14 dielectric layer [0167] 15 second recesses [0168] 16 metallic subsegment [0169] 17 connecting layer [0170] 18 further dielectric layer [0171] 19 opening [0172] 20 radiation exit surface [0173] 21 third recess [0174] 22 electrically insulating separation layer [0175] 23 contact enhancement layer [0176] 24 steps [0177] 25 substrate [0178] 26 trench