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Mixed-mode quarter square multipliers for machine learning

10700695 ยท 2020-06-30

    Inventors

    Cpc classification

    International classification

    Abstract

    Multipliers are fundamental building blocks in signal processing, including in emerging applications such as machine learning (ML) and artificial intelligence (AI) that predominantly utilize digital-mode multipliers. Generally, digital multipliers can operate at high speed with high precision, and synchronously. As the precision and speed of digital multipliers increase, generally the dynamic power consumption and chip size of digital implementations increases substantially that makes solutions unsuitable for some ML and AI segments, including in portable, mobile, or near edge and near sensor applications. The present invention discloses embodiments of multipliers that arrange data-converters to perform the multiplication function, operating in mixed-mode (both digital and analog), and capable of low power consumptions and asynchronous operations, which makes them suitable for low power ML and AI applications.

    Claims

    1. A quarter square method of multiplying signals utilizing data converters, the method comprising: adding an at least one P signal to an at least one Q signal to generate an at least one sum signal (P+Q); generating an at least one absolute value sum signal of the at least one P+Q signal (|P+Q|); subtracting the at least one Q signal from the at least one P signal to generate an at least one subtraction signal (PQ); generating an at least one absolute value subtraction signal of the at least one PQ signal (|PQ|); squaring the at least one |P+Q| signal to generate an at least one square sum signal (|P+Q|.sup.2; and squaring the at least one |PQ| signal to generate an at least one square subtraction signal (|PQ|.sup.2.

    2. The quarter square method of multiplying signals utilizing data converters of claim 1, the method further comprising: inputting the at least one |P+Q|.sup.2 signal onto an at least one sum Digital-to-Analog-Converter (DAC) to generate an at least one square sum analog signal (|p+q|.sup.2); and inputting the at least one |PQ|.sup.2 signal onto an at least one subtracting DAC to generate an at least one square subtraction analog signal (|pq|.sup.2).

    3. The quarter square method of multiplying signals utilizing data converters of claim 2, the method further comprising: subtracting the at least one |pq|.sup.2 analog signal from the at least one |p+q|.sup.2 analog signal to generate an at least one analog product signal (4pq).

    4. The quarter square method of multiplying signals utilizing data converters of claim 2, the method further comprising: summing more than one of the at least one |p+q|.sup.2 analog signal to generate a sum of square sum analog signal (|p+q|.sup.2); summing more than one of the at least one |pq|.sup.2 analog signal to generate a sum of square subtraction analog signal (|pq|.sup.2); and subtracting the |pq|.sup.2 analog signal from the |p+q|.sup.2 analog signal to generate a scaled multiply-accumulate analog signal (4pq).

    5. The quarter square method of multiplying signals utilizing data converters of claim 1, the method further comprising: subtracting the at least one |PQ|.sup.2 signal from the at least one |P+Q|.sup.2 signal to generate an at least one product signal (4PQ); and inputting the at least one 4PQ signal onto an at least one product Digital-to-Analog-Converter (DAC) to generate an at least one product analog signal (4pq).

    6. The quarter square method of multiplying signals utilizing data converters of claim 5, the method further comprising: summing more than one of the at least one 4pq analog signals to generate a scaled multiply-accumulate analog signal (4|pq).

    7. The quarter square method of multiplying signals utilizing data converters of claim 2, the method further comprising: utilizing current mode DACs.

    8. The quarter square method of multiplying signals utilizing data converters of claim 5, the method further comprising: utilizing current mode DACs.

    9. A segmentation method of multiplying signals utilizing data converters, the method comprising: segmenting an at least one P signal into an at least one P Most-Significant-Portion signal (P.sub.MSP) and an at least one P Least-Significant-Portion signal (P.sub.LSP); segmenting an at least one Q signal into an at least one Q Most-Significant-Portion signal (Q.sub.MSP) and an at least one Q Least-Significant-Portion (Q.sub.LSP) signal; multiplying the at least one P.sub.MSP signal by the at least one Q.sub.MSP to generate an at least one MSP segment-product signal (P.sub.MSPQ.sub.MSP); multiplying the at least one P.sub.MSP signal by the at least one Q.sub.LSP to generate an at least one MSP LSP cross-segment-product signal (P.sub.MSPQ.sub.LSP); multiplying the at least one P.sub.LSP signal by the at least one Q.sub.MSP to generate an at least one LSP MSP cross-segment-product signal (P.sub.LSPQ.sub.MSP); and multiplying the at least one P.sub.LSP signal by the at least one Q.sub.LSP to generate an at least one LSP segment-product signal (P.sub.LSPQ.sub.LSP).

    10. The segmentation method of multiplying signals utilizing data converters of claim 9, the method further comprising: inputting the at least one P.sub.MSPQ.sub.MSP signal onto an at least one MSP segment-product Digital-to-Analog-Converter (DAC) to generate an at least one MSP segment-product analog signal (p.sub.MSPq.sub.MSP); inputting the at least one P.sub.MSPQ.sub.LSP signal onto an at least one MSP LSP cross-segment-product DAC to generate an at least one MSP LSP cross-segment-product analog signal (p.sub.MSPq.sub.LSP); inputting the at least one P.sub.LSPQ.sub.MSP signal onto an at least one LSP MSP cross-segment-product DAC to generate an at least one LSP MSP cross-segment-product analog signal (p.sub.LSPq.sub.MSP), and inputting the at least one P.sub.LSPQ.sub.LSP signal onto an at least one LSP segment-product DAC to generate an at least one LSP segment-product analog signal (p.sub.LSPq.sub.LSP).

    11. The segmentation method of multiplying signals utilizing data converters of claim 10, the method further comprising: scaling the at least one p.sub.MSPq.sub.MSP analog signal to generate an at least one s.sub.mp.sub.MSPq.sub.MSP analog signal wherein an at least one s.sub.m is an at least one MSP scale factor; scaling the at least one p.sub.MSPq.sub.LSP analog signal to generate an at least one s.sub.c1p.sub.MSPq.sub.LSP analog signal wherein an at least one s.sub.c1 is an at least one MSP LSP scale factor; scaling the at least one p.sub.LSPq.sub.MSP analog signal to generate an at least one s.sub.c2p.sub.LSPq.sub.MSP analog signal wherein an at least one s.sub.c2 is an at least one LSP MSP scale factor; scaling the at least one p.sub.LSPq.sub.LSP analog signal to generate an at least one s.sub.lp.sub.LSPq.sub.LSP analog signal wherein an at least one s.sub.l is an at least one LSP scale factor; and combining the at least one s.sub.mp.sub.MSPq.sub.MSP analog signal, the at least one s.sub.c1p.sub.MSPq.sub.LSP analog signal, the at least one s.sub.c2p.sub.LSPq.sub.MSP analog signal, and the at least one s.sub.lp.sub.LSPq.sub.LSP analog signal to generate an at least one product analog signal (pq).

    12. The segmentation method of multiplying signals utilizing data converters of claim 9, the method further comprising: scaling the at least one P.sub.MSPQ.sub.MSP signal to generate an at least one s.sub.mP.sub.MSPQ.sub.MSP signal wherein an at least one s.sub.m is an at least one MSP scale factor; scaling the at least one P.sub.MSPQ.sub.LSP signal to generate an at least one s.sub.c1P.sub.MSPQ.sub.LSP signal wherein an at least one s.sub.c1 is an at least one MSP LSP scale factor; scaling the at least one P.sub.LSPQ.sub.MSP signal to generate an at least one s.sub.c2P.sub.LSPQ.sub.MSP signal wherein an at least one s.sub.c2 is an at least one LSP MSP scale factor; scaling the at least one P.sub.LSPQ.sub.LSP signal to generate an at least one s.sub.lP.sub.LSPQ.sub.LSP signal wherein an at least one s.sub.1 is an at least one LSP scale factor; and combining the at least one s.sub.mP.sub.MSPQ.sub.MSP signal, the at least one s.sub.c1P.sub.MSPQ.sub.LSP signal, the at least one s.sub.c2P.sub.LSPQ.sub.MSP signal, and the at least one s.sub.lP.sub.LSPQ.sub.LSP signal to generate an at least one product signal (PQ).

    13. The segmentation method of multiplying signals utilizing data converters of claim 10, the method further comprising: utilizing current mode DACs.

    14. The segmentation method of multiplying signals utilizing data converters of claim 9, the method further comprising: inputting the at least one PQ signal onto an at least one Digital-to-Analog-Converter (DAC) to generate an at least one product analog signal (pq).

    15. The segmentation method of multiplying signals utilizing data converters of claim 14, the method further comprising: utilizing current mode DACs.

    16. The segmentation method of multiplying signals utilizing data converters of claim 9, the method further comprising: wherein the at least one Q signal is identical to the at least one P signal; wherein the at least one Q.sub.MSP signal is identical to the least one P.sub.MSP signal; and wherein the at least one Q.sub.LSP signal is identical to the least one P.sub.LSP signal.

    17. A multiplier system utilizing data-converters in an integrated circuit, the multiplier system comprising: an at least one D.sub.X digital input port for receiving an at least one digital X word; an at least one D.sub.Y digital input port for receiving an at least one digital Y word; an at least one A.sub.Rd analog reference input port for receiving an at least one I.sub.Rd analog reference current signal; an at least one A.sub.Ra analog reference input port for receiving an at least one I.sub.Ra analog reference current signal; an at least one digital multiplier (MULT), the at least one MULT comprised of the at least one D.sub.X port, the at least one D.sub.Y port, and an at least one product D.sub.XY digital output port; an at least one current mode Digital-to-Analog-Converter (iDAC), the at least one comprised of an least one digital input port (D.sub.Id), an least one analog current output port (A.sub.Od), and the at least one A.sub.Rd analog reference input port; the at least one D.sub.XT port of the at least one MULT coupled to the at least one D.sub.I port of the at least one iDAC; a plurality of the at least one A.sub.Od analog current output ports, of a plurality of the at least one iDACs, coupled to an at least one multiply-accumulate analog current port (A.sub.iMAC); an at least one current mode Analog-to-Digital-Converter (iADC), the at least one iADC comprised of an least one digital output port (D.sub.Oa), an at least one analog current input port (A.sub.Ia), and the at least one A.sub.Ra analog reference input port; the at least one A.sub.iMAC analog current port coupled to the at least one A.sub.Ia analog current input port of the at least one iADC; wherein the at least one D.sub.XY port of the at least one MULT for outputting an at least one product digital word (X.Y), the at least one X.Y digital word for being responsive to the multiplication product of the at least one X digital word by the at least one Y digital word; wherein the at least one A.sub.Od analog current port, of the at least one iDAC, for outputting an at least one product (x.y) analog current signal, the at least one x.y analog current signal for being responsive to the at least one X.Y digital word and proportional to the at least one I.sub.Rd analog reference current signal; wherein the at least one multiply-accumulate analog current port (A.sub.iMAC) for generating an at least one multiply-accumulate analog current signal (I.sub.iMAC); and wherein the at least one D.sub.oa digital port of the at least one iADC for outputting an at least one multiply-accumulate (X.Y) digital output word, the at least one X.Y digital word being responsive to the at least one I.sub.iMAC analog current signal and proportional to the at least one I.sub.Ra analog reference current signal.

    18. The multiplier system utilizing data-converters in an integrated circuit of claim 17, the multiplier system comprising: wherein the at least one digital multiplier MOLT utilizes a quarter square method of multiplying signals.

    19. The multiplier system utilizing data-converters in an integrated circuit of claim 17, the multiplier system comprising: wherein the at least one digital multiplier MULT utilizes a segmentation method of multiplying signals.

    Description

    BRIEF DESCRIPTION OF THE DRAWINGS

    (1) FIG. 1 is a simplified circuit schematic diagram illustrating a DAC utilizing a resistor string (R-string).

    (2) FIG. 2 is a simplified circuit schematic diagram illustrating an ADC utilizing a R-string.

    (3) FIG. 3 is a simplified circuit schematic diagram illustrating two DACs that share the same transfer function network wherein the transfer function network is a R-string.

    (4) FIG. 4 is a simplified circuit schematic diagram illustrating two ADCs that share the same transfer function network wherein the transfer function network is a R-string.

    (5) FIG. 5 is a simplified circuit schematic diagram illustrating embodiment of a DAC with field programmable or real-time programmable transfer function network.

    (6) FIG. 6 is a simplified circuit schematic diagram illustrating embodiment of an ADC with field programmable or real-time programmable transfer function network.

    (7) FIG. 7 is a simplified schematic diagram illustrating embodiment of plurality of mixed-mode digital-inputs to analog-voltage-output multipliers (XD.sub.iV.sub.os) comprising of a current-output DAC (iDAC) whose output supplies the reference input of a resistor-string that is shared between plurality of voltage-output DACs (vDAC).

    (8) FIG. 8 is a simplified schematic diagram illustrating an embodiment of mixed-mode digital-inputs to analog-current-output multiplier (XD.sub.iI.sub.o) that operate in current mode comprising of a first current-output DAC (iDAC) whose output supplies the reference input to a second current-output iDAC.

    (9) FIG. 9 is a simplified schematic diagram illustrating an embodiment of a matrix mixed-mode analog-current-inputs to analog-current-outputs multipliers (XI.sub.iI.sub.os) that operates in current mode comprising of a first current-output ADC (iDACs) whose digital output supplies the digital inputs of plurality of iDACs.

    (10) FIG. 10 is a simplified block diagram illustrating an embodiment of a digital-input to analog-output multiplier (X.sub.2D.sub.iA.sub.o) utilizing plurality of DACs whose input-to-output transfer functions are programmed to approximates a square function.

    (11) FIG. 11 is a simplified block diagram illustrating an embodiment of an analog-input to digital-output multiplier (X.sub.2A.sub.iD.sub.o) utilizing plurality of ADCs whose input-to-output transfer functions are programmed to approximates a square function.

    (12) FIG. 12 is a simplified block diagram illustrating an embodiment of a digital-input to analog-output multiplier (X.sub.logD.sub.iA.sub.o) utilizing plurality of DACs whose input-to-output transfer functions are programmed to approximates a logarithmic function.

    (13) FIG. 13 is a simplified block diagram illustrating an embodiment of an analog-input to digital-output multiplier (X.sub.logA.sub.iD.sub.o) utilizing plurality of ADCs whose input-to-output transfer functions are programmed to approximates a logarithmic function.

    (14) FIG. 14 is a simplified functional block diagram illustrating an embodiment of a digital-input to analog-output multiplier (X.sub.SD.sub.iA.sub.o) utilizing segmented mixed-mode multiplication (SM.sup.3) method.

    (15) FIG. 15 is a simplified functional block diagram illustrating an embodiment of an analog-input to analog-output multiplier (X.sub.SA.sub.iA.sub.o) utilizing segmented mixed-mode multiplication (SM.sup.3) method.

    (16) FIG. 16 is a simplified circuit schematic illustrating an embodiment of a signal conditioning (SC) circuit, that can be utilized for SC.sub.15A and SC.sub.15B blocks illustrated in FIG. 15 of section 15. The circuit in FIG. 16 is part of the current analog-input to current analog-output multiplier (X.sub.SI.sub.iI.sub.o) that is arranged by utilizing segmented mixed-mode multiplication (SM.sup.3) method.

    (17) FIG. 17 is a simplified circuit schematic illustrating a current analog-input to current analog output multiplier circuit, operating in subthreshold, that can be utilized as XA.sub.15 block that is illustrated in FIG. 15 of section 15. The circuit in FIG. 17 is a part of a current analog-input to current analog-output multiplier (X.sub.SI.sub.iI.sub.o) that is arranged by utilizing segmented mixed-mode multiplication (SM.sup.3) method.

    (18) FIG. 18 is a simplified circuit schematic illustrating a digital-input to current analog-output multiplying DAC, that can be utilized as DAC.sub.15A and DAC.sub.15B block that is illustrated in FIG. 15 of section 15. The circuit in FIG. 18 a part of a current analog-input to current analog-output multiplier (X.sub.SI.sub.iI.sub.o) that is arranged by utilizing segmented mixed-mode multiplication (SM.sup.3) method.

    (19) FIG. 19 is a simplified circuit schematic illustrating a digital-input to current analog-output multiplier, utilizing two current mode DACs, that can be utilized as XDA.sub.15 block that is illustrated in FIG. 15 of section 15. The circuit in FIG. 19 a part of a current analog-input to current analog-output multiplier (X.sub.SI.sub.iI.sub.o) that is arranged by utilizing segmented mixed-mode multiplication (SM.sup.3) method.

    (20) FIG. 20 is a circuit simulation showing waveforms of the current analog-input to current analog-output multiplier (X.sub.SI.sub.iI.sub.o), that is arranged utilizing segmented mixed-mode multiplication (SM.sup.3) method and illustrated in FIG. 15, which utilizes the circuits illustrated in FIGS. 16, 17, 18, and 19.

    SUMMARY OF THE DISCLOSURE

    (21) An aspect of the present disclosure is a method of operating a multiplier by utilizing mixed-mode data converters circuits, the method comprising: operating the data converters (clock free) asynchronously to provide asynchronous multiplication. Further aspect of the present disclosure is a method of operating a multiplier by utilizing mixed-mode data converters circuits, the method comprising: sharing the data converters reference network among plurality of data converters. Further aspect of the present disclosure is a method of operating a multiplier by utilizing mixed-mode data converters circuits, the method comprising: programming the data converter's reference network that utilizes at least one of resistors and current sources to arrange the data-converter's transfer function. Further aspect of the present disclosure is a method of operating a multiplier by utilizing mixed-mode data converters circuits, the method comprising: programming the data converters reference network to follow at least one of logarithmic and square function input-output transfer functions. Further aspect of the present disclosure is a method of operating a multiplier by utilizing a pair of mixed-mode data converters circuits, the method comprising: performing multiplication by summing the outputs of the pair of data converters whose input-output transfer functions are programmed logarithmically. Further aspect of the present disclosure is a method of operating a multiplier by utilizing a pair of mixed-mode data converters circuits, the method comprising: performing multiplication by subtracting an absolute value of square of sum of input signals from square of absolute value of subtraction of the input signals, wherein input-output transfer functions of the pair of data converters are programmed square function.

    (22) Another aspect of the present disclosure is a method of modifying the transfer function of a data converter, the method comprising: providing a first data converter having a first reference network defining a first input-to-output transfer function, wherein the first reference network may be shared among a plurality of data converters; and programming the first reference network to modify the first input-to-output transfer function. Further aspects of the disclosed method of modifying the transfer function of a data converter herein include the method further comprising: constructing the first reference network using one or more resistive elements; and programming the one or more resistive elements to modify first input-to-output transfer function. Further aspects of the disclosed method of modifying the transfer function of a data converter herein include the method further comprising: constructing the first reference network using one or more current sources; and programming the one or more current sources to modify first input-to-output transfer function. Further aspects of the disclosed method of modifying the transfer function of a data converter herein include the method further comprising: constructing the first reference network using one or more switched capacitor; and programming the one or more switched capacitors to modify first input-to-output transfer function. Further aspects of the disclosed method of modifying the transfer function of a data converter herein include the method further comprising: programming the first reference network such that the first input-to-output transfer function approximating a square function. Further aspects of the disclosed method of modifying the transfer function of a data converter herein include the method further comprising: applying a first input signal P to a first input port of the first data converter; and generating, at a first output port of the first data converter, a first product approximating the square of P. Further aspects of the disclosed method of modifying the transfer function of a data converter herein include the method further comprising: programming the first reference network such that the first input-to-output transfer function approximating a logarithmic function. Further aspects of the disclosed method of modifying the transfer function of a data converter herein include the method further comprising: applying a first input signal P to a first input port of the first data converter; and generating, at a first output port of the first data converter, a first product approximating the logarithm of P.

    (23) Another aspect of the present disclosure is a method of multiplying signals utilizing data converters, the method comprising: applying a first input signal (P) to a first input port of a first analog-to-digital converter (ADC); applying plurality (z) of input signals (Q.sub.Z) to plurality of reference ports (R.sub.Z) of plurality of digital-to-analog converters (DAC.sub.Z); coupling a first output port of the first ADC to plurality of digital input ports of the plurality of DAC.sub.Zs; and generating plurality of products at plurality of analog output ports of the plurality of DAC.sub.Zs, wherein the plurality of products are multiplications of the P signal by the plurality of Q.sub.Z signals. Further aspects of the disclosed the method of multiplying signals, the method further comprising: operating the first ADC in current mode. Further aspects of the disclosed the method of multiplying signals utilizing data converters, the method further comprising: operating the plurality of DAC.sub.Zs in current mode.

    (24) Another aspect of the present disclosure is a method of multiplying signals utilizing data converters, the method comprising: adding a first signal P to a second signal Q to generate a first intermediate sum P+Q and generating absolute value of the P+Q; subtracting the second signal Q from the first signal P to generate a first intermediate difference PQ and generating absolute value of the PQ; programming a first data converter and a second data converter such that the respective input-to-output transfer functions of the first and the second data converters each approximates a square function; coupling absolute value of the P+Q to a first input port of the first data converter to generate a first approximate product(P+Q).sup.2; coupling the absolute value of the PQ to a first input port of the second data converter to generate a first approximate product (PQ).sup.2; subtracting (PQ).sup.2 from (P+Q).sup.2 to generate a difference signal 4PQ; and scaling the difference signal 4PQ to generate a resultant PQ. Further aspects of the disclosed the method of multiplying signals utilizing data converters, the method further comprising: utilizing data converters comprising resistive elements; and sharing the resistive elements among a plurality of data converters. Further aspects of the disclosed the method of multiplying signals utilizing data converters, the method further comprising: utilizing current mode data converters. Further aspects of the disclosed the method of multiplying signals utilizing data converters, the method further comprising: utilizing algorithmic data converters.

    (25) Another aspect of the present disclosure is a method of multiplying signals utilizing data converters, the method comprising: programming a first data converter and a second data converter such that the respective input-to-output transfer functions of the first and the second data converters each approximates a logarithmic function; coupling a first signal P to the first data converter to generate a first approximate product log P coupling a second signal Q to the second data converter to generate second approximate product log P; and adding log P to log Q to generate a first product log(PQ). Further aspects of the disclosed the method of multiplying signals utilizing data converters, the method further comprising: programming a third data converter such that its input-to-output transfer functions approximates an anti-logarithmic function; and coupling the first product log(PQ) to the input of the third data converter to generate a second product PQ. Further aspects of the disclosed the method of multiplying signals utilizing data converters, the method further comprising: utilizing data converters comprising input-to-output transfer functions that utilize resistive elements; programming the resistor elements to program the data-converter's input-to-output transfer functions to approximate at least one of logarithmic or anti-logarithmic functions; and sharing the resistive elements among a plurality of data converters. Further aspects of the disclosed the method of multiplying signals utilizing data converters, the method further comprising: utilizing current mode data converters. Further aspects of the disclosed the method of multiplying signals utilizing data converters, the method further comprising: utilizing algorithmic data converters.

    (26) Another aspect of the present disclosure is a method of multiplying signals utilizing data converters, the method comprising: segmenting a first signal P into a first most significant portion MP and a first least significant portion LP; segmenting a second signal Q into a second most significant portion MQ and a second least significant portion LQ; multiplying MP by MQ to produce a first product MPMQ; multiplying MP by LQ to produce a second product MPLQ; multiplying MQ by LP to produce a third product MQLP; wherein at least one of the multiplying MP by MQ, multiplying MP by LQ, and multiplying MQ by LP, is performed in a mixed mode multiplication; and scaling and combining the first, second, and third products to generate a first final product PQ of the first signal P and the second signal Q. Further aspects of the disclosed the method of multiplying signals utilizing data converters, the method further comprising: multiplying LP by LQ to produce a fourth product LPLQ; and scaling and combining the fourth product with the first final product. Further aspects of the disclosed the method of multiplying signals utilizing data converters, the method further comprising: performing the mixed mode multiplication utilizing at least one multiplying digital to analog converter. Further aspects of the disclosed the method of multiplying signals utilizing data converters, the method further comprising: wherein the multiplying digital to analog converter operates in current mode. Further aspects of the disclosed the method of multiplying signals utilizing data converters, the method further comprising: performing the mixed mode multiplication utilizing at least one multiplying analog to digital converter. Further aspects of the disclosed the method of multiplying signals utilizing data converters, the method further comprising: the segmenting of the first signal P is performed in a first analog to digital converter, wherein the first most significant portion MP is digital and the first least significant portion LP is analog; and the segmenting of the second signal Q is performed in a second analog to digital converter, wherein the second most significant portion MQ is digital and the second least significant portion LQ is analog. Further aspects of the disclosed the method of multiplying signals utilizing data converters, the method further comprising: wherein the first analog to digital converter operates as an algorithmic analog to digital converter. Further aspects of the disclosed the method of multiplying signals utilizing data converters, the method further comprising: wherein the second analog to digital converter operates as an algorithmic analog to digital converter. Further aspects of the disclosed the method of multiplying signals utilizing data converters, the method further comprising: the multiplying MP by LQ to produce the second product MPLQ is performed in a first multiplying digital to analog converter; and the multiplying MQ by LP to produce the third product MQ by LP is performed in a second multiplying digital to analog converter. Further aspects of the disclosed the method of multiplying signals utilizing data converters, the method further comprising: the multiplying MP by MQ to produce the first product MPMQ is performed in a first digital multiplier.

    (27) Another aspect of the present disclosure is a quarter square method of multiplying signals utilizing data converters, the method comprising: adding an at least one P signal to an at least one Q signal to generate an at least one sum signal (P+Q); generating an at least one absolute value sum signal of the at least one P+Q signal (|P+Q|); subtracting the at least one Q signal from the at least one P signal to generate an at least one subtraction signal (PQ); generating an at least one absolute value subtraction signal of the at least one PQ signal (|PQ|); squaring the at least one |P+Q| signal to generate an at least one square sum signal (|P+Q|.sup.2; and squaring the at least one |PQ| signal to generate an at least one square subtraction signal (PQ|.sup.2. Further aspects of the disclosed quarter square method of multiplying signals utilizing data converters, the method further comprising: inputting the at least one |P+Q|.sup.2 signal to an at least one sum Digital-to-Analog-Converter (DAC) to generate an at least one square sum analog signal (|p+q|.sup.2); and inputting the at least one |PQ|.sup.2 signal to an at least one subtracting DAC to generate an at least one square subtraction analog signal (|pq|.sup.2). Further aspects of the disclosed quarter square method of multiplying signals utilizing data converters, the method further comprising: subtracting the at least one |pq|.sup.2 analog signal from the at least one |p+q|.sup.2 analog signal to generate an at least one analog product signal (4pq). Further aspects of the disclosed quarter square method of multiplying signals utilizing data converters, the method further comprising: summing more than one of the at least one |p+q|.sup.2 analog signal to generate a sum of square sum analog signal (|p+q|.sup.2); summing more than one of the at least one |pq|.sup.2 analog signal to generate a sum of square subtraction analog signal (|pq|.sup.2); and subtracting the (|pq|.sup.2) analog signal from the (|p+q|.sup.2) analog signal to generate a scaled multiply-accumulate analog signal (4|pq). Further aspects of the disclosed quarter square method of multiplying signals utilizing data converters, the method further comprising: subtracting the at least one |PQ|.sup.2 signal from the at least one |P+Q|.sup.2 signal to generate an at least one product signal (4PQ); and inputting the at least one 4PQ signal to an at least one product Digital-to-Analog-Converter (DAC) to generate an at least one product analog signal (4pq). Further aspects of the disclosed quarter square method of multiplying signals utilizing data converters, the method further comprising: summing more than one of the at least one 4pq analog signals to generate a scaled multiply-accumulate analog signal (4pq). Further aspects of the disclosed quarter square method of multiplying signals utilizing data converters, the method further comprising: utilizing current mode DACs.

    (28) Another aspect of the present disclosure is a segmentation method of multiplying signals utilizing data converters, the method comprising: segmenting an at least one P signal into an at least one P Most-Significant-Portion signal (P.sub.MSP) and an at least one P Least-Significant-Portion signal (P.sub.LSP); segmenting an at least one Q signal into an at least one Q Most-Significant-Portion signal (Q.sub.MSP) and an at least one Q Least-Significant-Portion (Q.sub.LSP) signal; multiplying the at least one P.sub.MSP signal by the at least one Q.sub.MSP to generate an at least one MSP segment-product signal (P.sub.MSPQ.sub.MsP); multiplying the at least one P.sub.MSP signal by the at least one Q.sub.LSP to generate an at least one MSP LSP cross-segment-product signal (P.sub.MSPQ.sub.LSP); multiplying the at least one P.sub.LSP signal by the at least one Q.sub.MSP to generate an at least one LSP MSP cross-segment-product signal (P.sub.LSPQ.sub.MsP); and multiplying the at least one P.sub.LSP signal by the at least one Q.sub.LSP to generate an at least one LSP segment-product signal (P.sub.LSPQ.sub.LSP). Further aspects of the disclosed segmentation method of multiplying signals utilizing data converters, the method further comprising: inputting the at least one P.sub.MSPQ.sub.MSP signal to an at least one MSP segment-product Digital-to-Analog-Converter (DAC) to generate an at least one MSP segment-product analog signal (p.sub.MSPq.sub.MSP); inputting the at least one P.sub.MSPQ.sub.LSP signal to an at least one MSP LSP cross-segment-product DAC to generate an at least one MSP LSP cross-segment-product analog signal (p.sub.MSPq.sub.LSP); inputting the at least one P.sub.LSPQ.sub.MSP signal to an at least one LSP MSP cross-segment-product DAC to generate an at least one LSP MSP cross-segment-product analog signal (p.sub.LSPq.sub.MSP); and inputting the at least one P.sub.LSPQ.sub.LSP signal to an at least one LSP segment-product DAC to generate an at least one LSP segment-product analog signal (p.sub.LSPq.sub.LSP) Further aspects of the disclosed the segmentation method of multiplying signals utilizing data converters, the method further comprising: scaling the at least one p.sub.MSPq.sub.MSP analog signal to generate an at least one s.sub.mp.sub.MSPq.sub.MSP analog signal wherein an at least one s.sub.m is an at least one MSP scale factor; scaling the at least one p.sub.MSPq.sub.LSP analog signal to generate an at least one s.sub.mp.sub.MSPq.sub.MSP analog signal wherein an at least one s.sub.m is an at least one MSP LSP scale factor; scaling the at least one p.sub.LSPq.sub.MSP analog signal to generate an at least one s.sub.mp.sub.MSPq.sub.MSP analog signal wherein an at least one s.sub.m is an at least one LSP MSP scale factor; scaling the at least one p.sub.MSPq.sub.LSP analog signal to generate an at least one s.sub.c1p.sub.MSPq.sub.LSP analog signal wherein an at least one s.sub.l is an at least one LSP scale factor; and combining the at least one s.sub.mp.sub.MSPq.sub.MSP analog signal, the at least one s.sub.c1p.sub.MSPq.sub.LSP analog signal, the at least one s.sub.c2p.sub.LSPq.sub.MSP analog signal, and the at least one s.sub.lp.sub.LSPq.sub.LSP analog signal to generate an at least one product analog signal (pq). Further aspects of the disclosed segmentation method of multiplying signals utilizing data converters, the method further comprising: scaling the at least one P.sub.MSPQ.sub.MSP signal to generate an at least one s.sub.mP.sub.MSPQ.sub.MSP signal wherein an at least one s.sub.m is an at least one MSP scale factor; scaling the at least one P.sub.MSPQ.sub.LSP signal to generate an at least one s.sub.c1P.sub.MSPQ.sub.LSP signal wherein an at least one s.sub.c1 is an at least one MSP LSP scale factor; scaling the at least one P.sub.LSPQ.sub.MSP signal to generate an at least one s.sub.c2P.sub.LSPQ.sub.MSP signal wherein an at least one s.sub.c2 is an at least one LSP MSP scale factor; scaling the at least one P.sub.LSPQ.sub.LSP signal to generate an at least one s.sub.lP.sub.LSPQ.sub.LSP signal wherein an at least one s.sub.l is an at least one LSP scale factor; and combining the at least one s.sub.mP.sub.MSPQ.sub.MSP signal, the at least one s.sub.c1P.sub.MSPQ.sub.LSP signal, the at least one s.sub.c2P.sub.LSPQ.sub.MSP signal, and the at least one s.sub.lP.sub.LSPQ.sub.LSP signal to generate an at least one product signal (PQ). Further aspects of the disclosed segmentation method of multiplying signals utilizing data converters, the method further comprising: inputting the at least one PQ signal to an at least one Digital-to-Analog-Converter (DAC) to generate an at least one product analog signal (pq). Further aspects of the disclosed segmentation method of multiplying signals utilizing data converters, the method further comprising: utilizing current mode DACs.

    DETAILED DESCRIPTION

    (29) Numerous embodiments are described in the present application and are presented for illustrative purposes only and is not intended to be exhaustive. The embodiments were chosen and described to explain principles of operation and their practical applications. The present disclosure is not a literal description of all embodiments of the disclosure(s). The described embodiments also are not, and are not intended to be, limiting in any sense. One of ordinary skill in the art will recognize that the disclosed embodiment(s) may be practiced with various modifications and alterations, such as structural, logical, and electrical modifications. For example, the present disclosure is not a listing of features which must necessarily be present in all embodiments. On the contrary, a variety of components are described to illustrate the wide variety of possible embodiments of the present disclosure(s). Although particular features of the disclosed embodiments may be described with reference to one or more particular embodiments and/or drawings, it should be understood that such features are not limited to usage in the one or more particular embodiments or drawings with reference to which they are described, unless expressly specified otherwise. The scope of the disclosure is to be defined by the claims.

    (30) Although process (or method) steps may be described or claimed in a particular sequential order, such processes may be configured to work in different orders. In other words, any sequence or order of steps that may be explicitly described or claimed does not necessarily indicate a requirement that the steps be performed in that order. The steps of processes described herein may be performed in any order possible. Further, some steps may be performed simultaneously despite being described or implied as occurring non-simultaneously (e.g., because one step is described after the other step). Moreover, the illustration of a process by its depiction in a drawing does not imply that the illustrated process is exclusive of other variations and modifications thereto, does not imply that the illustrated process or any of its steps are necessary to the embodiment(s). In addition, although a process may be described as including a plurality of steps, that does not imply that all or any of the steps are essential or required. Various other embodiments within the scope of the described disclosure(s) include other processes that omit some or all of the described steps. In addition, although a circuit may be described as including a plurality of components, aspects, steps, qualities, characteristics and/or features, that does not indicate that any or all of the plurality are essential or required. Various other embodiments may include other circuit elements or limitations that omit some or all of the described plurality.

    (31) Note that all the figures comprised of circuits, blocks, or systems illustrated in this disclosure are powered up by positive and negative power supplies, VDD and VSS (and VSS can be connected to the ground potential or zero volts for single supply applications), respectively (unless otherwise specified), and they are not shown for illustrative clarity of the disclosed figures. Terms FET is field-effect-transistor; MOS is metal-oxide-semiconductor; MOSFET is MOS FET; PMOS is p-channel MOS; NMOS is n-channel MOS; BiCMOS is bipolar CMOS; residual LSP of a signal is residual least significant portion of the signal and MSP of the signal is most significant portion of the signal where the sum of the MSP of the signal plus the residual LSP of the signal are equal to the whole signal and the MSP or residual LSP can be represented in analog or digital form or combination thereof.

    (32) All the data-converters including, analog-to-digital converters (ADC) as well as digital-to-analog converters (DAC) may not show (for illustrative clarity) a positive reference and a negative reference input, where the negative reference input can be connected to the ground potential or zero volts.

    (33) Throughout this disclosure, data-converter that are otherwise illustrated with a 2-bits of resolution for demonstrative and descriptive clarity, can have higher resolution, unless otherwise specified (e.g., utilized data-converters can have higher resolutions where 16-bits of resolution is practical). Also, for descriptive clarity some illustrations are simplified, where their improvements would be obvious to one skilled in the arts. For example, some circuit schematics are show current sources or mirrors utilizing one FET. In such instances, FETs can instead be cascaded to improve the performance of current sources such as increasing their output impedance. In some instances, analog switches are shown as single FETs with one input, one output, and a control input. In such instances, the one FET acting as a switch can be replaced with two FETs with a common input but opposite control polarity to manage the switch input's on and off voltage span and improve on-off glitch transients. Also note that other manufacturing technologies, such as Bipolar, BiCMOS, and others can utilize the disclosure in whole or part.

    (34) Also, for illustrative clarity, some of the data-converters in this disclosure are shown as sharing their transfer function network with only one other data-converter. The same transfer function network can be shared with more than two data-converters and the data-converters sharing the same transfer function network can be plurality of DACs, or plurality of ADCs, or combination of either's plurality of DACs or plurality of ADCs. Data-converters utilizing a resistor string network or switched-capacitor network to arrange their transfer function network, can share their transfer function amongst plurality of data-converters, unless otherwise specified.

    (35) In this disclosure, unless otherwise specified, the illustrated data-converters are generally asynchronous (i.e., they are clock free) which eliminates the need for a free running clock and improves dynamic power consumption with lower clock noise.

    (36) Note that the methods, systems, or circuits disclosed generally are applicable to data-converters that are synchronous (i.e., requiring clocks). For example, the comparators in the ADC, can be designed with lower offset and lower noise utilizing switched capacitors topologies. Also, instead of utilizing a resistor string to arrange the data-converters transfer function network, switched capacitor network can be utilized and they be shared amongst plurality of other data-converters.

    (37) For illustrative clarity, for n-bit data-converters that utilize resistor strings as their transfer function reference network, 2.sup.n1 switches and the respective 2.sup.n1 decoding or encoding logic control lines are shown to tap directly into each resistor along a resistor string. For higher resolution data-converters, to reduce the output routes of decoders or encoder and to reduce the chips area associated with the digital word bit width of 2.sup.n1 that selects 2.sup.n1 switches, there are other alternatives embodiments. For example, in case of a resistor string voltage DAC, a mux-tree with cascaded layers of switches (that technically perform the function of analog decoding instead of digital decoding) where each layer of the mux-tree is supplied with the data-converters n-bit digital binary input word instead of the decoded or encoded 2.sup.n1 bits.

    (38) Throughout this disclosure, data-converters and multipliers that operate in current mode generally have the following benefits: First, data-converters and multipliers operating in current mode are inherently fast. Second, current signal processing that occurs within the nodes of data-converters and multipliers, generally, have small voltage swings which enables operating the current mode data-converters and multipliers with lower power supply voltages. Third, operating at low supply voltage reduces power consumption of current mode data-converters and multipliers. Fourth, summation and subtraction functions in analog current mode is generally simple and takes small chip area. For example, summation of two analog currents could be accomplished by coupling the current signals. Depending on accuracy and speed requirements, subtraction of analog current signals could be accomplished by utilizing a current mirror where the two analog current signals are applied to the opposite side of the current mirror, for example.

    Section 1Description of FIG. 1

    (39) FIG. 1 is a simplified DAC circuit schematic whose reference network is constructed using a resistor string (R.sub.1A, R.sub.1B, R.sub.1C, R.sub.1D). The resistor string reference network generates the transfer function of a data-converter. The embodiment illustrated in FIG. 1 is arranged such that the resistors in the reference resistor string are selectively programmed in order to program the transfer function of the data-converter to, for example, follow a non-linear profile such as a square or logarithmic function. For descriptive clarity, the DAC in FIG. 1 is illustrated with only n=2 which is two bits of resolution. The DAC's resistor string in FIG. 1 generates voltage taps (V.sub.1A, V.sub.1B, V.sub.1C) that are selected by the DAC's digital input word, P.sub.D1. The digital selection of respective switches is accomplished via decoding the P.sub.D1 input bits which are applied to a logic decoder, L.sub.1A, whose decoded digital outputs select the switches (S.sub.1A, S.sub.1B, S.sub.1C). The said switches pass the selected resistor string's voltage taps (V.sub.1A, V.sub.1B, V.sub.1C) that follow a programmed profile to the DAC's analog output port, P.sub.A1. Generally, for a DAC with n-bits of resolution, the L.sub.1A would be a logic decoder that receives the DAC digital inputs as being n-bit wide, and the decoder L.sub.1A digital output word would be 2.sup.n1 wide. Similarly, there would be 2.sup.n1 programmed voltage taps along the resistor string which are digitally selected by the 2.sup.n1 switches. The top reference input port VR.sub.1B=VR.sub.+ and the bottom reference input port VR.sub.1A=VR.sub.. The upper voltage reference VR.sub.+ or full scale, and the lower reference voltage VR.sub. or zero scale, establish the range of reference voltage. As such, VR.sub.+ and VR.sub. determine the DAC analog output range spanning from zero-scale to full-scale, respectively. Note that VR.sub. can be connect to the ground or zero voltage.

    (40) In a general, the output voltage of a linear DAC can mathematically be expressed as V.sub.o=V.sub.R.sub.i=1.sup.nD.sub.i2.sup.i1 where V.sub.o is the analog output voltage of the DAC, V.sub.R is the VR.sub.+ reference voltage, n is the resolution of the DAC and D.sub.i is 0 or 1 representing the value of the i.sup.th digital input bits of the DAC.

    (41) As noted earlier, for the DAC embodiment illustrated in FIG. 1, each of the resistors in the resistor string network of the DAC are be programmed to different values which arranges the DAC's reference network to follow a non-linear transfer function profile. An example to attain a non-linear transfer function for a DAC is (an approximate) logarithmic digital input to analog output transfer function, which hereafter is called proximate logarithmic DAC. The mathematical expression for a logarithmic DAC can be approximately represented with .sub.i=1.sup.nD.sub.i2.sup.i1Log(V.sub.o/V.sub.R). In other words, for FIG. 1, Log(P.sub.A1)(P.sub.D1) where is a transfer function, P.sub.A1 represent the analog form of a signal P, and P.sub.D1 represent the digital form of the signal P.

    (42) In other embodiment of the FIG. 1, the DAC's resistor string, which establishes the transfer function of the data-converter, can be programmed to other non-linear profiles such a square transfer function. As such, an approximate digital input to square analog output transfer function would follow a square function profile. The mathematical expression for a square DAC can be approximately represented with .sub.i=1.sup.nD.sub.i2.sup.i1(V.sub.o/V.sub.R).sup.2. In other words, (P.sub.A1).sup.2(P.sub.D1), which henceforth is called proximate square DAC.

    (43) To save on chip area and achieve higher resolutions, a sub-ranging DAC can be arranged. A sub-ranging DAC (e.g., with 8-bits of resolution) comprising of an MSB DAC is supplied with the MSB bank of the digital word (e.g., first 4 MSBs), and an LSB DAC is supplied with the LSB bank digital word (e.g., the last 4 LSBs). The MSB bank would utilize a first resistor string that is programmed to be non-linear to generate a non-linear transfer function such as, for example, logarithmic or square transfer function profiles. The LSB DAC, with for example 4-bit of resolution, can be a linear binarily weighted DAC utilizing for example a second resistor string (with equal sized resistors in the resistor string) or a conventional linear R2R DAC. As such, the linear LSB DAC (while properly buffered to avoid loading errors into the MSB DAC) could linearly extrapolate between the non-linear MSB DAC sub-ranges. Accordingly, a proximate non-linear DAC is arranged having for example, a proximate logarithmic or square transfer function profiles.

    (44) Some of the benefits of embodiment in FIG. 1 are chiefly in its usage and combination in a mixed mode multiplier system which are (1) the ability to program an approximate non-linear digital input to analog output transfer function such as for example logarithmic or square functions, and (2) the same approximate input-to-output transfer function can be shared between plurality of data-converters for better matching between the data-converter channels and save on power consumption and attain smaller chip area.

    Section 2Description of FIG. 2

    (45) FIG. 2 is a simplified 2-bit ADC schematic whose reference network is also constructed using a resistor string (R.sub.2A, R.sub.2B, R.sub.2C, R.sub.2D). The embodiment illustrated in FIG. 2 is arranged such that the resistors in the reference resistor string are selectively programmed in order to program the transfer function of the data-converter to, for example, follow a non-linear profile. For clarity, the ADC in FIG. 2 is illustrated with n=2 bits of resolution and it is comprised of 2.sup.n1 comparators A.sub.2A, A.sub.2B, and A.sub.2C. The ADC's comparators compare the analog input signal P.sub.A2 with the respective voltage taps along the resistor string 2.sup.n1, which in the case of FIG. 2. are V.sub.2A, V.sub.2B, and V.sub.2C, respectively. Accordingly, a digital word is generated at the output of the 2.sup.n1 comparators (A.sub.2A, A.sub.2B, and A.sub.2C). The digital outputs of the said comparators are applied to a logic encoder, L.sub.2A, which generates the ADC's digital output signal word P.sub.A2 where the digital output word in n-bit wide. As noted, for an ADC with n-bits of resolution, there would be 2.sup.n1 programmed voltage taps along the reference resistor string network. Similarly, there would be 2.sup.n1 comparators whose first input receives P.sub.A2 and input of each of 2.sup.n1 other comparators are connected to the respective 2.sup.n1 programmed voltage taps along the reference resistor string network. The upper port of the resistor string VR.sub.2B=VR.sub.+ and the lower port of the resistor string VR.sub.2A=VR.sub. are applied to the resistor string network to set the upper reference voltage VR.sub.+ or full scale of ADC and the lower reference voltage VR.sub. or zero scale of the ADC. As such, VR.sub.+ and VR.sub. determine the ADC's input voltage (P.sub.A2) range spanning from zero-scale to full-scale, respectively. Note that VR.sub. can be connected to the ground or zero voltage.

    (46) In a typical linear ADC configuration, a general mathematical expression for an ADC's transfer function can be approximately represented as Do.sub.1.fwdarw.n=(2.sup.nV.sub.IN)/V.sub.REF where Do.sub.1.fwdarw.n is the ADC's digital output word that is n-bit wide (including Do.sub.1 as the LSB to Do.sub.n as the MSB), V.sub.IN is the ADC's analog input voltage, and V.sub.REF is the ADC's reference voltage (where VR.sub.2B=VR.sub.+ and VR.sub.2A=VR.sub.=0). Note that an input voltage increments applied to the analog input terminal of the ADC, corresponds to an LSB weight of V.sub.REF/2.sup.n.

    (47) In the embodiment illustrated in FIG. 2, each of the resistors in the resistor string network of the ADC can be programmed to different values to enable the data-converter to follow a non-linear transfer function profile. For example, an approximate logarithmic ADC, the analog input to digital output transfer function can be fashioned by proper programming the data-converter's reference network (in this case programming the value of resistors in the resistor string, which is the data-converters reference network) to follow an approximate logarithmic profile, which hereafter is called proximate logarithmic ADC. As noted earlier, the analog input to digital output transfer characteristics of a logarithmic ADC can approximately be expressed as log(P.sub.D2)(P.sub.A2).

    (48) In other embodiment of the FIG. 2, the ADC's resistor string can also be programmed to other non-linear profiles such a square transfer function. For example, an approximate analog input to square digital output transfer function can be arranged. In other words, (DO.sub.2A).sup.2(VI.sub.2A), which henceforth is called proximate square ADC.

    (49) To save on area and achieve higher resolutions, a sub-ranging or 2-step ADC can be arranged. A sub-ranging ADC (e.g., with 8-bit of resolution) comprising of an MSB ADC that generates the MSB bank of the digital output word (e.g., first 4 MSBs), and an LSB ADC that generates the LSB bank digital output word (e.g., the last 4 LSBs). The MSB non-linear ADC would utilize a first resistor string that is programmed to be non-linear to generate a non-linear MSB transfer function such as, for example, logarithmic or square transfer functions. The LSB ADC can be a linear binarily weighted ADC. As such, the linear LSB ADC would linearly extrapolate between the non-linear MSB sub-ranges, where the subranges are programmed by the non-linear MSB ADC. Accordingly, a proximate non-linear ADC is arranged having for example, a proximate logarithmic or square transfer function profiles.

    (50) Some of the benefits of embodiment in FIG. 2 is in its utilization and combination in a mixed mode multiplier system are (1) ability to program an approximate non-linear analog input to digital output transfer function such as for example logarithmic and square, and (2) share the same approximate input-to-output transfer function network between multiple data-converters that are utilized in mixed-mode multiplier system for better matching between channels and to save on power consumption and attain smaller chip area.

    Section 3Description of FIG. 3

    (51) FIG. 3 is a simplified schematic comprising of two DACs (e.g., P DAC and Q DAC), where each of the P and Q DACs have the topology described in FIG. 1 of section 1, where in FIG. 3. the same programmed transfer function network is shared between the two DACs. The embodiment illustrated in FIG. 3, similar to the one in FIG. 1, is arranged such that the resistors in the reference resistor string are selectively programmed in order to program the transfer function of the data-converter to, for example, follow a non-linear logarithmic or square function profile. Additionally, the input-to-output transfer functions, between the two DACs, match since they are derived from the same transfer function network. Besides better matching, sharing the same transfer function network between the two DACs saves on chip area and power consumption, which is a key requirement for low-power and low-cost and high-volume applications. Moreover, the shared transfer function via the resistor string would allow for one system-wide correction (e.g., calibration or trimming the resistor string) to further improve accuracy, such as in gain error or offset. The input signals of the P and Q data-converters are P.sub.D3 and Q.sub.D3 respectively (when the digital inputs of the two DACs are n-bit and m-bit wide, respectively) and the output signal of the two DACs are P.sub.A3 and Q.sub.A3, respectively. In the illustration of FIG. 3 the (bits) words width n and m of the P and Q DACs are the same, but they can be arranged to have different digital word widths. The positive reference voltage is supplied to VR.sub.3B and the negative reference voltage is supplied to VR.sub.3A.

    (52) Let's consider applying two digital words, P.sub.D and Q.sub.D, respectively to the two inputs of the two DAC embodiments illustrated in FIG. 3, where the shared reference network of the two DACs is programmed to follow an approximate logarithmic profile. Accordingly, the analog outputs of the two DACs can be summed together which would result in the equivalent of Log(P.sub.AQ.sub.A). Here, P.sub.A and Q.sub.A are the analog output representations of P.sub.D and Q.sub.D digital input word signals, respectively. This is the case because Log(P.sub.D)+Log (Q.sub.D)=Log(P.sub.AQ.sub.A).

    (53) The benefits of embodiment of FIG. 3 are the following: By utilizing mixed-mode data-converters whose transfer functions are programmed to follow a logarithmic profile, the multiplication of two digital words P.sub.D and Q.sub.D (is performed in the logarithmic domain). As such, the realization of the multiplication function as performed by the circuit schematic embodiment illustrated in FIG. 3 can be simplified to an addition operation of the two output of the two respective non-linear (logarithmic) DACs. Moreover, the sharing of the same proximate logarithmically programmed transfer function network (e.g., the sharing of the same resistor string network that is programmed logarithmically) between the two DACs saves chip area, reduces power consumption, and improves matching between the transfer function of the two logarithmic DACs which in turn would improve the accuracy of the mixed-mode multiplier. Also, the multiplication process can be performed asynchronously. A such, when the digital inputs P.sub.D and Q.sub.D are applied to the two logarithmic DAC inputs, then the summation of the two logarithmic DAC outputs generates the analog logarithmic multiplication equivalent of P.sub.AQ.sub.A without any clock delay. The response time of the digital input to analog output of this mixed mode multiplier is generally dominated by the response time of the logarithmic DAC and the analog addition function delay for the two analog logarithmic outputs.

    (54) Let's now consider the summation and subtraction of P.sub.D and Q.sub.D (which are the two input digital words P.sub.D+Q.sub.D and P.sub.DQ.sub.D, respectively) being applied to the two input ports of the two DAC embodiments illustrated in FIG. 3, whose transfer function (i.e., the resistor string network) is programmed to follow an approximate square function. Subsequently, the analog outputs of the two DACs can be subtracted from one another which would result in the equivalent of 4P.sub.AQ.sub.A. Here, P.sub.A and Q.sub.A signals are the analog output representations of P.sub.D and Q.sub.D digital inputs, respectively. This is the case because (P.sub.D+Q.sub.D).sup.2 (P.sub.DQ.sub.D).sup.24P.sub.AQ.sub.A.

    (55) Additionally, the benefits of the embodiment illustrated in FIG. 3 are the following: As it can be seen by utilizing non-linear mixed-mode data-converters, whose transfer functions are programmed to follow a square function profile, the multiplication of two digital signals P.sub.D and Q.sub.D is made efficient by being simplified to a subtraction operation of the two analog outputs of the two respective non-linear (square) DACs. Moreover, the sharing of the same proximate square programmed transfer function network (e.g., the sharing of the same resistor string network that is programmed to follow a square profile) between the two square DACs saves chip area, lowers power consumption, and improves matching between the transfer function of the two square DACs which improves the accuracy of the mixed-mode multiplier. Moreover, the multiplication process is made asynchronously. When the digital input words P.sub.D and Q.sub.D, are applied to the two square DAC inputs, then the subtraction of the two square DAC outputs that generate the analog multiplication equivalent of 4P.sub.AQ.sub.A is generated without clock delay. The response time of the digital input to analog output is generally dominated by the response time of the square DAC and the subtraction of the two analog outputs of the square DACs.

    Section 4Description of FIG. 4

    (56) FIG. 4 is a simplified schematic circuit diagram illustrating two ADCs (e.g., P ADC and Q ADC) share the same transfer function network wherein the transfer function network is a resistor string. The P and Q ADCs illustrated in FIG. 4 are arranged similar to that of the ADC topology described in FIG. 2 of section 2. Similar to FIG. 2, the embodiment illustrated in FIG. 4 programs the resistors in the reference resistor string in order to arrange the transfer function of the data-converter to follow a non-linear profile, for example such as logarithmic or square function. In FIG. 4, the same resistor string is shared between the two ADCs, which saves chip area and lowers power consumption. Moreover, the two ADC's matching with one another is improved since any imprecision is derived from the same shared transfer function network. Also, note that the shared transfer function via the resistor string would allow for one system-wide correction (e.g., calibration or trimming the resistor string) to further improve accuracy, such as in gain error or offset. The analog input of the P ADC is P.sub.A4 and the analog input of the Q ADC is Q.sub.A4. The digital output of the P ADC, that is n-bit wide is P.sub.D4. The digital output of the Q ADC, that is m-bit wide, is Q.sub.D4. In the illustration of FIG. 4, the bit words n and m of the P and Q ADCs are the same, but they can be arranged to have different bit-widths. The positive reference voltage is supplied to VR.sub.4B and the negative reference voltage is supplied to VR.sub.4A (which can be set to zero potential or ground).

    (57) Let's consider applying two analog inputs, P.sub.A and Q.sub.A, respectively to the two ADC embodiments illustrated in FIG. 4, where the shared reference network of the two ADCs is programmed to follow an approximate logarithmic function. Accordingly, the digital output generated at the output of the two ADCs can be added together in the digital domain which would result in the equivalent of Log(P.sub.DQ.sub.D). This is the case because Log(P.sub.D)+Log (Q.sub.D)Log(P.sub.DQ.sub.D). As it can be seen by utilizing mixed-mode data-converters, whose transfer functions are programmed to follow a logarithmic profile, the multiplication of two analog signals P.sub.A and Q.sub.A (is performed in the logarithmic domain and it) is simplified to a low cost simple and fast addition of two digital output words of the logarithmic ADCs. Moreover, the sharing of the same proximate logarithmically programmed transfer function network between two ADCs would saves on chip area, lowers power consumption, and improves matching between the transfer function of the two logarithmic ADCs which improved the accuracy of the mixed-mode multiplier. Moreover, the multiplication process is asynchronous. When the analog inputs P.sub.A and Q.sub.A, are applied to the two logarithmic ADCs, then the summation of the two ADC digital outputs is the logarithmic multiplication equivalent of PQ which can be generated without clock delay. The response time of the analog input to digital output of such mixed-mode multiplier is generally dominated by the response time of the logarithmic ADC.

    (58) Let's now consider the summation and subtraction of P.sub.A and Q.sub.A (which are the two input analog signals P.sub.A+Q.sub.A and P.sub.AQ.sub.A, respectively) being applied to the two inputs of the two ADCs embodiments illustrated in FIG. 4, whose transfer function (i.e., the resistor string network) is programmed to follow an approximate square function. Subsequently, the digital outputs of the two ADCs can be subtracted from one another, in the digital domain, which would result in the equivalent of 4P.sub.DQ.sub.D. Here, P.sub.A and Q.sub.A are the analog input signal's representations of the P.sub.D and Q.sub.D digital output words, respectively. This is the case because (P.sub.A+Q.sub.A).sup.2(P.sub.AQ.sub.A).sup.2 4P.sub.DQ.sub.D. Note that since the P.sub.AQ.sub.A results and P.sub.A+Q.sub.A results are taken to the power of two, the sign of the said square results is always positive, and thus simplifying the implementation of the functions of summation and subtraction of P.sub.A and Q.sub.A. As it can be seen by utilizing proximate square transfer function mixed-mode data-converters, the multiplication of two analog words P.sub.A and Q.sub.A that is performed in the square domain is efficient and simplified to a subtraction operation of the two digital output words of the two respective non-linear (square) ADCs. Moreover, the sharing of the same proximate square programmed transfer function network between the two ADCs saves chip area, reduces power consumption, and improves matching between the transfer function of the two square ADCs which improves the accuracy of the mixed-mode multiplier. Moreover, the multiplication process is asynchronous. When the analog inputs P.sub.A and Q.sub.A, are applied to the two proximate square ADC's analog inputs, then the subtraction of the two square ADC's digital output words generate the digital multiplication equivalent of 4P.sub.DQ.sub.D which is generated without clock delay. The response time of the analog input signal to digital output word is generally dominated by the response time of the proximate square ADC.

    Section 5Description of FIG. 5

    (59) FIG. 5 is a simplified circuit schematic diagram illustrating embodiment of a DAC with field programmable or real-time programmable transfer function network. To the right-hand side of the resistor string in FIG. 5 is a main DAC similar to the one described in FIG. 1 of section 1. The main DAC's n-bit wide digital input word is P.sub.D5 and its analog output is A.sub.D5.

    (60) The main DAC's transfer function is field and real-time programmable through an array of current mode DACs (iDAC). The main DAC's resistor string, is field programmable or real-time programmable by data bits T.sub.D5i (i-bit wide) and address bits T.sub.D5j(j-bit wide). The T.sub.D5i data bits are inputted to an array of iDACs, namely F.sub.5A, F.sub.5B, and F.sub.5C, where each of the respective iDAC is selected by the address bits T.sub.D5j.

    (61) The left-had side of the resistor string in FIG. 5 is a block diagram illustration of the method to provide field programmable or real-time programing of the resistor-string (main) DAC's transfer function. By sinking or sourcing programmable currents via iDACs into each of the selected voltage taps along the main DAC's resistor string reference network, the main DAC's transfer function can be re-programmed. As noted, the sinking and sourcing programmable current sourcing is accomplished by F.sub.5A, F.sub.5B, and F.sub.5C which are simplified block diagrams of the iDACs. Data bits and address bits for each of the iDACs F.sub.5A, F.sub.5B, and F.sub.5C are provided by the digital words i.sub.1, i.sub.2 and i.sub.3, respectively. For example, F.sub.5A is a simplified block diagram representing an iDAC comprising of a bank of S.sub.5B analog switches (that are digitally addressed and enabled by digital words i.sub.1) which select the binary weighted current sources (1.sub.5A bank) and steers the F.sub.5A's output currents onto node V.sub.5A of the main DAC selected resistor string voltage tap. In this example as touched upon earlier, the digital words i.sub.1 (comprising of both the address bits and data bits of each iDAC) is provided by the output of logic block L.sub.5B. The logic block L.sub.5B inputs are data bits TD.sub.5i (that is i-bit wide) and address bits TD.sub.5j (that is j-bit wide). Note that the bank of binary weighted current sources in iDACs, for example in F.sub.5A, is comprising of bi-directional current sources (connected to positive and negative bias voltages +VB.sub.5 and VB.sub.5) that sink and source currents from and to the voltage tap nodes (e.g., V.sub.5A) along the resistor string reference network. The extra circuitry associated with the field and real-time programmable iDACs, has the following benefit: It has greater flexibility to attain different non-linear transfer functions that are real-time or field programmable (e.g., logarithmic, square, or arbitrary function) for resistor-string based data-converter. As noted earlier, the main resistor string DAC of FIG. 5 illustrates only 2-bits (n=2) of resolution for the sake of descriptive clarity, but n can be more than 2 and the data-converter's resolution can practically be up to 16-bits wide. Similarly, for the number of programmable iDACs are shown (for n=2 bits) 2.sup.n1 or 3 iDACs (F.sub.5A, F.sub.5B, and F.sub.5C) shown here for clarity of illustration, whereas n can be greater than 2 (and less than 16) depending on cost-precision requirement of the applications.

    (62) The field or real-time programmable iDACs can be programmed to follow a non-linear transfer function such as logarithmic, square, or other arbitrary transfer functions. As noted earlier, for higher resolution non-linear data-converters that are cost effective, a sub-ranging data converter arrangement may be utilized. In such a sub-ranging data-converter, the non-linear MSB data-converter can be arranged similar to the circuit illustrated in FIG. 5, and the LSB data converter can be arranged as a linear binary weighted DAC. In such arrangement, the LSB data-converter, extrapolates linearly between the non-linear ranges or windows (e.g., the range or window between V.sub.5A and V.sub.5B) that are provided by the non-linear MSB data-converter, which in the case of FIG. 5 type topology would be a resistor-string main DAC. Setting aside the manufacturing non-idealities, the described transfer function here would follow an approximate non-linear transfer function where the precision of the overall data-converter is dominated by the non-linear transfer function of the MSB data-converter, and the approximation is due to the linear interpolation of the LSB data-converter.

    Section 6Description of FIG. 6

    (63) FIG. 6 is a simplified circuit schematic diagram illustrating embodiment of an ADC with field programmable or real-time programmable transfer function network. To the right of the resistor string in FIG. 6, there is the main ADC that is similar to the ADC illustrated in FIG. 2 which is described in section 2. In FIG. 6, the main ADC's analog input signal is P.sub.A6 and its digital output signal word is P.sub.D6 which is a n-bit wide digital word. Also, in FIG. 6, there is the field programmable or real-time programmable iDAC array that is to the left of the resistor string, and the iDAC array is similar to the one illustrated in FIG. 5 (to the left of FIG. 5's resistor-string) that is described in section 5. For the iDAC array section, the data bits are TD.sub.6i (i-bit wide) and the address bits are TD.sub.6j (j-bit wide). The iDAC array's analog outputs are coupled with their respective resistor-string voltage taps (e.g., V.sub.6A, V.sub.6B, and V.sub.6C) which program the transfer function of the main ADC.

    (64) For more cost effective and higher resolution non-linear ADCs, a 2-step or sub-ranging ADC can be arranged, similar in principle to that described regarding the sub-ranging DACs in section 5. As noted earlier, in a sub-ranging data-converter, a first non-linear ADC digitizes the MSBs portion of the analog input (i.e., non-linear MSB ADC) and a second ADC linearly digitizes the LSB portions of the analog input. The transfer function of the non-linear MSB ADC can be field programmed or real-time programmed to follow a non-linear transfer function such as logarithmic, square, or arbitrary function. The linear LSB ADC can be a linear binary ADC, which in effect interpolates between the non-linear ranges of the MSB ADC. As such, a field programmable or real-time programmable ADC can be arranged that follows an approximate non-linear (e.g., logarithmic, square) transfer function.

    Section 7Description of FIG. 7

    (65) FIG. 7 is a simplified schematic diagram illustrating plurality of mixed-mode digital-inputs to analog-voltage-output multipliers (XD.sub.iV.sub.os) comprising of a current-output DAC (iDAC) whose output supplies the reference input of a resistor-string shared by plurality of voltage-output DACs (vDAC). Similar to previous sections and for illustrative clarity, here, the resolution of data-converters is shown as having two bits (e.g., l=m=n=2), but l, m and n can be up to 16-bits. Moreover, the plurality of vDAC channels or Z.sub.7 channels is shown for Z.sub.7=2 channels for illustrative clarity in FIG. 7 but Z.sub.7 can be greater than 2. As noted earlier, in artificial neural networks or machine learning application, multi-channel (or matrix) multiplication is needed, where one signal needs to be multiplied cost effectively with plurality of signals at low power, small size, and with proper accuracy, which is one of the objectives of the embodiment disclosed in FIG. 7.

    (66) The P-channel iDAC's digital-inputs are P.sub.D, and its reference input current is IR.sub.7. The iDAC's output current flows out of node VR.sub.7B onto a resistor string that is shared amongst Z.sub.7 plurality of vDACs. In the P-channel iDAC section for FIG. 7, the IR.sub.7 is mirrored through M.sub.7A onto M.sub.7B and M.sub.7C which are binary weighted (e.g., b=1, c=2). The iDAC's, that is n-bit wide, selects the respective iDAC switches (e.g., S.sub.7G and S.sub.7H). The output of the iDAC switches then sum the selected iDAC's binary weighted currents (e.g., M.sub.7C and M.sub.7B) onto the iDAC output node at VR.sub.7B. Accordingly, the binary weighted P-channel iDAC input-output equation can mathematically be expressed as Io.sub.pIR.sub.7.sub.D=1.sup.nP.sub.D2.sup.D1, where Io.sub.p is the analog current output of the P-channel iDAC. Let's .sub.D=1.sup.nP.sub.D2.sup.D1=P.sub.A where P.sub.A is equivalent analog-output signal representation of P.sub.D (which is the digital-input signal of the iDAC).

    (67) The Z.sub.7 plurality of vDAC's section of FIG. 7 is similar to plurality of vDACs described in FIG. 3 of section 3.

    (68) The vDAC with Q.sub.D as its digital inputs (that are m-bit wide) is referred to as Q vDAC. The VR.sub.7B is the VR.sub.+ reference input voltage. The Q.sub.D is the Q vDAC's digital input and it is 0 or 1 representing the value of the D.sup.th digital input bits of the Q vDAC. As noted earlier, a binary weighted vDAC equation can mathematically be expressed as Vo.sub.qV.sub.R.sub.D=1.sup.mQ.sub.D2.sup.D1, where V.sub.R=VR.sub.7B and let's .sub.D=1.sup.mQ.sub.D2.sup.D1=Q.sub.A where Q.sub.A is equivalent analog-output signal representation of Q.sub.D, (which is the digital-input signal of the Q vDAC.)

    (69) Note that voltage VR.sub.7B(Io.sub.pR.sub.7), where the sum of the resistance of the resistor string is R.sub.7=R.sub.7A+R.sub.7B+R.sub.7C+R.sub.7D+ . . . .

    (70) Therefore, the output for the Q vDAC, Vo.sub.pq(Io.sub.pR.sub.7).sub.D=1.sup.mQ.sub.D2.sup.D1. Accordingly, Vo.sub.pqIR.sub.7R.sub.7.sub.D=1.sup.nP.sub.D2.sup.D1.sub.D=1.sup.mQ.sub.D2.sup.D1. Thus, (Vo.sub.pq/R.sub.7IR.sub.7)=P.sub.AQ.sub.A.

    (71) Similar to the Q vDAC, the vDAC with R.sub.D as its digital inputs (that are l-bit wide) is referred to as R vDAC. The VR.sub.7B is also the VR.sub.+ reference input voltage. The R.sub.D is the R vDAC's digital input and it is 0 or 1 representing the value of the D.sup.th digital input bits of the R vDAC. Also, the binary weighted R vDAC equation can mathematically be expressed as Vo.sub.RV.sub.R.sub.D=1.sup.lR.sub.D2.sup.D1, where V.sub.R=VR.sub.7B and let's .sub.D=1.sup.lR.sub.D2.sup.D1=R.sub.A where R.sub.A is equivalent analog-output signal representation of R.sub.D, (which is the digital-input signal of the R vDAC).

    (72) Similarly, the output for the R vDAC, Vo.sub.pr(Io.sub.pR.sub.7).sub.D=1.sup.mQ.sub.D2.sup.D1. Accordingly, Vo.sub.prIR.sub.7R.sub.7.sub.D=1.sup.nP.sub.D2.sup.D1.sub.D=1.sup.lR.sub.D2.sup.D1. Thus, (Vo.sub.pr/R.sub.7)(IR.sub.7)=P.sub.AR.sub.A.

    (73) In summary, P.sub.D's analog equivalent which is P.sub.A is multiplied by Q.sub.D's analog equivalent which is Q.sub.A as well as R.sub.D's analog equivalent which is R.sub.A. As such, the resulting P.sub.AQ.sub.A and P.sub.AR.sub.A are generated using the same resistor string amongst 2-vDAC channels, namely the R and the Q DACs. As noted earlier, the same resistor string can be shared amongst Z.sub.7 plurality of vDACs (more than 2 channels) which saves area, power, with improved matching between channels that share the same input-output transfer function (established by the shared resistor string).

    (74) In summary and in addition to the general benefits of this disclosure listed in the Background section, the benefits of the embodiment illustrated in the simplified FIG. 7 are (1) plurality of vDACs can share the same resistor string and tap into the same resistor string's voltage segments. As such, the P.sub.A that is generated from the iDAC can be then multiplied with plurality of signals. This would be a useful feature for machine learning or artificial neural networks that require matrix multiplication where one column signal such as one P.sub.A is multiplied with multiple rows of signals such as Q.sub.A, R.sub.A, and more. As noted earlier, besides saving chip area and lowering power consumption for sharing the same resistor-string, the matching between the plurality of vDACs that share the same resistor string is improved. (2) mixed-mode multiplication is arranged such that a multiplier XD.sub.iV.sub.o accepts digital inputs and generates a voltage output, (3) the XD.sub.iV.sub.o is fabricated in standard CMOS where the resistor string, that facilitates the voltage output generations, can be made of existing polysilicon on digital CMOS process, (4) the dynamic response of the multiplier is enhanced since the iDAC operates in current mode which is inherently fast, and the vDAC speed is dominated by a RC time constant at nodes VR.sub.7B and at the output of the multiplier that generates the P.sub.AQ.sub.A, (5) the non-trimmed precision of the multiplier would be dominated by the matching of iDAC current mirrors such as for example M.sub.7B and M.sub.7C and the matching of resistors in the resistor string of vDAC. (6) utilizing lower resolution data-converters, that occupy smaller areas, but have higher accuracy due to higher matching between binary weighted current sources or segmented current sources can be utilized in the data-converters, which would yield higher accuracy for the P.sub.AQ.sub.A multiplication results at lower chip cost.

    (75) Note that it would be obvious to one skilled in the art to improve the precision of iDAC by, for example, utilizing current source segmentation, cascading reference current mirrors, and or boot-strapping the current reference to track the voltage VR.sub.7B Also, as noted before, it would be obvious to one skilled in the art, to increase the resolution of the DACs utilizing sub-ranging methods, or to save chip area in the vDAC's resistor string's switch decoding section, by for example, cascading in layers of switches instead of parallel taping the full 2.sup.m1 logic decoded switches onto the resistor string network (e.g., S.sub.7A, S.sub.7B, S.sub.7C, etc.).

    Section 8Description of FIG. 8

    (76) FIG. 8 is a simplified schematic diagram illustrating a mixed-mode digital-inputs to analog-current-output multiplier (XD.sub.iI.sub.o) that operates in current-mode comprising of a first current-output DAC (iDAC) whose output supplies the reference input to a second current-output iDAC.

    (77) Similar to the iDAC description provided in section 7, the first iDAC in FIG. 8 illustrates digital-inputs P.sub.D (that is n-bit wide), and reference input current is IR.sub.8A as well as a bias current IR.sub.8B. One of the beneficial features of this disclosure is the arrangement of the coupling the first iDAC's output current terminal with the analog reference input terminal of the second iDAC at node P.sub.8, which is described next.

    (78) In the first iDAC, the IR.sub.8 is mirrored through iDAC's current sources (e.g., M.sub.8E onto M.sub.8F and M.sub.8G) which are binary weighted (e.g., f=1, g=2). The iDAC's P.sub.D, that is n-bit wide, selects the first iDAC switches (e.g., S.sub.8C and S.sub.8D) that sum the respectively selected iDAC output node selected iDAC's binary weighted currents (e.g., M.sub.8F and M.sub.8G) onto the iDAC output node at P.sub.8. The second iDAC's reference input current is supplied by the first iDAC current output at node P.sub.8, which concurrently supplies the second iDAC's binary weighted current sources (e.g., M.sub.8C and M.sub.8D where c=1 and d=2). The respectively selected second iDAC binary weighted current sources are summed at the second iDAC's output (P.sub.AQ.sub.A) after being selected by the second iDAC switches (e.g., S.sub.8A and S.sub.8B). The ratio of IR.sub.8A and IR.sub.8B currents as well as the ratio W/Ls of M.sub.8A and M.sub.8B (e.g., the a, b ratios) establish the VGS.sub.M8A that provides sufficient drain-to-source voltage (VDS) head-room for the first iDAC current sources (e.g., M.sub.8F and M.sub.8G) as well as enough gate-to-source voltage (VGS) for the second iDAC current sources (M.sub.8C and M.sub.8D). Moreover, setting aside normal manufacturing related device mismatches, the disclosed arrangement in FIG. 8 helps VDS of the first iDAC current sources to match to a first order (e.g., matched VDS between M.sub.8E M.sub.8F and M.sub.8G). Also, in the disclosed arrangement in FIG. 8, the first iDAC's switch terminal voltages can be programmed by VB.sub.8C to track the voltage at P.sub.8, which lowers glitches and improves the iDAC's switches (e.g., S.sub.8A and S.sub.8B) dynamic response

    (79) In addition to the general benefits of this disclosure listed in the Background section, the benefits of the embodiment illustrated in the simplified FIG. 8 are: (1) routing the first iDAC analog output current signal P.sub.A to the second iDAC's reference input terminal through a hand-off current mirror would burden the XD.sub.iI.sub.o with its mismatches, delay, and extra size. This is due to the sizing requirement of the hand-off current mirror with respect to the second iDAC's binary weighted current sources. The disclosed arrangement of circuit illustrated in FIG. 8 avoids the hand-off current mirror and its burdens, by providing the first iDAC's analog output current directly onto the second iDAC's reference input terminal, (2) the XD.sub.iI.sub.o's signal processing is all in current mode and or via digital switching (i.e., fast logic). Steering signals in current mode swings with smaller voltage, which makes current mode signal processing fast, enables XD.sub.iI.sub.o to run fast, (3) small voltage swings in current mode signal processing enables low power supply operations which enables XD.sub.iI.sub.o to operate with low power supply voltages, (d) there are no passive devices in the embodiment of FIG. 8, and as such there is no need for resistors or capacitors, which reduces manufacturing size and cost, (4) the precision of XD.sub.iI.sub.o would depend on the matching of the first iDAC's current sources amongst themselves and the matching of the second iDAC's current sources amongst themselves, (5) utilizing lower resolution data-converters, that occupy smaller areas, but have higher accuracy due to higher matching between the binary weighted current sources or segmented current sources, would yield higher accuracy P.sub.AQ.sub.A multiplication at lower cost.

    (80) As noted earlier, the disclosure in FIG. 8 is illustrated with two bits of resolution for descriptive clarity but the topology can provide higher resolutions data converters (more resolution for the XD.sub.iI.sub.o). The precision of the first and second iDACs by for example utilizing current source segmentation, or cascading the iDAC's current mirrors. Bias voltage of the second terminal of the first and second iDAC's switches can be connected to different bias voltages or VSS depending on cost-performance requirement (e.g., VB.sub.8C can be connect to VSS and the other terminal of S.sub.8A and S.sub.8B can be connected to another bias voltage other than VSS as shown in FIG. 8)

    Section 9Description of FIG. 9

    (81) FIG. 9 is a simplified schematic diagram illustrating a matrix mixed-mode current analog-inputs to current analog-outputs multipliers (XI.sub.iI.sub.os) that operates in current mode comprising of a first current-output ADC (iDACs) digital output supplies the digital inputs of more than one iDACs. Accordingly, the matrix XI.sub.iI.sub.os multiplies a single iADC analog-current input (P.sub.A) by plurality of iDAC's analog-currents (e.g., R.sub.A, Q.sub.A, etc.) that are inputted to the reference terminal of plurality of iDACs (e.g., Q iDAC, R iDAC, etc.). Similar to previous sections and for clarity of illustration, the data-converters resolution shown here are 2-bits, but resolution can be up to 16-bits, for example. Note also that for clarity of illustration, FIG. 9 shows only two iDAC's digital inputs receiving the iADC's digital-outputs, but the disclosure is applicable to plurality of (more than two) iDACs receiving their digital input from the single iADC. This matrix multiplication feature is particularly useful in machine learning or artificial engineering applications.

    (82) In FIG. 9. an iADC's reference current, IR.sub.9 is applied to M.sub.9E which is mirrored and scaled (in thermometer arrangement) onto M.sub.9H, M.sub.9G, M.sub.9F. Also in FIG. 9, the iADC analog-current input (P.sub.A) is mirrored by M.sub.9A onto M.sub.9B, M.sub.9G, M.sub.9D where the mirrored P.sub.A input current signal is compared by thermometer reference currents of M.sub.9H, M.sub.9G, M.sub.9F respectively (e.g., thermometer scaling f=1, g=2, h=3). The logic circuit L.sub.9A comprising of comparator and encoder functions that receives the resultant respective 2.sup.n1 (e.g., For n=2 there are 2.sup.n1=3) current analog input signal to current reference signal differences, and accordingly, the L.sub.9A outputs the iADC digital output word P.sub.D that is n-bit wide (e.g., n=2 bits). The digital output P.sub.D is the digital representation of P.sub.A that is inputted to plurality of iDACs (e.g., one iDAC with R.sub.A current analog signal and the other iDAC with Q.sub.A current analog signal supplying the analog reference signal to the respective iDACs). Note that other current mode iADC architectures, such as gray-code or algorithmic can be utilized here as well.

    (83) The iDACs in FIG. 9 are similar to the iDACs described in sections 7 and 8. Let Z.sub.9 be the plurality number of iDACs (e.g., Z.sub.9=2 in FIG. 9). The plurality of iDAC's inputs receive the P.sub.D9 digital word (e.g., two bit wide for n=2), and the reference of each of the plurality of iDACs (e.g., for Z.sub.9=2 where one iDAC is the R iDACs and the other is the Q iDAC) are inputted with plurality of analog inputs (e.g., two inputs R.sub.A and Q.sub.A supplying the reference signal to R iDAC and Q iDAC, respectively). The analog outputs of the plurality of iDACs generate Q.sub.A9P.sub.A9 and R.sub.A9P.sub.A9, respectively. (e.g., for Z.sub.9=2 the multiplication matrix has Z.sub.9=2 rows and 1 column, where the Z.sub.9 row entries are Q.sub.A9 and R.sub.A9 and the one column entry is P.sub.A9).

    (84) Note also that it would be obvious to one skilled in the art to improve accuracy of the data-converters by current source segmentation and or cascading the current mirror that arrange the reference network of the data-converters. Also note that it would be obvious to one in the art to utilize sub-ranging current-mode data-converters to increase the resolution of data-converters cost effectively.

    (85) In addition to the general benefits of this disclosure listed in the Background section, the benefits of the embodiment illustrated in the simplified FIG. 9 are: (1) the XI.sub.iI.sub.o's signal processing is in current mode and or via digital switching (i.e., fast logic). Steering signals in current mode swings nodes with smaller voltage, which makes current mode signal processing fast, and hence enables XI.sub.iI.sub.o to run fast, (3) small voltage swings in current mode signal processing enables low power supply operations which enables XI.sub.iI.sub.o to operate with low power supply voltages, (d) there are no passive devices in the embodiment of FIG. 9, and as such there is no need for resistors or capacitors, which reduces die size and chip cost, (4) the precision of XI.sub.iI.sub.o would depend on the matching of the data-converter's current sources amongst themselves. Moreover, utilizing lower resolution data-converters would occupy smaller areas, but such data-converters having higher accuracy due to their higher matching binary weighted current sources or segmented current sources, would yield higher accuracy P.sub.AQ.sub.A multiplication at lower cost.

    Section 10Description of FIG. 10

    (86) FIG. 10 is a simplified block diagram illustrating a digital-input to analog-output multiplier (X.sub.2D.sub.iA.sub.o) utilizing two DACs whose input-to-output transfer functions are programmed to approximates a square function. The multiplication function illustrated in FIG. 10 is performed relying on the quarter square principle, which was described earlier in this disclosure.

    (87) In FIG. 10, a first digital input signal P.sub.D10 (that is n-bit wide) and second digital input signal Q.sub.D10 (that is m-bit wide) are applied to a logic circuit L.sub.10 which generates a digital absolute value summation signals |P.sub.D10+Q.sub.D10| (that is m1-bit wide) and a digital absolute value subtraction signal |P.sub.D10Q.sub.D10| (that is n1-bit wide). Then, |P.sub.D10+Q.sub.D10| and |P.sub.D10Q.sub.D10| digital signals are applied to a first proximate square data-converter DAC.sub.10B and a second proximate square data-converter DAC.sub.10A, respectively. In accordance with the proximate square transfer function profile of the first and second data-converters, DAC.sub.10A outputs the analog equivalent signal of (|P.sub.A10Q.sub.A10|).sup.2 and DAC.sub.10B outputs the analog equivalent signal of (|P.sub.A10+Q.sub.A10|).sup.2. The analog circuit A.sub.10 subtracts the analog outputs of DAC.sub.10A and DAC.sub.10B from one another and generates the analog representation of the two multiplied signals scaled by a factor of four or 4P.sub.A10Q.sub.A10

    (88) Note that the square of either a positive or a negative signal (e.g., P.sub.D10+Q.sub.D10 and P.sub.D10Q.sub.D10) is a positive signal, which enables the disclosed multiplier in FIG. 10 to be capable of operating in four quadrants. Note also that implementation of logic circuit L.sub.10's functions of addition, subtraction, and absolute value simple and low cost in logic.

    (89) As noted earlier, a shared resistor string (that is programmed to approximate a square input-output transfer function) between DAC.sub.10B and DAC.sub.10A saves area, reduces power consumption, and improves matching.

    (90) In FIG. 10, implementing the square data-converters in current mode will have the following benefits: (1) operating in current mode is fast, (2) current voltage swings are smaller compared to voltage mode, which enables operating the multiplier with lower power supply voltage, (3) operating at low supply voltage reduces power consumption, (4) subtraction function performed in analog and current mode is small and fast. Also note that analog implementation of summation and subtraction of array of pairs of multiplied signals in A.sub.10 circuit (e.g., to perform the multiply and accumulate function needed in artificial neural networks and machine learning applications) can be made simple, small, and fast. Moreover, operating in current mode in FIG. 10, the output of A.sub.10 circuit would be a current signal of 4P.sub.A10Q.sub.A10 that can be fed onto a current mode ADC (iADC), to provide the conversion and scaling to a digital word representing P.sub.D10Q.sub.D10.

    (91) Additionally, note that besides resistor string or reference current network, other data-converter with square transfer functions can be utilized here such as a switch-capacitive data-converters whose capacitive transfer function network is programmed to approximates a square input-to-output transfer function. Furthermore, note that principles of FIG. 10 embodiment are applicable to multiple channel (array-based multiplication and accumulation) by utilizing the same two data-converters, in multiple cycles, while saving each multiplication result on array of sample-and-hold circuits the receive the output of the A.sub.10, which are the multiplication results of array of pairs of inputs, as an example. Such arrangements would have the following benefits: (1) It saves on area and cost, (2) lower power consumption, (3) the conversions based on the same data-converters matched better, which can allow for one system-wide correction or trim to improve accuracy, such as correcting for gain error, offsets, or switch capacitor sample-and-hold droop rates. Naturally, the trade-off here is in utilizing the same two data-converters between an array of channels to be multiplied sequentially, would extend the conversion cycles which slows down the data processing time.

    Section 11Description of FIG. 11

    (92) FIG. 11 is a simplified block diagram illustrating an analog-input to digital-output multiplier (X.sub.2A.sub.iD.sub.o) utilizing two ADCs whose input-to-output transfer functions are programmed to approximates a square function. The multiplication function in FIG. 11 is performed relying on the quarter square principle, which was described earlier in this disclosure.

    (93) In FIG. 11, an analog input signal P.sub.A11 and second analog input Q.sub.A11 are applied to an analog signal conditioning circuit A.sub.11 which generates an analog absolute value summation signals |P.sub.A11+Q.sub.A11| as well an analog absolute value subtraction signal |P.sub.A11Q.sub.A11|. Then, |P.sub.A11+Q.sub.A11| and |P.sub.A11Q.sub.A11| analog signals are applied to a first proximate square data-converter ADC.sub.11B and a second proximate square data-converter ADC.sub.11A, respectively. In accordance with the proximate square transfer function of the first and second data-converters, ADC.sub.11A outputs the digital equivalent signal of (|P.sub.D11Q.sub.D11|).sup.2 that is m-bit wide, and ADC.sub.11B outputs the digital equivalent signal of (|P.sub.D11+Q.sub.D11|).sup.2 that is n-bit wide. The digital circuit D.sub.11 subtracts the analog outputs of ADC.sub.11A and ADC.sub.11B from one another and generates the digital representation of the two multiplied signals scaled by a factor of four or 4P.sub.D10Q.sub.D10

    (94) Note that the square of both positive or negative signals (e.g., P.sub.A10+Q.sub.A10 and P.sub.A10Q.sub.A10) is a positive signal, which enables the disclosed multiplier to be capable of operating with four quadrants. As noted in section 4, a shared resistor string (that is programmed to approximate a square input-output transfer function) between ADC.sub.11B and ADC.sub.11A saves area, reduces power consumption, and improves matching.

    (95) Also, in FIG. 11, implementing the square data-converters in current mode will have the following benefits: (1) operating in current mode is fast, (2) current voltage swings are smaller compared to voltage mode, which enables operating the multiplier with lower power supply voltage, (3) operating at low supply voltage reduces power consumption, (4) implementing the addition, subtraction, and absolute value function implementations in analog current mode is small and fast. Also note that digital implementation of subtraction and divide by 4 in logic circuit L.sub.11 can be made simple, small, and fast.

    (96) Furthermore, note that besides the alternatives of utilizing data-converters whose transfer function is based on resistor string or reference current network, a switched capacitor arrangement can also be utilized. For example, switch-capacitive data-converters whose capacitive transfer function is programmed to follow a square transfer function profile. Also note that a multiple-input to single-output sample-hold can sequentially supply the X.sub.2A.sub.iD.sub.o with pairs of analog signals to be multiplied and digitized sequentially, which is useful for neural artificial intelligence and machine learning application requiring matrix multiplication plus accumulation functions. The sequential outputs of a X.sub.2A.sub.iD.sub.o in such an arrangement can be subsequently added, divided by 4, and stored in memory for post signal processing, which is a simple implementation in logic. The sample and hold array-based arrangement that was just described has the following benefits: (1) saves on area and cost, (2) has lower power consumption, (3) all conversions matched better since the same X.sub.2A.sub.iD.sub.o performs the multiplication function and converts the multiplied array of pairs of signals. Additionally, such arrangement would enable one system-wide correction to improve accuracy, such as gain error, offsets, or systematic droop rates associated with the front-end analog sample-and-hold. Naturally, the trade-off here is in utilizing the same two data-converters between an array of channels to be multiplied sequentially, would extend the conversion cycles which slows down the data processing time.

    (97) As noted earlier, in the case of an array of independent X.sub.2A.sub.iD.sub.o that utilize independent ADCs with a single shared a square input-to-output transfer function reference network, there are savings on power, area, and enhanced matching between ADC channels and better matching between multiplication results. Naturally, another benefit is that all multiplication results would be available asynchronously without need to a clock or without cycle delay. Also, such an arrangement can allow for one system-wide correction or trim of the single shared reference network to improve accuracy, such as gain error or offset.

    Section 12Description of FIG. 10

    (98) FIG. 12 is a simplified block diagram illustrating a digital-input to analog-output multiplier (X.sub.logD.sub.iA.sub.o) utilizing two DACs whose input-to-output transfer functions are programmed to approximates a logarithmic function. The multiplication function illustrated in FIG. 12 is performed relying on the quarter square principle, which was described earlier in this disclosure.

    (99) In FIG. 12, a first digital input P.sub.D12 (that is n-bit wide) and second digital input Q.sub.D12 (that is m-bit wide) are applied to a first proximate square data-converter DAC.sub.12A and a second proximate square data-converter DAC.sub.12B, respectively. In accordance with the proximate logarithmic transfer function profile of the first and second data-converters, DAC.sub.12A outputs the analog equivalent signal of log(P.sub.A12) and DAC.sub.12B outputs the analog equivalent signal of log(Q.sub.A12). The analog circuit A.sub.12 sums the analog outputs of DAC.sub.12A and DAC.sub.12B and generates the analog representation of the two multiplied signals in the logarithmic domain or log(P.sub.A12Q.sub.A12). The summation function for voltage signals can be implemented with averaging function of two equal resistors (e.g., resistor divider) being supplied on each of the resistor's end with buffered voltage signals equivalent of log(P.sub.A12) and log(Q.sub.A12). The summation of analog current signals would be simple coupling of current signal equivalents of log(P.sub.A12) and log(Q.sub.A12).

    (100) As noted earlier, a shared resistor string (that is programmed to approximate a logarithmic input-output transfer function) in FIG. 12 between DAC.sub.12B and DAC.sub.12A saves area, reduces power consumption, and improves matching.

    (101) In FIG. 12, implementing logarithmic data-converters in current mode will have the following benefits: (1) operating in current mode is fast, (2) current voltage swings are smaller compared to voltage mode, which enables operating the multiplier with lower power supply voltage, (3) operating at low supply voltage reduces power consumption, (4) as noted earlier the summation function in current mode involves shorting the log(P.sub.A12) and log(Q.sub.A12) analog current signals and the dynamic response is inherently fast. Also, operating in current mode, the output current signal representing log(PA.sub.12Q.sub.A12) can be fed onto an anti-log (exponential) current mode ADC (iADC), to provide the conversion to a digital word representing P.sub.D12Q.sub.D12.

    (102) In addition, note that besides resistor string or reference current network, other data-converter with logarithmic transfer functions can be utilized here such as a switch-capacitive data-converters whose capacitive transfer function network is programmed to approximates a logarithmic input-to-output transfer function. Moreover, note that principles of FIG. 12 embodiment are applicable to multiple channel (array-based multiplication and accumulation) by utilizing the same two data-converters, in multiple cycles, while saving each of log-based multiplication result sequentially on array of sample-and-hold circuits whose output feeds an anti-log iADC to remap the log based analog information to linear binary digital words. Such an arrangement would have the following benefits: (1) saves on die area and chip cost, (2) has lower power consumption, (3) the conversions based on the same data-converters matched better, which can allow for one system-wide correction or trim to improve accuracy, such as correcting for gain error, offsets, or switch capacitor sample-and-hold droop rates. Naturally, the trade-off here is in utilizing the same two data-converters between an array of channels to be multiplied sequentially, would extend the conversion cycles which slows down the data processing time.

    Section 13Description of FIG. 13

    (103) FIG. 13 is a simplified block diagram illustrating an analog-input to digital-output multiplier (X.sub.logA.sub.iD.sub.o) utilizing two ADCs whose input-to-output transfer functions are programmed to approximates a logarithmic function. The multiplication function in FIG. 13 is performed relying on logarithmic principle, which was described earlier in the disclosure.

    (104) In FIG. 13, a first digital input P.sub.A13 and second digital input Q.sub.A13 are applied to a first proximate logarithmic data-converter ADC.sub.13A and a second proximate logarithmic data-converter ADC.sub.13B, respectively. In accordance with the proximate logarithmic transfer function profile of the first and second data-converters, ADC.sub.13A outputs the analog equivalent signal of log(P.sub.D13) and ADC.sub.13B outputs the analog equivalent signal of log(Q.sub.D13). The logic circuit L.sub.10 sums the digital outputs of ADC.sub.13A and ADC.sub.13B and generates the analog representation of the two multiplied signals in the logarithmic domain or log(P.sub.D13Q.sub.D13).

    (105) As noted in section 4, a shared resistor string (that is programmed to approximate a logarithmic input-output transfer function) in FIG. 13 between ADC.sub.13A and ADC.sub.13B saves area, reduces power consumption, and improves matching. Also, in FIG. 13, implementing the logarithmic data-converters in current mode will have the following benefits: (1) operating in current mode is fast, (2) current voltage swings are smaller compared to voltage mode, which enables operating the multiplier with lower power supply voltage, (3) operating at low supply voltage reduces power consumption, (4) implementing the addition of log(P.sub.D13) and log(Q.sub.D13) in logic is small and fast.

    (106) Additionally, note that besides the alternatives of utilizing data-converters whose transfer function is based on resistor string or reference current network, a switched capacitor arrangement can also be utilized. For example, switch-capacitive data-converters whose capacitive transfer function is programmed to follow a logarithmic transfer function profile. Also note that a multiple-input to single-output sample-hold can sequentially supply the X.sub.logA.sub.iD.sub.o with pairs of analog signals to be multiplied and digitized sequentially, which is useful for neural artificial intelligence and matching learning application requiring matrix multiplication plus accumulation functions. The sequential outputs of a X.sub.logA.sub.iD.sub.o in such an arrangement can be subsequently added, and stored in logic for conversion to linear binary, which is a simple implementation in the digital domain. The sample and hold array-based arrangement that was just described has the following benefits: (1) saves on area and cost, (2) has lower power consumption, (3) all conversions matched better since the same X.sub.logA.sub.iD.sub.o performs the multiplication function and converts the multiplied array of pairs of signals. Also, such arrangement would enable one system-wide correction to improve accuracy, such as gain error, offsets, or systematic droop rates associated with the front-end analog sample-and-hold. Naturally, the trade-off here is in utilizing the same two data-converters between an array of channels to be multiplied sequentially, would extend the conversion cycles which slows down the data processing time.

    (107) As noted earlier, in the case of an array of independent X.sub.logA.sub.iD.sub.o that utilize independent ADCs with a single shared a logarithmic input-to-output transfer function reference network, there are saving on power, area, and enhanced matching between ADC channels and better matching between multiplication results. Naturally, another benefit is that all multiplication results would be available asynchronously without need to a clock or without cycle delay. Also, such an arrangement can allow for one system-wide correction or trim of the single shared reference network to improve accuracy, such as gain error or offset.

    Section 14Description of FIG. 14

    (108) FIG. 14 is system block diagram illustrating a digital-input to analog-output multiplier (X.sub.SD.sub.iA.sub.o) utilizing segmented mixed-mode multiplication (SM.sup.3) method. The SM.sup.3 method performs the multiplication function by utilizing mixed-mode and data-converter circuits arranged based on the multiplication principle of segmentation which is described as follows:

    (109) The input signals P and Q are partitioned to most significant portions (MSP) and Least-Significant-Portions (LSP). In describing the method SM.sup.3, P is equal to the sum of MSP of P plus LSP of P, and similarly, Q is equal to the sum of MSP of Q plus LSP of Q. Also, in describing the SM.sup.3 method, the MSP and LSP signals can be analog or digital or combination representations of their respective P and Q signals.

    (110) First the most significant portion of the input signals' multiplication is generated. Here, a P's MSP (P.sub.MSP) is multiplied by a Q's MSP (Q.sub.MSP) utilizing at least one data-converter to generate a scaled (S) segment of multiplication SP.sub.MSPQ.sub.MPS.

    (111) Then, the cross-multiplication or the intermediate segment of the multiplication is generated utilizing at least one data-converter. Here, a P's LSP (P.sub.LSP) is multiplied with the Q.sub.MSP, to generate another scaled (S) segment of multiplication SP.sub.LSPQ.sub.MSP. Similarly, a Q's LSP (Q.sub.LSP) is multiplied with the P.sub.MSP, to generate another scaled (S) segment of multiplication SQ.sub.LSPP.sub.MSP.

    (112) Lastly, the least significant portion of the multiplication is generated utilizing at least one data-converter. Here, another scaled (S) segment of multiplication SP.sub.LSPQ.sub.LSP is generated.

    (113) Finally, the multiplication results of PQ is generated by summing each above segment that each carries their proportional scale factors:
    PQ=SP.sub.MSPQ.sub.MSP+S(P.sub.LSPQ.sub.MSP+Q.sub.LSPP.sub.MSP)+SP.sub.LSPQ.sub.LSP

    (114) The benefits of utilizing SM.sup.3 method to multiply signals are as flows:

    (115) First, the accuracy of the multiplication is dominated by the P.sub.MSPQ.sub.MSP which allows utilizing less accurate and lower cost data-converters to perform the intermediate segments cross multiplication or (P.sub.MSPQ.sub.LSP+Q.sub.MSPP.sub.LSP) and even less accurate and smaller data-converters to perform the LSP multiplication of P.sub.LSPQ.sub.LSP. This benefit enables making the data converters utilized in the intermediate and least significant portions of multiplication smaller which saves on die area and chip cost.

    (116) Second, utilizing the disclosed method where data-converters perform multiplication, then low-resolution data-converter whose transfer function has higher-accuracy can be utilized, which would generate multiplication results with higher-accuracy, and this is how. For example, considering normal manufacturing related imperfections, if the transfer function of a 4-bit resolution data-converter can be linear to 8-bits or 0.4% accuracy, then utilizing a data-converters with 4-bits of resolution (to perform the multiplication in accordance with the disclosed method), then the generated multiplication results would be accurate to 8 bits of 0.4%. As such, high-accuracy multiplication can be achieved with less resolution and thus smaller size data-converters, which lowers the die cost of the multiplier.

    (117) Third, the dynamic response of the multiplier is improved since the speed would be mainly a function of the dynamic response of the most significant portion of the input signals' multiplication or speed of P.sub.MPSQ.sub.MSP, and as such the multiplication speed in the intermediate and least signification is less critical.

    (118) Fourth, segmenting the multiplication process allows the data-converter's transfer function reference network be arranged in smaller segments which in turn improves the glitch transients associated with data-converter's code transition.

    (119) Fifth, there is an area trade-off between performing multiplication using conventional multiplying DACs versus the disclosed segmented multiplication. For multiplication using high-resolution data-converters, the large size of the transfer function reference network associated with a high-resolution data converter is replaced with plurality of smaller transfer function reference network segments associated with lower resolution data-converters.

    (120) Here, FIG. 14 which is an embodiment of the disclosed SM.sup.3 method is described. In FIG. 14, the two digital-input words to be multiplied are P.sub.D14 (that is i-bit wide and as an example i=6) and Q.sub.D14 (that is j-bit wide and as an example j=6). A logic circuit L.sub.14 provides P.sub.D14M (that is it-bit wide and as an example i1=3) which is the Most-Significant-Portion (MSP) of P.sub.D14. The logic circuit L.sub.14 also provides P.sub.D14L (that is i2-bit wide and as an example i2=3) which is the Least-Significant-Portion (LSP) of P.sub.D14. Also, L.sub.14 provides Q.sub.D14M (that is j1-bit wide and as an example j1=3) which is the MSP of Q.sub.D14 and L.sub.14 also provides Q.sub.D14L (that is j2-bit wide and as an example j2=3) which is the LSP of Q.sub.D14.

    (121) At this point, the MSP segments multiplication is described. In FIG. 14, the reference input of a DAC.sub.14A receives a reference signal REF.sub.14A. The digital-input port of DAC.sub.14A receives the digital input word P.sub.D14M, and the DAC.sub.14A generates an analog signal P.sub.A14M at its analog-output port. The reference input of a DAC.sub.14B receives the analog reference signal P.sub.A14M. The DAC.sub.14B receive the digital-input word Q.sub.D14M and the DAC.sub.14B generates an analog signal P.sub.A14MQ.sub.A14M at its analog-output port.

    (122) Now, the MSP and LSP segments cross multiplication is described. Also, in FIG. 14, the reference input of a DAC.sub.14C receives a reference signal REF.sub.14B. The digital-input port of DAC.sub.14C receive the digital input word P.sub.D14M, and the DAC.sub.14C generates an analog signal P.sub.A14M, at its analog-output port. The reference input of a DAC.sub.14D receives the analog reference signal P.sub.A14M. The DAC.sub.14D receives the digital-input word Q.sub.D14L and the DAC.sub.14D generates an analog signal P.sub.A14MQ.sub.A14L at its analog-output port. Also, the reference input of a DAC.sub.14E receives a reference signal REF.sub.14B. The digital-input port of DAC.sub.14E receive the digital input word P.sub.D14L, and the DAC.sub.14E generates an analog signal P.sub.A14L at its analog-output port. The reference input of a DAC.sub.14F receives the analog reference signal P.sub.A14L. The DAC.sub.14F receives the digital-input word Q.sub.D14M and the DAC.sub.14F generates an analog signal P.sub.A14LQ.sub.14M at its analog-output port.

    (123) Here, the LSP segments multiplication is described. In FIG. 14, the reference input of a DAC.sub.14G receives a reference signal REF.sub.14C. The digital-input port of DAC.sub.14G receive the digital input word P.sub.D14L, and the DAC.sub.14G generates an analog signal P.sub.A14L at its analog-output port. The reference input of a DAC.sub.14H receives the analog reference signal P.sub.A14L. The DAC.sub.14H receive the digital-input word Q.sub.D14L and the DAC.sub.14H generates an analog signal P.sub.A14LQ.sub.A14M at its analog-output port.

    (124) Note that the reference signal values of REF.sub.14A is scaled at S, REF.sub.14B is scaled at S, and REF.sub.14C is scaled at S. For example, having 6-bit DACs where i=j=6, and where i1=j1=3, and i2=j2=3, then for S=1, S=S/2.sup.i1=S/2.sup.3=S/8 and S=S/2.sup.j1=S/2.sup.3=S/8=S/(88). In this example, the full-scale value at the analog output of DAC.sub.14B would be 8 times bigger than full-scale value at the analog output of DAC.sub.14D and DAC.sub.14F. Also, the full-scale value at the analog output of DAC.sub.14B would be 88=64 times bigger than full-scale value at the analog output of DAC.sub.14H. Moreover, in this example, the signal value of REF.sub.14A could be 8 times bigger than the signal value of REF.sub.14B. Also, the signal value of REF.sub.14A could be 88=64 times bigger than the signal value of REF.sub.14C.

    (125) As noted earlier, the summation function in current mode is simple, and eliminates the need for an analog circuit A.sub.14. After proportional scaling of each segment multiplication as explained above, current mode summation is realized by coupling each of the multiplying segment iDAC outputs together (i.e., summing the current output of iDACs including DAC.sub.14B, DAC.sub.14D, DAC.sub.14F, and DAC.sub.14H). Thus, P.sub.A14Q.sub.A14 analog current multiplications is generated by scaling the sum of the segments multiplication of the multiplier's input signal's most-significant and least-significant portions that is P.sub.A14MQ.sub.A14M+P.sub.A14MQ.sub.A141L+P.sub.A14LQ.sub.A14M+P.sub.A14LQ.sub.A14L.

    (126) An alternative embodiment of XD.sub.iA.sub.o, as a variation to the disclosure illustrated in FIG. 14, would be to use a digital multiplier to perform the most-significant-portion of segment multiplication in logic and then apply the digital multiplication result to a DAC. In other words, the digital MSP portions of the digital-input words or P.sub.D14M and Q.sub.D14M are applied to a digital multiplier which generates the most significant portion of digital-input multiplication results in digital form of P.sub.D14MQ.sub.D14M. Then, P.sub.D14MQ.sub.D14M digital signal is inputted to a DAC to generate an analog equivalent form of P.sub.A14MQ.sub.A14M. Since the digital multiplication would result with no error, the DAC accuracy will dominate the accuracy of the analog equivalent form of P.sub.A14MQ.sub.A14M, which dominates the accuracy of this alternative embodiment of XD.sub.iA.sub.o. As such, if high precision is required, the DAC can be made more accurate by improving its transfer function reference network accuracy by means such as segmentation, calibration, or trimming and other ways. For the alternative embodiment of XD.sub.iA.sub.0 that was just disclosed, but for the alternative arrangement to generate P.sub.A14MQ.sub.A14M, the rest of the arrangement can remain as illustrated in FIG. 14.

    (127) To save die area and chip cost, another alternative embodiment of XD.sub.iA.sub.0 which would be a variation to the disclosure illustrated in FIG. 14 would be to utilize one DAC (instead of DAC.sub.14A and DAC.sub.14B) to generate the P.sub.A14M signal and then scale it down by factor of S to S to generate the P.sub.A14M, signal. Similarly, one DAC (instead of DAC.sub.14E and DAC.sub.14G) to generate the P.sub.14M signal and then scale it down by factor of S to S to generate the P.sub.A14L signal.

    (128) A current mode embodiment of XD.sub.iA.sub.0 disclosed in FIG. 14 (which would be designated as a XD.sub.iI.sub.o) could be arranged as a current-mode multiplier that utilizes current-mode DACs (iDACs) to perform segment multiplication (i.e., segment multiplying iDACs) as disclosed in the section 8 illustration of FIG. 8. For example, digital-inputs to analog-current-output multiplier XD.sub.iI.sub.o of FIG. 8 (naturally, considering the resolution of the segment multiplying iDAC's as needed by the application and proportional S, S, and S scaling of current reference IR.sub.8A) can be utilized to perform the function of segment multiplication by pairs of segment multiplying iDACs including DAC.sub.14A-DAC.sub.14B, DAC.sub.14C-DAC.sub.14D, DAC.sub.14E-DAC.sub.14F, and DAC.sub.14G-DAC.sub.14H. As noted earlier, the current reference network of the most-significant-portion of the segment multiplying iDACs (i.e., DAC.sub.14A-DAC.sub.14B) can be made more accurate by current network segmentation, trimming, calibration, or selecting larger W/L field-effect-transistors or FETs (e.g., the most-significant portion multiplying iDACs having larger W/L for M.sub.8F, M.sub.8G, and etc.). Also, to save die area and lower chip cost, the intermediate to LSP segment multiplying iDACs can, for example, be designed as having less accurate and smaller FETs.

    (129) It would be obvious to one skilled in the art to convert the analog multiplication results P.sub.A14Q.sub.A14 and convert to digital utilizing a voltage mode or current mode ADC to generate the digital representation of the multiplication results P.sub.D14Q.sub.D14.

    Section 15Description of FIG. 15

    (130) FIG. 15 is a simplified system block diagram illustrating an analog-input to analog-output multiplier (X.sub.SA.sub.iA.sub.o) utilizing segmented mixed-mode multiplication (SM.sup.3) method.

    (131) In FIG. 15, the two analog-inputs of X.sub.SA.sub.iA.sub.o are P.sub.A15 and Q.sub.A15, which are inputted to signal conditioning (SC) SC.sub.15A and SC.sub.15B, respectively. The SC.sub.15A and SC.sub.15B receive the X.sub.SA.sub.iA.sub.o input signals and they each output a pair of signals, one signal representing its input signal's MSP in digital form, and the other signal representing its input signal's residual LSP in analog form. The REF.sub.15A provides the reference signal for SC.sub.15A and SC.sub.15B, and as such it establishes the full-scale to zero-scale analog ranges of the analog input signals. Let's call the reference (REF) scale factor of REF.sub.15A as S, where value of full scale REF.sub.15A=SREF. The SC.sub.15A outputs a digital-output P.sub.D15M signal (that is n-bit wide) which is the digital representation of its MSP of the analog-input signal P.sub.A15. Also, the SC.sub.15A outputs an analog-output P.sub.A15L signal which is the analog representation of the LSP of the analog-input signal P.sub.A15. As stated earlier, note that for the purpose of SM.sup.3 method as embodied in the illustration of FIG. 15, a signal (e.g., P.sub.A15) value is equal to the sum of its MSP and its residual LSP where the MSP and residual LSP can be represented in analog, digital, or analog and digital combination formats. Similarly, SC.sub.15B outputs a digital-output Q.sub.D15M signal (that is m-bit wide) which is the digital representation of its MSP of the analog-input signal Q.sub.A15. Also, the SC.sub.15B outputs an analog-output Q.sub.A15L signal which is the analog representation of the residual LSP of the analog-input signal Q.sub.A15. Similarly, note that for the purpose of SM.sup.3 method as embodied in the illustration of FIG. 15, a signal (e.g., Q.sub.A15) value is equal to the sum of its MSP and its residual LSP where the MSP and residual LSP can be represented in analog, digital, or analog and digital combination formats.

    (132) At this point, the MSP segments multiplication is described. In FIG. 15, the mixed-mode circuit denoted as XDA.sub.15 receives the digital words P.sub.D15M (that is n-bit wide) signal and Q.sub.D15M (that is m-bit wide) signal, and multiplies the two signals and generates an analog multiplication result P.sub.A15MQ.sub.A15M. The reference signal to XDA.sub.15 is REF.sub.15B, and let's call the reference (REF) scale factor of REF.sub.15B as S, where value of full scale REF.sub.15B=SREF. Multiplication of P.sub.D14MQ.sub.D14M and generating their result represented in analog form (i.e., P.sub.A14MQ.sub.A14M) can be realized by using multiplying DACs. For example, REF.sub.15B is the reference signal to a first DAC whose output supplies the reference signal of a second DAC, as described in the MSP segment multiplication (e.g. DAC.sub.14A paired with DAC.sub.14B) in section 14. Alternatively, P.sub.D15M and Q.sub.D15M can be multiplied in digital logic and their digital multiplication results P.sub.D15MQ.sub.D15M can be fed onto a DAC that generates the respective analog multiplication result P.sub.A15MQ.sub.A15M.

    (133) Now, the MSP and LSP segments cross multiplication is described. Also, in FIG. 15, the reference input of a DAC.sub.15A receives a signal P.sub.A15L. Note that the zero-scale to full-scale value of signal P.sub.A15L, applied to reference input of DAC.sub.15A is scaled at SREF. The digital-input port of DAC.sub.15A receive the digital input word Q.sub.D15M, and the DAC.sub.15A generates an analog signal P.sub.A15LQ.sub.A15M at its analog-output port. The digital-input port of DAC.sub.15B receive the digital input word P.sub.D15M, and the reference input of a DAC.sub.15B receives the analog signal Q.sub.A15L. Similarly, in FIG. 15, note that the zero-scale to full-scale value of signal Q.sub.A15L applied to reference input of DAC.sub.15B is scaled at SREF. Accordingly, DAC.sub.15B generates an analog signal P.sub.A15MQ.sub.A15L at its analog-output port. The MSP and LSP segments cross multiplication segment's results are summed together in the analog circuit A.sub.15A which generates P.sub.A15LQ.sub.A15M+P.sub.A15MQ.sub.A15L.

    (134) Here, the LSP segments multiplication is described. In FIG. 15, XA.sub.15 is an analog-input to analog-output multiplier with a reference signal REF.sub.15C that is scaled at S33 REF. The XA.sub.15 receive the analog signals Q.sub.A15L and P.sub.Aisi, and generates an analog signal P.sub.A14LQ.sub.A14L at its analog-output port.

    (135) Now, the reference signal scaling ratios for the respective MSP and LSP segment multiplication is described by way of an example. For instance, for n=m=2 bits, then for S=1.fwdarw.S=S/2.sup.n=S/2.sup.2=S/4 and S=S/2.sup.m=S/2.sup.2=S/4=S/(44). In this example, if REF=16 units, then zero to full-scale value of REF.sub.15A would be 16 units; zero to full-scale value of REF.sub.15B would be 16 units; zero to full-scale value of P.sub.A15L and Q.sub.A15L that are applied as reference signals to DAC.sub.15A and DAC.sub.15B, respectively, would be 16/4=4 units; and zero to full-scale value of REF.sub.15C would be 16/44=1 unit.

    (136) Accordingly, upon proper scaling of the segmented analog signals and their summation before or after the analog circuit A.sub.15, a final multiplication analog result is generated where P.sub.A15Q.sub.A15=P.sub.A15MQ.sub.A15M+P.sub.A14MQ.sub.A15L+P.sub.A15LQ.sub.A15M+P.sub.A15LQ.sub.A15L.

    (137) It would be obvious to one skilled in the art to convert the analog multiplication signal P.sub.A15Q.sub.A15 to its digital equivalent P.sub.D15Q.sub.D15 utilizing an ADC.

    Section 16Description of FIG. 16

    (138) FIG. 16 is a simplified circuit schematic illustrating a signal conditioning (SC) circuit, that can be utilized as SC.sub.15A and SC.sub.15B blocks that are illustrated in FIG. 15 of section 15, as part of a current analog-input to current analog-output multiplier (X.sub.SI.sub.iI.sub.o) is arranged utilizing segmented mixed-mode multiplication (SM.sup.3) method.

    (139) The SC circuit of FIG. 16 receives its current analog input PQA.sub.16=i.sub.i, and generates 2-bits (n=m=2) of digital MSP signals PQD.sub.16M0 and PQD.sub.16M1 as well a residual analog LSP signal PQA.sub.16L. At its REF.sub.16A port, the SC circuit receives its reference signal IREF.sub.16=i.sub.r/4 which is mirrored through M.sub.16B onto 4 (e.g., 2.sup.n=2.sup.m=2.sup.2=4) current mirror reference segments M.sub.16A, M.sub.16C, M.sub.16I, and M.sub.16O. The voltage bias signal VB.sub.16 provides the gate voltage for M.sub.16S. Note that the accuracy of the SC circuit and that of the multiplier X.sub.SI.sub.iI.sub.o is dominated, firstly, by the matching between the current reference segments and current mirror FETs M.sub.16A, M.sub.16C, M.sub.16I, and M.sub.16O. Also, note that the zero-scale to full-scale span of SC circuit is 4i.sub.r/4=i.sub.r

    (140) At the analog input PQA.sub.16, an analog-input signal i.sub.i is first compared with the first current mirror (M.sub.16A) reference segment that has a value of i.sub.r/4. The resultant difference flows either through M.sub.16E or M.sub.16F depending on the polarity of (i.sub.ii.sub.r/4) and accordingly a digital signal is outputted by A.sub.16A. If i.sub.i<i.sub.r/4, then the difference or (i.sub.ii.sub.r/4) flows through M.sub.16F and onto M.sub.16G. On the other hand, if i.sub.i>i.sub.r/4, then the difference or (i.sub.ii.sub.r/4) flows through M.sub.16E where (i.sub.ii.sub.r/4) gets compared with i.sub.r/4 which is M.sub.16D's current.

    (141) Similarly, the difference (i.sub.ii.sub.r/4)i.sub.r/4 flows either through M.sub.16J or M.sub.16K depending on the polarity of (i.sub.ii.sub.r/4i.sub.r/4) and accordingly a digital signal is outputted by A.sub.16B. If i.sub.ii.sub.r/4<i.sub.r/4, then the difference or (i.sub.ii.sub.r/4)i.sub.r/4 flows through M.sub.16K and onto M.sub.16L. On the other hand, if i.sub.ii.sub.r/4>i.sub.r/4, then the difference (i.sub.ii.sub.r/4)i.sub.r/4 flows through M.sub.16J where (i.sub.ii.sub.r/4) gets compared with i.sub.r/4 which is M.sub.16I's current.

    (142) As i.sub.i ripples through (the effectively) the SC circuit's thermometer current reference (four segment) network, the digital signals outputted by A.sub.16A, A.sub.16B, and A.sub.16C (with proper sign) control the current flow through the analog switches M.sub.16L, M.sub.16R, and M.sub.16T whose sum of current flows M.sub.16M. Note that the gate to source voltage of M.sub.16M and the current through M.sub.16M represent the residual analog LSP of the SC circuit's input current.

    (143) FIG. 20 upper graphs illustrate a pair of triangular saw-tooth waveforms which are residual LSP of P and residual LSP of Q signals. This saw-tooth waveform illustrate the equivalent current residual LSP signals P.sub.A15L, and Q.sub.A15L generated by SC.sub.15A and SC.sub.15B blocks in FIG. 15 (of section 15) that utilize the SC circuit of FIG. 16 (of section 16).

    (144) To avoid the transitional glitches that appears at the final multiplication results due in part to the MSP transitions, the SC circuit can be modified to output an equilateral triangular waveform instead of a saw-tooth triangular waveform. As such, the triangular waveform does not pulse from full-scale to zero-scale. Accordingly, the final multiplication results can be generated by proper analog and digital signal re-assembly of the MSP and residual LSP segments.

    (145) In FIG. 20, it can be observed that the zero-scale to full-scale span of LSP of P and residual LSP of Q signals ratio versus zero-scale to full scale span of SC circuit are is 1/2.sup.n=1/2.sup.m=1/2.sup.2=1/4. FIG. 20 will be described in more detail later in section 20.

    (146) Also, note that the digital signals outputted by A.sub.16A, A.sub.16B, and A.sub.16c with proper sign control, are inputted to a 3-bit (e.g., 2.sup.n1=2.sup.m1=2.sup.21=3) to 2-bit encoder (comprising XNOR.sub.16, NAND.sub.16A, and NAND.sub.16B) that generate (PQD.sub.16M0 and PQD.sub.16M1 which is) the digital MSP of the SC circuit's input current.

    (147) Accordingly, utilizing the SC circuit of FIG. 16 as SC.sub.15A and or SC.sub.15B of FIG. 15, the FIG. 16's SC circuit's analog-output signal PQA.sub.16L represents scaled equivalent of FIG. 15 SC.sub.15A and or SC.sub.15B analog signals P.sub.A15L and or Q.sub.A15L (the LSP of P and LSP of Q signals), respectively. Similarly, FIG. 16's SC circuit's digital-output word PQD.sub.16M0/1 represents scaled equivalent of FIG. 15 SC.sub.15A and or SC.sub.15B digital words P.sub.D15M and or Q.sub.D15M (the MSP of P and or MSP of Q signals, respectively.

    (148) Note that other circuits such as current mode algorithmic analog to digital converters can be utilized to generate the digital MSP and the residual analog LSP of its respective analog input current signal.

    Section 17Description of FIG. 17

    (149) FIG. 17 is a simplified circuit schematic illustrating a current analog-input to current analog-output multiplier circuit, operating in subthreshold, that can be utilized as the XA.sub.15 block that is illustrated in FIG. 15 of section 15, as a part of a current analog-input to current analog-output multiplier (X.sub.SI.sub.iI.sub.o) is arranged utilizing segmented mixed-mode multiplication (SM.sup.3) method.

    (150) The current analog multiplier illustrated in FIG. 17 receives two analog input signals, PA.sub.17L and QA.sub.17L, and generates their multiplication I.sub.N17AI.sub.N17B/I.sub.R17 which is a current analog-output signal PQA.sub.17L. The current analog multiplier illustrated in FIG. 17 also has a current reference input signal IR.sub.17 that is inputted at REF.sub.17C port. Currents through FETs M.sub.17F and M.sub.17G scaled at d.X (relative to its mirror FET M.sub.16M in FIG. 16) receive the residual analog LSP of P and LSP of Q signal currents, respectively. The current analog multiplier illustrated in FIG. 17 operates in subthreshold, and as such its FETs behave like pseudo-bipolar transistors. Therefore, the voltage loop provides the following: VGS.sub.M17A+VGS.sub.M17CVGS.sub.M17D+VGS.sub.M17B=0. Thus, I.sub.M17C/I.sub.M17AI.sub.M17B/I.sub.M17D or I.sub.M17F/I.sub.R17=I.sub.M17D/I.sub.M17G or I.sub.M17D=I.sub.M17FI.sub.M17G/I.sub.R17, which is mirrored by M.sub.17H and M.sub.17I and scaled e.X and f.X current mirror scale factors to provide PQ.sub.A17L multiplication of the residual analog LSP of P and LSP of Q signal currents with the proper sign.

    (151) Accordingly, the PQ.sub.A17L analog signal in FIG. 17 is a scaled equivalent analog signal to that of P.sub.A15LQ.sub.A15L in FIG. 15 of section 15.

    (152) As discussed earlier, the errors attributed to multiplier's linearity or settling time are attenuated (referred back to the input signals of X.sub.SI.sub.iI.sub.o of FIG. 15) since the current analog multiplier of FIG. 17 only handles the residual LSP of P and Q signals. As such, the analog multiplier of FIG. 17 can be made simple, and small (low cost).

    (153) Note that current analog-input to analog-output multipliers (relying on the square function relationship between voltage and current in CMOS) that operate in higher current levels in the MOSFET saturation region (not limited to subthreshold operation) can also be utilized depending on the application requirement.

    Section 18Description of FIG. 18

    (154) FIG. 18 is a simplified circuit schematic illustrating a digital-input to current analog-output multiplying DAC, that can be utilized as DAC.sub.15A and DAC.sub.15B blocks illustrated in FIG. 15 of section 15. The circuit in FIG. 18 a part of a current analog-input to current analog-output multiplier (X.sub.SI.sub.iI.sub.o) is arranged utilizing segmented mixed-mode multiplication (SM.sup.3) method.

    (155) In FIG. 18, the digital input word comprising two-bit wide digital word signal (PQ.sub.18D1 and PW.sub.18D0) that can correspond to either of P.sub.D15M (n=2 bit wide) or P.sub.Q15M (m=2 bit wide) of FIG. 15 in section 15. The FIG. 18's DAC's reference signal is REF.sub.18 corresponds to the PQ.sub.Ai6L of FIG. 16 in section 16, which can correspond to either P.sub.A15L or QA.sub.15L of FIG. 15 in section 15. Note that FET M.sub.16M with a.X scale (in FIG. 16) is mirrored onto FETs M.sub.18A (scaled at b.X) and M.sub.18B (scaled at c.X) in FIG. 18, where c=2b which binary scales the FIG. 18 DAC's M.sub.18A and M.sub.18B currents, relative to the FIG. 16's M.sub.16M's current signal (which can be the LSP of P or LSP of Q signals).

    (156) As discussed earlier, the errors attributed to FIG. 18's multiplying DAC's linearity are attenuated (referred back to the input signals of X.sub.SI.sub.iI.sub.o of FIG. 15) since the current analog multiplier of FIG. 18 handles the intermediate or cross multiplication of MSP of P and Q signals with the residual LSP of P and Q signals. The multiplying DAC of FIG. 17 is fast since it runs current mode (with current sources being steered with digital switches) and can be made simple, and small (low cost).

    Section 19Description of FIG. 19

    (157) FIG. 19 is a simplified circuit schematic illustrating a digital-input to current analog-output multiplier, utilizing two current mode DACs, that can be utilized as XDA.sub.15 block that is illustrated in FIG. 15 of section 15. The circuit in FIG. 19 a part of a current analog-input to current analog-output multiplier (X.sub.SI.sub.iI.sub.o) is arranged utilizing segmented mixed-mode multiplication (SM.sup.3) method.

    (158) The multiplying DAC of FIG. 19 (that corresponds to XDA.sub.15 of FIG. 15) multiplies the MSP portion of P to MSP portion of Q signals as it pertains to FIG. 15. The multiplying DAC of FIG. 19 receives a n=2 bit digital word signal (P.sub.D19M0, P.sub.D19M1) that it multiplies with another m=2 bit digital word signal (Q.sub.D19M0, Q.sub.D19M1) and outputs their multiplication as an analog current PQ.sub.A19M signal. The reference signal IREF.sub.19 applied to REF.sub.19 port of a first iDAC in FIG. 19 that is mirrored and scaled by FETs M.sub.19C (scaled at a.X), M.sub.19D (scaled at b.X), and M.sub.19E (scaled at c.X) where c=2b for the first iDAC's binary-scaled current reference network. The output of the first iDAC is fed onto a second iDAC through FETs M.sub.19F (scaled at a.X) which is married with M.sub.19G (scaled at b.X) and M.sub.19H (scaled at c.X) where c=2b for the second iDAC's binary-scaled current reference network.

    (159) Note that the digital word signal (P.sub.D19M0, P.sub.D19M1) of FIG. 19 corresponds to the n=2 bit word P.sub.D15M of FIG. 15; the digital word signal (Q.sub.D19M0, QD.sub.19M1) of FIG. 19 corresponds to the m=2 bit word Q.sub.D15M of FIG. 15; and the analog output signal PQ.sub.A19M of FIG. 19 corresponds to P.sub.A15MQ.sub.A15M signal of FIG. 15.

    (160) The multiplying iDAC of FIG. 19 is current mode and fast, which enhances the overall dynamic performance of the X.sub.SI.sub.iI.sub.o. The matching of the FETs in the IDAC's current mirrors (M.sub.19C, M.sub.19D, and M.sub.19E as well as matching between M.sub.19F, M.sub.19G, and M.sub.19H) dominates the accuracy of the overall X.sub.SI.sub.iI.sub.o. Also as stated earlier, the function of digital input to analog output multiplication of XDA.sub.15 can be performed by multiplying the digital bits utilizing a digital multiplier (e.g. 2-bits by 2-bit digital input to 4-bit digital output digital multiplier) and then feeding the output of the digital multiplier to a (e.g., 4-bit) iDAC.

    Section 20Description of FIG. 20

    (161) FIG. 20 is a circuit simulation showing waveforms of the current analog-input to current analog-output multiplier (X.sub.SI.sub.iI.sub.o), that is arranged utilizing segmented mixed-mode multiplication (SM.sup.3) method, and illustrated in FIG. 15. FIG. 20's illustrated simulation waveforms pertain to a X.sub.SI.sub.iI.sub.o that utilizes the circuits illustrated in FIG. 16 (corresponding to SC.sub.15A and SC.sub.15B of FIG. 15), FIG. 17 (corresponding to XA.sub.15 of FIG. 15), FIG. 18 (corresponding to the DAC.sub.15A and DAC.sub.15B of FIG. 15), and 19.

    (162) Note that the final output of the FIG. 15's multiplier X.sub.SI.sub.iI.sub.o or P.sub.A15Q.sub.A15 is the sum of the corresponding current signals PQ.sub.A19M (one of FIG. 19's circuit pertain to the Q and P MSP multiplication output result) plus current signals PQ.sub.A18 (two of FIG. 18's circuit pertaining to the cross multiplication of P and Q MSP and LSP output result) plus PQ.sub.A17L (one of FIG. 17's circuit pertain to the Q and P LSP multiplication output result), where each if the segment currents have been proportionally scaled as described earlier.

    (163) The upper graph in FIG. 10 illustrated the P spanning from full scale to zero scale while Q spans from zero-scale to full scale and the ideal PQ waveforms all of which are normalized over their absolute value (for illustrative clarity of signals spanning between one and zero, and where PQ is offset by 0.125 to avoid pictorial over-lap). Note that P, Q, and PQ correspond to P.sub.A15, Q.sub.A15, and P.sub.A15Q.sub.A15 signals of FIG. 15, respectively.

    (164) The upper graph in FIG. 20 also shows the simulated PQ, as well as the residual LSP of P and residual LSP of Q signals which are the saw tooth signals and 1/2.sup.n=1/2.sup.m=1/2.sup.2=1/4 of the full scale of P and Q signals. Again, in FIG. 20, the signals shown as residual LSP of P and residual LSP of Q correspond to P.sub.A15L and Q.sub.A15L signals in FIG. 15, respectively, which are applied to as reference signals for DAC.sub.15A and DAC.sub.15B.

    (165) The lower graph in FIG. 20 shows the simulated PQ minus the ideal PQ to generate a linearity error plot for the multiplier X.sub.SI.sub.iI.sub.o. As expected, note that the overall X.sub.SI.sub.iI.sub.o's linearity error is about 0.14% which is attenuated by about 1/(2.sup.22.sup.2)=1/16 of the roughly 2% linearity error associated with the current analog-input to current analog output circuit illustrated in FIG. 17 analog multiplier.