NARROWBAND INTERNET-OF-THINGS (NBIOT) PHYSICAL DOWNLINK CONTROL CHANNEL (PDCCH) MONITORING OPTIMIZATION IN NON-TERRESTRIAL NETWORKS (NTN)

Abstract

Methods and apparatuses for monitoring NPDCCH in NBIoT are disclosed. A method comprises receiving a first control signal scheduling a data transmission; and monitoring a second control signal from a start time slot to an end time slot, wherein the start time slot is a gap period behind the last time slot for receiving the first control signal, and the end time slot is a time period ahead of the first time slot for the data transmission.

Claims

1. A method comprising: receiving a first control signal scheduling a data transmission; and monitoring a second control signal from a start time slot to an end time slot, wherein the start time slot is a gap period behind a last time slot for receiving the first control signal, and the end time slot is a time period ahead of a first time slot for the data transmission.

2. The method of claim 1, wherein, the gap period is configured by broadcast signal.

3. The method of claim 1, wherein the gap period is determined by at least one of user equipment (UE) location information, or corresponding satellite orbit and ephemeris information.

4. The method of claim 1, further comprising: skipping monitoring the second control signal during the gap period, wherein a first time slot of the gap period is next to the last time slot for receiving the first control signal.

5. The method of claim 1, wherein a time period between the end time slot and the first time slot for the data transmission is two time slots.

6. A remote unit, comprising: a receiving circuitry; a transmitting circuitry; and a processor connected to the receiving circuitry and the transmitting circuitry, the processor configured to cause the remote unit to: receive a first control signal scheduling a data transmission; and monitor a second control signal from a start time slot to an end time slot, wherein the start time slot is a gap period behind a last time slot for receiving the first control signal, and the end time slot is a time period ahead of a first time slot for the data transmission.

7. The remote unit of claim 6, wherein, the gap period is configured by broadcast signal.

8. The remote unit of claim 6, wherein the gap period is determined by at least one of user equipment (UE) location information, or corresponding satellite orbit and ephemeris information.

9. The remote unit of claim 6, wherein, the processor is further configured to cause the remote unit to skip monitoring the second control signal during the gap period, wherein a first time slot of the gap period is next to the last time slot for receiving the first control signal.

10. The remote unit of claim 6, wherein a time period between the end time slot and the first time slot for the data transmission is two time slots.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0019] A more particular description of the embodiments briefly described above will be rendered by reference to specific embodiments that are illustrated in the appended drawings. Understanding that these drawings depict only some embodiments, and are not therefore to be considered to be limiting of scope, the embodiments will be described and explained with additional specificity and detail through the use of the accompanying drawings, in which:

[0020] FIG. 1 illustrates a legacy NPDCCH search space;

[0021] FIG. 2 illustrates the legacy NPDCCH search space;

[0022] FIG. 3 illustrates an updated legacy NPDCCH search space;

[0023] FIG. 4 illustrates the monitoring of NPDCCH in the updated legacy NPDCCH search space;

[0024] FIG. 5 illustrates the monitoring of NPDCCH according to an embodiment;

[0025] FIG. 6 illustrates a situation in which the NPDCCH monitoring window is positioned at the end of the gap period;

[0026] FIG. 7 illustrates a situation in which the NPDCCH monitoring window is positioned in the beginning of the gap period;

[0027] FIG. 8 is a schematic flow chart diagram illustrating an embodiment of a method; and

[0028] FIG. 9 is a schematic block diagram illustrating apparatuses according to one embodiment.

DETAILED DESCRIPTION

[0029] As will be appreciated by one skilled in the art that certain aspects of the embodiments may be embodied as a system, apparatus, method, or program product. Accordingly, embodiments may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro-code, etc.) or an embodiment combining software and hardware aspects that may generally all be referred to herein as a “circuit”, “module” or “system”. Furthermore, embodiments may take the form of a program product embodied in one or more computer readable storage devices storing machine-readable code, computer readable code, and/or program code, referred to hereafter as “code”. The storage devices may be tangible, non-transitory, and/or non-transmission. The storage devices may not embody signals. In a certain embodiment, the storage devices only employ signals for accessing code.

[0030] Certain functional units described in this specification may be labeled as “modules”, in order to more particularly emphasize their independent implementation. For example, a module may be implemented as a hardware circuit comprising custom very-large-scale integration (VLSI) circuits or gate arrays, off-the-shelf semiconductors such as logic chips, transistors, or other discrete components. A module may also be implemented in programmable hardware devices such as field programmable gate arrays, programmable array logic, programmable logic devices or the like.

[0031] Modules may also be implemented in code and/or software for execution by various types of processors. An identified module of code may, for instance, include one or more physical or logical blocks of executable code which may, for instance, be organized as an object, procedure, or function. Nevertheless, the executables of an identified module need not be physically located together, but, may include disparate instructions stored in different locations which, when joined logically together, include the module and achieve the stated purpose for the module.

[0032] Indeed, a module of code may contain a single instruction, or many instructions, and may even be distributed over several different code segments, among different programs, to and across several memory devices. Similarly, operational data may be identified and illustrated herein within modules and may be embodied in any suitable form and organized within any suitable type of data structure. This operational data may be collected as a single data set, or may be distributed over different locations including over different computer readable storage devices. Where a module or portions of a module are implemented in software, the software portions are stored on one or more computer readable storage devices.

[0033] Any combination of one or more computer readable medium may be utilized. The computer readable medium may be a computer readable storage medium. The computer readable storage medium may be a storage device storing code. The storage device may be, for example, but need not necessarily be, an electronic, magnetic, optical, electromagnetic, infrared, holographic, micromechanical, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing.

[0034] A non-exhaustive list of more specific examples of the storage device would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or Flash Memory), portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer-readable storage medium may be any tangible medium that can contain or store a program for use by or in connection with an instruction execution system, apparatus, or device.

[0035] Code for carrying out operations for embodiments may include any number of lines and may be written in any combination of one or more programming languages including an object-oriented programming language such as Python, Ruby, Java, Smalltalk, C++, or the like, and conventional procedural programming languages, such as the “C” programming language, or the like, and/or machine languages such as assembly languages. The code may be executed entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the very last scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider).

[0036] Reference throughout this specification to “one embodiment”, “an embodiment”, or similar language means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, appearances of the phrases “in one embodiment”, “in an embodiment”, and similar language throughout this specification may, but do not necessarily, all refer to the same embodiment, but mean “one or more but not all embodiments” unless expressly specified otherwise. The terms “including”, “comprising”, “having”, and variations thereof mean “including but are not limited to”, unless otherwise expressly specified. An enumerated listing of items does not imply that any or all of the items are mutually exclusive, otherwise unless expressly specified. The terms “a”, “an”, and “the” also refer to “one or more” unless otherwise expressly specified.

[0037] Furthermore, described features, structures, or characteristics of various embodiments may be combined in any suitable manner. In the following description, numerous specific details are provided, such as examples of programming, software modules, user selections, network transactions, database queries, database structures, hardware modules, hardware circuits, hardware chips, etc., to provide a thorough understanding of embodiments. One skilled in the relevant art will recognize, however, that embodiments may be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid any obscuring of aspects of an embodiment.

[0038] Aspects of different embodiments are described below with reference to schematic flowchart diagrams and/or schematic block diagrams of methods, apparatuses, systems, and program products according to embodiments. It will be understood that each block of the schematic flowchart diagrams and/or schematic block diagrams, and combinations of blocks in the schematic flowchart diagrams and/or schematic block diagrams, can be implemented by code. This code may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which are executed via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the schematic flowchart diagrams and/or schematic block diagrams for the block or blocks.

[0039] The code may also be stored in a storage device that can direct a computer, other programmable data processing apparatus, or other devices, to function in a particular manner, such that the instructions stored in the storage device produce an article of manufacture including instructions which implement the function specified in the schematic flowchart diagrams and/or schematic block diagrams block or blocks.

[0040] The code may also be loaded onto a computer, other programmable data processing apparatus, or other devices, to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the code executed on the computer or other programmable apparatus provides processes for implementing the functions specified in the flowchart and/or block diagram block or blocks.

[0041] The schematic flowchart diagrams and/or schematic block diagrams in the Figures illustrate the architecture, functionality, and operation of possible implementations of apparatuses, systems, methods and program products according to various embodiments. In this regard, each block in the schematic flowchart diagrams and/or schematic block diagrams may represent a module, segment, or portion of code, which includes one or more executable instructions of the code for implementing the specified logical function(s).

[0042] It should also be noted that in some alternative implementations, the functions noted in the block may occur out of the order noted in the Figures. For example, two blocks shown in succession may substantially be executed concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. Other steps and methods may be conceived that are equivalent in function, logic, or effect to one or more blocks, or portions thereof, to the illustrated Figures.

[0043] Although various arrow types and line types may be employed in the flowchart and/or block diagrams, they are understood not to limit the scope of the corresponding embodiments. Indeed, some arrows or other connectors may be used to indicate only the logical flow of the depicted embodiment. For instance, an arrow may indicate a waiting or monitoring period of unspecified duration between enumerated steps of the depicted embodiment. It will also be noted that each block of the block diagrams and/or flowchart diagrams, and combinations of blocks in the block diagrams and/or flowchart diagrams, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and code.

[0044] The description of elements in each Figure may refer to elements of proceeding figures. Like numbers refer to like elements in all figures, including alternate embodiments of like elements.

[0045] As described in the background part, unnecessary power consumption may be present in monitoring the next DCI in the UE specific search space. FIG. 4 illustrates the monitoring of NPDCCH when the delay period is extended to k.sub.0+K.sub.offset.

[0046] As shown in FIG. 4, the UE, after receiving a first DCI N0 ending in time slot n (hereinafter, time slot is referred to as subframe), will start the corresponding NPUSCH format 1 transmission starting from subframe n+k.sub.0+K.sub.offset (i.e. k=k.sub.0+K.sub.offset). In addition, the UE continues to monitor the NPDCCH from subframe n+1 to subframe n+k.sub.0+K.sub.offset−3 for a next DCI N0 (a second DCI N0). The UE does not monitor the NPDCCH at subframe n+k.sub.0+K.sub.offset−2 and subframe n+k.sub.0+K.sub.offset−1 as these two frames are used for switching to the NPUSCH transmission. k.sub.0 is determined by DCI N0. K.sub.offset is configured by broadcast signal, e.g. in SIB or RRC signaling. K.sub.offset may be alternatively determined by the UE when the UE has its position information, and the earth orbit and ephemeris information. The earth orbit and ephemeris information indicates the position where the satellite is.

[0047] Due to long RTD in NTN, the offset K.sub.offset may be quite long. Therefore, it is power wasting to monitor the NPDCCH for the second DCI N0 during the entire period from subframe n+1 to subframe n+k.sub.0+K.sub.offset−3.

[0048] FIG. 5 illustrates the monitoring of NPDCCH according to an embodiment of the present application.

[0049] As shown in FIG. 5, the UE receives a first DCI N0 ending in subframe n. Then, the UE skips NPDCCH monitoring from subframe n+1 to subframe n+K.sub.offset. The UE monitors NPDCCH for a second DCI N0 from subframe n+K.sub.offset+1 to subframe n+K.sub.offset+k.sub.0−3. The UE is not required to monitor NPDCCH for the last two subframes, i.e. subframe n+K.sub.offset+k.sub.0−2 and subframe n+K.sub.offset+k.sub.0−1, used for switching to the NPUSCH transmission. The UE starts NPUSCH format 1 transmission indicated by the first DCI N0 from subframe n+K.sub.offset+k.sub.0.

[0050] It can be seen that, according to the present invention, if the NB-IoT UE detects NPDCCH with DCI Format N0 ending in subframe n, and if the corresponding NPUSCH format 1 transmission starts from n+k (i.e. n+K.sub.offset+k.sub.0), the UE is not required to monitor an NPDCCH candidate during a gap period, i.e. in subframes starting from subframe n+1 to subframe n+K.sub.offset nor during a time period (used for switching), i.e. from subframe n+K.sub.offset+k.sub.0−2 to subframe n+K.sub.offset+k.sub.0−1. The first subframe of the gap period, i.e. subframe n+1, is just behind (i.e. next to) the last subframe for receiving DCI Format N0, i.e. subframe n.

[0051] From another point of view, if the NB-IoT UE detects NPDCCH with DCI Format N0 ending in subframe n, and if the corresponding NPUSCH format 1 transmission starts from subframe n+k (i.e. n+K.sub.offset+k.sub.0), the UE monitors an NPDCCH candidate from a start subframe n+K.sub.offset+1 to an end subframe n+K.sub.offset+k.sub.0−3.

[0052] The start subframe, i.e. subframe n+K.sub.offset+1, is behind the last subframe for receiving DCI Format N0, i.e. subframe n, by the gap period (from subframe n+1 to subframe n+K.sub.offset). In other words, the gap period (from subframe n+1 to subframe n+K.sub.offset) is between the last subframe for receiving DCI Format N0, i.e. subframe n, and the start subframe, i.e. subframe n+K.sub.offset+1.

[0053] The end subframe, i.e. subframe n+K.sub.offset+k.sub.0−3, is two subframes ahead of the first subframe for NPUSCH format 1 transmission (i.e. subframe n+K.sub.offset+k.sub.0). In other words, the two subframes used for switching (subframe n+K.sub.offset+k.sub.0−2 and subframe n+K.sub.offset+k.sub.0−1) are between the end subframe (subframe n+K.sub.offset+k.sub.0−3) and the first subframe for NPUSCH format 1 transmission (subframe n+K.sub.offset+k.sub.0).

[0054] According to the present invention, for NBIoT in NTN with maximum HARQ process number of 2, after reception a first DCI N0, UE will start to monitor the NPDCCH for a second DCI N0 after the gap period, e.g., after K.sub.offset subframes.

[0055] The gap period may be configured by broadcast signal, e.g. by SIB or higher layer. The gap period ranges from tens of milliseconds to hundreds of milliseconds. For example, if the eNB is on LEO, the gap period may be tens of milliseconds, while if the eNB is on GEO, the gap period may be hundreds of milliseconds. The gap period may be alternatively determined by the UE if the UE has its location information, and the earth orbit and ephemeris information.

[0056] A NPDCCH search space is periodic. The length of the NPDCCH search space (i.e. NPDCCH period) may be indicated as T=G.Math.R.sub.max, in which G is determined by higher layer, R.sub.max is the maximum number of NPDCCH repetition. The gap period may be represented in unit of NPDCCH period. For example, the gap period may be 10 NPDCCH periods (i.e. 10T=10G.Math.R.sub.max).

[0057] A comparison between FIG. 4 and FIG. 5 can indicate that the UE does not monitor NPDCCH for a next DCI N0 from subframe n+1 to subframe n+K.sub.offset according to the embodiment of the present invention (FIG. 5) while the UE has to monitor NPDCCH from subframe n+1 to subframe n+K.sub.offset according to prior art shown in FIG. 4. Therefore, power consumption for monitoring from subframe n+1 to subframe n+K.sub.offset can be saved according to the embodiment of the present invention.

[0058] The NPDCCH monitoring window according to the present invention, i.e. from subframe n+K.sub.offset+1 to subframe n+K.sub.offset+k.sub.0−3 as shown in FIG. 5, is positioned at the end of the gap period between the last subframe for receiving DCI N0 and the corresponding NPUSCH transmission (in particular, 2 subframes (used for switching) ahead of the NPUSCH transmission), rather than in the beginning or middle of the gap period. The position of the NPDCCH monitoring window is chosen in view of facilitating the scheduling, especially when the maximum HARQ process number is equal to 2.

[0059] FIG. 6 illustrates a situation in which the NPDCCH monitoring window is positioned at the end of the gap period. FIG. 7 illustrates another situation in which the NPDCCH monitoring window is positioned in the beginning of the gap period (e.g. following the DCI).

[0060] As shown in FIG. 6, the second DCI is monitored at the end of the gap period between the first DCI and the corresponding first NPUSCH; the third DCI is monitored at the end of the gap period between the second DCI and the corresponding second NPUSCH. The scheduling is made smoothly.

[0061] On the other hand, as shown in FIG. 7, the scheduling will be blocked by the limited (two) HARQ process numbers.

[0062] As a whole, if the NB-IoT UE detects NPDCCH with DCI Format N0 ending in subframe n, and if the corresponding NPUSCH format 1 transmission starts from subframe n+k, the UE is not required to monitor an NPDCCH candidate in subframes starting from subframe n+1 to subframe n+K.sub.offset and from subframe n+k−2 to subframe n+k−1 (assuming k=K.sub.offset+k.sub.0).

[0063] FIG. 8 is a schematic flow chart diagram illustrating an embodiment of a method 800 according to the present application. In some embodiments, the method 800 is performed by an apparatus, such as a remote unit. In certain embodiments, the method 800 may be performed by a processor executing program code, for example, a microcontroller, a microprocessor, a CPU, a GPU, an auxiliary processing unit, a FPGA, or the like.

[0064] The method 800 may include 810 receiving a first control signal scheduling a data transmission; and 820 monitoring a second control signal from a start time slot to an end time slot, wherein the start time slot is a gap period behind the last time slot for receiving the first control signal, and the end time slot is a time period ahead of the first time slot for the data transmission.

[0065] FIG. 9 is a schematic block diagram illustrating apparatuses according to one embodiment.

[0066] Referring to FIG. 9, the UE (i.e. the remote unit) includes a processor, a memory, and a transceiver. The processor implements a function, a process, and/or a method which are proposed in FIG. 8. The eNB (i.e. base unit) includes a processor, a memory, and a transceiver. Layers of a radio interface protocol may be implemented by the processors. The memories are connected with the processors to store various pieces of information for driving the processors. The transceivers are connected with the processors to transmit and/or receive a radio signal. Needless to say, the transceiver may be implemented as a transmitter to transmit the radio signal and a receiver to receive the radio signal.

[0067] The memories may be positioned inside or outside the processors and connected with the processors by various well-known means.

[0068] In the embodiments described above, the components and the features of the embodiments are combined in a predetermined form. Each component or feature should be considered as an option unless otherwise expressly stated. Each component or feature may be implemented not to be associated with other components or features. Further, the embodiment may be configured by associating some components and/or features. The order of the operations described in the embodiments may be changed. Some components or features of any embodiment may be included in another embodiment or replaced with the component and the feature corresponding to another embodiment. It is apparent that the claims that are not expressly cited in the claims are combined to form an embodiment or be included in a new claim.

[0069] The embodiments may be implemented by hardware, firmware, software, or combinations thereof. In the case of implementation by hardware, according to hardware implementation, the exemplary embodiment described herein may be implemented by using one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), processors, controllers, micro-controllers, microprocessors, and the like.

[0070] Embodiments may be practiced in other specific forms. The described embodiments are to be considered in all respects to be only illustrative and not restrictive. The scope of the invention is, therefore, indicated by the appended claims rather than by the foregoing description. All changes which come within the meaning and range of equivalency of the claims are to be embraced within their scope.