III-V-ON-SILICON NANORIDGE OPTO-ELECTRONIC DEVICE WITH CARRIER BLOCKING LAYERS

Abstract

The disclosed technology relates to the development of a monolithic active electro-optical device. The electro-optical device may be fabricated using the so-called nanoridge aspect ratio trapping (ART) approach. In one aspect, the disclosed technology is directed to a monolithic integrated electro-optical device, which comprises a III-V-semiconductor-material ridge structure arranged on a Si-based support region. The ridge structure includes a first-conductivity-type bottom region arranged on the support region, a first-conductivity-type lower blocking layer arranged on the top surface and parts of the side surfaces of the bottom region and configured to block second-conductivity-type charge carriers, a not-intentionally-doped (NID) intermediate region arranged on the top and side surfaces of the lower blocking layer and containing a recombination region, a second-conductivity-type upper blocking layer arranged on the top and side surfaces of the intermediate region and configured to block first-conductivity-type charge carriers, and a second-conductivity-type top region arranged on the top and side surfaces of the upper blocking layer.

Claims

1. A monolithic integrated electro-optical device, comprising: a first-conductivity-type Si-based support region; and a III-V-semiconductor-material ridge structure extending from the Si-based support region, the ridge structure comprising: a first-conductivity-type bottom region arranged on the support region, a first-conductivity-type lower blocking layer arranged on a top surface and parts of side surfaces of the bottom region and configured to block second-conductivity-type charge carriers, a not-intentionally-doped (NID) intermediate region arranged on a top surface and side surfaces of the lower blocking layer and comprising a recombination region, a second-conductivity-type upper blocking layer arranged on a top surface and side surfaces of the intermediate region and configured to block first-conductivity-type charge carriers, and a second-conductivity-type top region arranged on a top surface and side surfaces of the upper blocking layer.

2. The electro-optical device according to claim 1, further comprising: a III-V-semiconductor capping layer having a higher band-gap than that of the III-V semiconductor material of the ridge structure and being arranged on an outer surface of the ridge structure covering at least surface regions between the lower blocking layer and the upper blocking layer.

3. The electro-optical device according to claim 1, wherein: the top region of the ridge structure comprises an upper part forming at least one fin structure narrower than and extending upwards from a lower part of the top region.

4. The electro-optical device according to claim 1, wherein: the bottom region of the ridge structure is partly arranged in a trench formed in the support region.

5. The electro-optical device according to claim 1, wherein: the bottom region of the ridge structure is grown onto a V-groove formed in the support region.

6. The electro-optical device according to claim 1, wherein: the intermediate region comprises one or more quantum wells and/or quantum dots and/or quantum wires as part of the recombination region.

7. The electro-optical device according to claim 1, wherein: the lower blocking layer and the upper blocking layer are each made of a III-V semiconductor material having a higher band-gap than that of a III-V semiconductor material forming the intermediate region.

8. The electro-optical device according to claim 1, wherein: the intermediate region is made of GaAs, InGaAs, or InP, and the lower blocking layer and the upper blocking layer are each made of InGaP or GaAsP.

9. The electro-optical device according to claim 8, wherein: the lower blocking layer and the upper blocking layer are each made of GaAsP with a P-content of 30-40%, and have an n-type doping level and a p-type doping level, respectively, between 1E+17 cm.sup.3 and 1E+20 cm.sup.3.

10. The electro-optical device according to claim 8, wherein: the lower blocking layer or the upper blocking layer is made of InGaP with an n-type doping level between 5E+16 cm.sup.3 and 5E+19 cm.sup.3 or with a p-type doping level between 5E+18 cm.sup.3 and 5E+20 cm.sup.3.

11. The electro-optical device according to claim 1, wherein: the ridge structure comprises a narrower portion arranged on the support region and a wider portion arranged on top of the narrower portion, the narrower portion comprises a lower part of the bottom region, and the wider portion comprises an upper part of the bottom region, the intermediate region, and at least a lower part of the top region.

12. The electro-optical device according to claim 1, wherein: the ridge structure is surrounded by a dielectric.

13. The electro-optical device according to claim 1, further comprising: a first electrode electrically contacting the top region and configured to inject the second-conductivity-type charge carriers into the ridge structure; and a second electrode electrically contacting the support region and configured to inject the first-conductivity-type charge carriers into the ridge structure.

14. The electro-optical device according to claim 1, being a part of: a laser, a light emitting diode, or an optical amplifier.

15. A method of fabricating a monolithic integrated electro-optical device, the method comprising: providing a first-conductivity-type Si-based support region; and processing a III-V-semiconductor-material ridge structure extending from the Si-based support region by: growing a first-conductivity-type lower region onto the support region, growing a first-conductivity-type lower blocking layer configured to block second-conductivity-type charge carriers onto a top surface and parts of side surfaces of the lower region, growing a NID intermediate region comprising a recombination region onto a top surface and side surfaces of the lower blocking layer, growing a second-conductivity-type upper blocking layer configured to block first-conductivity-type charge carriers onto a top surface and side surfaces of the intermediate region, and growing a second-conductivity-type top region onto a top surface and side surfaces of the upper blocking layer.

16. The method according to claim 15, further comprising: providing a III-V-semiconductor capping layer arranged on an outer surface of the ridge structure covering at least surface regions between the lower blocking layer and the upper blocking layer.

17. The method according to claim 15, further comprising: forming, as an upper part the top region of the ridge structure, at least one fin structure that is narrower than and extending upwards from a lower part of the top region.

18. The method according to claim 15, further comprising: providing one or more quantum wells and/or quantum dots and/or quantum wires as part of the recombination region.

19. The method according to claim 15, further comprising: providing a dielectric surrounding the ridge structure.

20. The method according to claim 15, further comprising: providing a first electrode electrically contacting the top region and configured to inject the second-conductivity-type charge carriers into the ridge structure; and providing a second electrode electrically contacting the support region and configured to inject the first-conductivity-type charge carriers into the ridge structure.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0070] The above described aspects and embodiments are explained in the following description of embodiments with respect to the enclosed drawings:

[0071] FIG. 1 shows an electro-optical device according to an embodiment of the disclosed technology.

[0072] FIG. 2A shows an electro-optical device according to an embodiment of the disclosed technology, and FIG. 2B shows a band diagram through a cross-section of the electro-optical device showing the two charge carrier blocking layers.

[0073] FIG. 3 shows a method according to an embodiment of the disclosed technology.

[0074] FIG. 4A shows a threshold current for an example GaAs-on-Si ridge electro-optical device (laser) according to an embodiment of the disclosed technology with and without charge carrier blocking layers, FIG. 4B shows an internal quantum efficiency with and without charge carrier blocking layers, and FIG. 4C shows a surface recombination efficiency with and without charge carrier blocking layers.

[0075] FIG. 5A and FIG. 5B shows two electro-optical devices according to embodiments of the disclosed technology.

[0076] FIG. 6 shows an example of a III-V-on-Si ridge electro-optical device.

[0077] FIG. 7 shows an example of a III-V-on-Si ridge electro-optical device, with indicated carrier flows and exposed III-V surfaces.

DETAILED DESCRIPTION OF CERTAIN ILLUSTRATIVE EMBODIMENTS

[0078] FIG. 1 shows a monolithic integrated electro-optical device 10 according to an embodiment of the disclosed technology, in particular a cross-section of the electro-optical device 10. The device 10 is particularly a III-V-on-Si ridge electro optical device. The electro-optical device 10 of FIG. 1 may in particular be a Laser, a LED, or an optical amplifier. The electro-optical device 10 may be fabricated using the nanoridge ART approach.

[0079] The device 10 particularly comprises a first-conductivity-type Si-based support region 11. The support region 11 may be a Si or Si-based (e.g., SiN) substrate. The support region 11 may also be a first-conductivity-type top region of an intrinsic Si or Si-based substrate, particularly of a SOI substrate.

[0080] The device 10 further comprises a III-V-semiconductor-material ridge structure 18 extending from the Si-based support region 11, wherein the ridge structure 18 contains a recombination region 15. The ridge structure 18 may be fabricated using the ART approach on the support region 11, i.e., may be grown in a high-aspect-ratio trench that is formed before in the support region 11. The ridge 12 may extend on the support region 11 along a direction, which is into the plane in the cross-section shown in FIG. 1.

[0081] In particular, the ridge structure 18 includes a plurality of different regions. Namely, the ridge structure 18 includes a first-conductivity-type bottom region 12, which is arranged on the support region 11. The bottom region 12 may be grown in the high-aspect ratio trench mentioned above. The bottom region 12 be narrow compared to the maximum width of the ridge structure 18.

[0082] The ridge structure 19 further includes a first-conductivity-type lower blocking layer 13, which is arranged on the top surface and on parts of the side surfaces of the bottom region 12, and is configured to block second-conductivity-type charge carriers. As can be seen in FIG. 1, the blocking layer 13 is non-planar, and may wrap partly around the bottom region 12. The lower blocking layer 13 may be made of a III-V semiconductor material having a higher band-gap than a III-V semiconductor material forming an intermediate region 14 of the ridge structure 18.

[0083] Accordingly, the ridge structure 18 further comprises the intermediate region 14, namely a NID intermediate region 14, which is arranged on the top surface and on side surfaces of the lower blocking layer 13, and contains the recombination region 15. The intermediate region 14 is exemplarily shown in FIG. 1 to be arranged on the entire side surface of the lower blocking layer 13.

[0084] Furthermore, the ridge structure 18 includes a second-conductivity-type upper blocking layer 16, which is arranged on the top surface and on side surfaces of the intermediate region 14, and is configured to block first-conductivity-type charge carriers. The blocking layer 16 may be arranged on the complete outer surface of the intermediate region 14, e.g., also on an exposed bottom surface as exemplarily shown in FIG. 1. Alternatively, a capping layer may be arranged on such an exposed bottom surface, as explained below in more detail. As can be seen in FIG. 1, the blocking layer 16 is non-planar, and may at wrap around the intermediate region. The upper blocking layer 16 may be made of a III-V semiconductor material having a higher band-gap than a III-V semiconductor material forming the intermediate region 14 of the ridge structure 18.

[0085] The ridge structure 18 comprises additionally a second-conductivity-type top region 17, which is arranged on the top surface and on side surfaces of the upper blocking layer 16. The top region 17 is exemplarily shown in FIG. 1 to be on the entire side surface of the upper blocking layer 16.

[0086] In the electro-optical device 10 shown in FIG. 1, the first-conductivity-type may be n-type and the second-conductivity-type p-type. First-conductivity-type charge carriers are thus electrons, and second-conductivity-type charge carriers are holed. However, these polarities could also be exchanged.

[0087] FIG. 2A shows an electro-optical device 10 according to an embodiment of the disclosed technology, in particular a cross-section of the electro-optical device 10, which builds on the device 10 shown in FIG. 1. Furthermore, FIG. 2B shows an exemplary band diagram through a cross-section of the electro-optical device 10 shown in FIG. 2A, wherein the cross-section is indicated in FIG. 2A by the dotted line. FIG. 2B exemplarily assumes that the first-conductivity-type is n-type, and the second-conductivity-type is p-type. Same elements in FIG. 1 and FIG. 2A share the same reference signs and function likewise. Accordingly, also the device 10 shown in FIG. 2A includes the Si-based support region 11, the III-V semiconductor material ridge structure 18, the III-V semiconductor capping layer 14, and the fin structure 15.

[0088] FIG. 2A further shows that the ridge structure 18 may include a narrower portion arranged on the support region 11, e.g., in a STI trench and/or V-groove 27 formed in the support region 11, and a wider portion arranged on top of the narrower portion. That is, the wider portion is freestanding supported by the narrower portion. The ridge structure 18 in other words is a freestanding ridge structure with a narrower foot and a wider body. The narrower portion includes a lower part 22 of the bottom region 12. The wider portion includes an upper part 23 of the bottom region 22, the intermediate region 14 and at least a lower part 24 of the top region 17. In FIG. 2A, the top region 17 of the ridge structure 18 includes an upper part 25, which forms at least one fin structure, i.e., is narrower than and extends upwards from the lower part 24 of the top region 17. The fin structure may be obtained by etching the top region of the ridge structure 18.

[0089] Along the extension direction of the ridge structure 12 (i.e., into the plane in FIG. 2A), the width of the fin structure 15 (left-right extension of the fin structure 15 in FIG. 2A) may vary. For instance, the fin structure 15 width may vary periodically from wider to narrower and again wider. Along the extension direction of the ridge structure 12, there may even be arranged a plurality of fin structures 15 one after the other. In particular, there may be selected parts without fin structure 15 on the top surface of the ridge structure 12, and other selected parts with fin structure 15 on the top surface of the ridge structure 12. This arrangement can also be considered as a fin structure 15 with varying width along the extension direction of the ridge structure 12, wherein the width becomes zero in selected parts.

[0090] The electro-optical device 10 shown in FIG. 2A further comprises a III-V-semiconductor capping layer 20 (e.g., a passivation layer) having a higher band-gap than the III-V semiconductor material of the ridge structure 18 and being arranged on an outer surface of the ridge structure 18. In FIG. 2A, the capping layer 20 is shown to encapsulate the wider portion of the ridge structure 18. However, the capping layer 20 may also surround at least partly the narrower portion of the ridge structure 18. The capping layer 20 may also be arranged only on parts of the outer surface of the wider portion, e.g., on the surface area between the two blocking layers 13 and 16, if the upper blocking layer 16 does not wrap completely around the outer surface of the intermediate region 14, i.e., for instance, on the above-mentioned exposed bottom surface of the intermediate region 14.

[0091] Furthermore, FIG. 2A shows that the ridge structure 18 and the capping layer 20 may be surrounded by a dielectric 26, e.g., an oxide like SiO.sub.2.

[0092] Furthermore, the electro-optical device 10 may include a first electrode 21, which is in electrical contact with the top region 17, particularly the fin structure 25. The first electrode 21 is particularly configured to inject second-conductivity-type charge carriers into the ridge structure 18, and also to collect excess first-conductivity-type charge carriers from the ridge structure 18, i.e., such first-conductivity-type charge carriers that did not recombine in the recombination region 15. The device 10 may also include a second electrode 28, which is in electrical contact with the support region 11. The second electrode 28 is configured to inject first-conductivity-type charge carriers into the ridge structure 18, and also to collect excess second-conductivity-type charge carriers from the ridge structure 18, i.e., such second-conductivity-type charge carriers that were injected by the first electrode 21 and did not recombine in the recombination region 15 with the first-conductivity-type charge carriers injected by the second electrode 28. The first and/or the second electrode may be a metal contact or plug, e.g., formed by using W, Cu or another suitable metal.

[0093] Both electro-optical devices 10 shown in FIG. 1 and FIG. 2A include the lower blocking layer 13 and the upper blocking layer 16, which are used to respectively block electrons and holes, i.e., different charge carrier types. Adding different doping types to the blocking layers 13 and 16i.e., making them respectively of the first-conductivity type and the second-conductivity typemakes them charge-carrier-species selective blocking layers. Doping is also added to parts of the ridge structure 18, particularly below the lower blocking layer 13 and above the upper blocking layer 16, respectively. As shown in FIG. 2B, this will align the conduction/valence bands of the blocking layers 13 and 16 and the access portions of the ridge structure 18, thus allowing for efficient conduction of the majority charge carriers through the layers 13 and 16, while preventing minority charge carriers to pass. In other words, the higher band-gap of the blocking layers 13 and 16 compared to the ridge structure semiconductor material will prevent minority carriers from passing through.

[0094] The level of p- and n-doping in the two blocking layers 13 and 16 and the ridge structure 18, respectively, is dependent on the choice of the semiconductor materials used for making the blocking layers 13 and 16, and more specifically dependent on the band-offsets between the blocking layers 13 and 16 and the ridge structure 18. For example: [0095] InGaP lattice matched to a GaAs ridge structure material has a high valence band offset to the GaAs (300-400 meV), compared to a moderate conduction band offset (100-150 meV). Thus, InGaP is ideal as a hole blocking layer in a GaAs ridge structure, and would for this require only moderate n-doping (e.g., 1E+17 cm.sup.3). InGaP can also be used as an electron blocking layer, but would require a higher p-doping density (e.g., 1E+19 cm.sup.3) to be sufficiently effective. [0096] GaAsP with a 30-40% phosphorous content has a more symmetric band offset compared to GaAs (as exemplary ridge structure material), and can thus function as a both a hole and electron blocking layer 13 and/or 16 with a moderate doping density (e.g., 1E+17 cm.sup.3 for n-doping or p-doping).

[0097] Notably, the semiconductor and/or doping materials used for the lower blocking layer 13 and the upper blocking layer 16, respectively, are not required to be the same.

[0098] FIG. 3 shows schematically a method 30 for fabricating the device 10 according to an embodiment of the disclosed technology. The method 30 includes at least the following steps. A step 31 of providing a first-conductivity-type Si-based support region 11, and a step 32 of processing a III-V-semiconductor-material ridge structure 18 extending from the Si-based support region 11.

[0099] The step 32 may include in particular: A step 33 of growing a first-conductivity-type lower region 12 onto the support region 11; a step 34 of growing a first-conductivity-type lower blocking layer 13 for blocking second-conductivity-type charge carriers onto the top surface and onto parts of side surfaces of the lower region 12; a step 35 of growing a NID intermediate region 14 containing a recombination region 15 onto the top and side surfaces of the lower blocking layer 13; a step 36 of growing a second-conductivity-type upper blocking layer 16 for blocking first-conductivity-type charge carriers onto the top and side surfaces of the intermediate region 14; and a step 37 of growing a second-conductivity-type top region 17 onto the top and side surfaces of the upper blocking layer 16.

[0100] Notably, with the method 30, a plurality of electro-optical devices 10 may be fabricated in parallel, particularly by providing a plurality of ridge structures 18 at the same time next to another on the Si-based support region 11. For instance, the Si-based support region 11 may belong to (or be) a full wafer, particularly a 200 mm or 300 mm wafer. The wafer may finally be diced, in order to separate individual electro-optical devices 10. If the ART approach is used to produce the electro-optical devices 10, a plurality of STI trenches may be formed in the support region 11, and a ridge structure 18 may be epitaxially grown in each of the STI trenches. The method 30 is, due to its relative simplicity, able to achieve high yields of fabricating the electro-optical devices 10.

[0101] Numerical simulations show that the incorporation of the charge carrier blocking layers 13 and 16 in the electro-optical device 10, when used as a Laser, significantly improve its performance.

[0102] In particular, FIG. 4A shows the threshold current density for the electro-optical device 10 (2 barriers) compared with a reference device (the device shown in FIG. 6; No barriers). The compared devices particularly included a 1 mm long section of a GaAs-on-Si ridge structure with cleaved facets (Fabry-Prot cavity). The charge carrier blocking layers 13 and 16 significantly improve the threshold current by almost an order of magnitude (i.e., from 11 kA/cm.sup.2 to 1 kA/cm.sup.2).

[0103] FIG. 4B compares the internal QE, defined as the fraction of carriers that recombine radiatively in the recombination region 15 (including QWs in this case) to the total number of carriers injected into the device. This shows that the introduction of the blocking layers 13 and 16 will improve the QE from about 6% at 10 kA/cm2 (without blocking layers) to 78% at 10 kA/cm.sup.2 with the two blocking layers 13 and 16.

[0104] This sharp increase of the IQE can be attributed to the fact that virtually all surface recombination is eliminated due to the carrier blocking layers 13 and 16, which can be seen in FIG. 4C. In particular, the surface recombination efficiency drops to zero with two charge carrier blocking layers 13 and 16, regardless of the current density (between 0 and 50000 A/cm.sup.2).

[0105] By introducing the two blocking layers 13 and 16 the following was also considered: [0106] Although the addition of doping impurities to the blocking layers 13 and 16, and the access regions of the ridge structure 18, may provide a low resistance path for the majority carriers to reach the recombination region 15, small interface depletion regions may cause non-zero potential barriers that can cause a voltage drop, hence consuming electrical power. However, simulations show that the additional series resistance is negligible compared to other contributing factors such as contact resistance. In practice, this small increase in diode series resistance does not harm laser performance of the electro-optical device 10. [0107] Due to the additional doping impurities close to the recombination region 15, there may be an increase in optical propagation loss through the III-V ridge structure 18 due to free carrier absorption. However, by careful choice of the blocking layers 13 and 16 (see details above), the doping densities can be kept relatively low, which does not increase the optical loss to an unacceptable level.

[0108] FIG. 5A and FIG. 5B show electro-optical devices 50 and 51, respectively, according to embodiments of the disclosed technology, which build on the electro-optical device 10 shown in FIG. 1. Same elements in FIG. 1, FIG. 5A and FIG. 5B share the same reference signs and function likewise. The devices 50 and 51 in FIG. 5A and FIG. 5B each include only one of the blocking layers 13 or 16 of the device 10 shown in FIG. 1. In particular, the device 50 shown in FIG. 5A includes only the (lower) blocking layer 13, while the device 51 in FIG. 5B includes only the (upper) blocking layer 16.

[0109] Thus, the device 50 shown in FIG. 5A is a monolithic integrated electro-optical device 50 comprising a first-conductivity-type Si-based support region 11, and a III-V-semiconductor-material ridge structure 18 extending from the Si-based support region 11. The ridge structure 18 includes a first-conductivity-type bottom region 12 arranged on the support region 11, a first-conductivity-type blocking layer 13 arranged on the top surface and parts of the side surfaces of the bottom region 12 and configured to block second-conductivity-type charge carriers, a NID intermediate region 14 arranged on the top and side surfaces of the blocking layer 13 and containing a recombination region 15, and a second-conductivity-type top region 17 arranged on the top and side surfaces of the intermediate region 14.

[0110] The device 51 shown in FIG. 5B is a monolithic integrated electro-optical device 51 comprising a first-conductivity-type Si-based support region 11, and a III-V-semiconductor-material ridge structure 18 extending from the Si-based support region 11. The ridge structure 18 includes a first-conductivity-type bottom region 12 arranged on the support region 11, a NID intermediate region 14 arranged on the top surface and parts of the side surfaces of the bottom region 12 and containing a recombination region 15, a second-conductivity-type blocking layer 16 arranged on the top and side surfaces of the intermediate region 14 and configured to block first-conductivity-type charge carriers, and a second-conductivity-type top region 17 arranged on the top and side surfaces of the blocking layer 16.