III-V-ON-SILICON NANORIDGE OPTO-ELECTRONIC DEVICE WITH A REGROWN FIN STRUCTURE

Abstract

The disclosed technology relates to the development of a monolithic active electro-optical device. In some embodiments, the electro-optical device may be fabricated using the so-called nanoridge aspect ratio trapping (ART) approach. In one aspect, the electro-optical device is a monolithic integrated electro-optical device comprising a first-conductivity-type Si-based support region and a III-V-semiconductor-material ridge structure extending from the Si-based support region, wherein the ridge structure contains a recombination region. Furthermore, the device comprises a III-V-semiconductor capping layer having a higher band-gap than that of the III-V semiconductor material of the ridge structure and being formed on an outer surface of the ridge structure. The device further comprises at least one second-conductivity-type III-V-semiconductor fin structure narrower than and extending upwards from a top surface of the ridge structure through an opening in the capping layer on the top surface of the ridge structure.

Claims

1. A monolithic integrated electro-optical device, comprising: a first-conductivity-type Si-based support region; a III-V-semiconductor-material ridge structure extending from the Si-based support region, the ridge structure containing a recombination region; a III-V-semiconductor capping layer having a higher band-gap than that of the III-V semiconductor material of the ridge structure and being formed on an outer surface of the ridge structure; and at least one second-conductivity-type III-V-semiconductor fin structure narrower than and extending upwards from a top surface of the ridge structure through an opening in the capping layer on the top surface of the ridge structure.

2. The electro-optical device according to claim 1, wherein: the fin structure is grown onto the top surface of the ridge structure.

3. The electro-optical device according to claim 1, wherein: a doping level in the fin structure is larger than 1E+17 cm.sup.3.

4. The electro-optical device according to claim 1, wherein: a doping level in the fin structure increases along a direction away from the top surface of the ridge structure.

5. The electro optical device according to claim 1, wherein: a width of the fin structure varies along an extension direction of the ridge structure tangent to the top surface of the ridge structure.

6. The electro-optical device according to claim 1, wherein: the ridge structure, capping layer and fin structure are surrounded by a dielectric, and the fin structure is grown in a trench into the dielectric above the ridge structure.

7. The electro-optical device according to claim 1, further comprising: a first electrode electrically contacting the fin structure and configured to inject second-conductivity-type charge carriers into the ridge structure; and a second electrode electrically contacting the support region and configured to inject first-conductivity-type charge carriers into the ridge structure.

8. The electro-optical device according to claim 1, wherein: the ridge structure is partly arranged in a trench formed in the support region, and/or the ridge structure is grown onto a V-groove formed in the support region.

9. The electro-optical device according to claim 1, wherein: the ridge structure comprises a narrower portion arranged on the support region and a wider portion arranged on top of the narrower portion.

10. The electro-optical device according to claim 1, wherein: the ridge structure comprises one or more quantum wells and/or quantum dots and/or quantum wires in the recombination region.

11. The electro-optical device according to claim 1, being a part of: a laser, a light emitting diode, or an optical amplifier.

12. A method of fabricating a monolithic integrated electro-optical device, the method comprising: providing a first-conductivity-type Si-based support region; growing a III-V-semiconductor-material ridge structure containing a recombination region onto the support region; growing a III-V-semiconductor capping layer having a higher band-gap than that of the III-V semiconductor material of the ridge structure onto an outer surface of the ridge structure; forming an opening in the capping layer to expose a part of a top surface of the ridge structure; and growing at least one second-conductivity-type III-V-semiconductor fin structure narrower than the top surface of the ridge structure onto the exposed part of the top surface of the ridge structure.

13. The method according to claim 12, further comprising: surrounding the ridge structure by a dielectric, after growing the capping layer; and etching a trench into the dielectric above the ridge structure and into the capping layer to form the opening.

14. The method according to claim 13, wherein: the fin structure is grown in the trench etched into the dielectric and onto the exposed part of the top surface.

15. The method according to claim 12, wherein: growing the fin structure comprises increasing a doping level of the second-conductivity-type III-V-semiconductor of the fin structure with progressing growth.

16. The method according to claim 12, further comprising: growing a second-conductivity-type layer of III-V semiconductor material below the top surface of the ridge structure.

17. The method according to claim 12, wherein: a doping level in the fin structure is larger than 1E+17 cm.sup.3.

18. The method according to claim 12, further comprising: forming a first electrode electrically contacting the fin structure and configured to inject second conductivity type charge carriers into the ridge structure; and forming a second electrode electrically contacting the support region and configured to inject first conductivity type charge carriers into the ridge structure.

19. The method according to claim 12, wherein: the ridge structure comprises a narrower portion arranged on the support region and a wider portion arranged on top of the narrower portion.

20. The method according to claim 12, wherein: the ridge structure comprises one or more quantum wells and/or quantum dots and/or quantum wires in the recombination region.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0059] The above described aspects and implementations are explained in the following description of embodiments with respect to the enclosed drawings:

[0060] FIG. 1 shows an electro-optical device according to an embodiment of the disclosed technology.

[0061] FIG. 2A shows an electro-optical device according to an embodiment of the disclosed technology, and FIG. 2B shows a doping density in the electro-optical device.

[0062] FIG. 3 shows a method according to an embodiment of the disclosed technology.

[0063] FIG. 4 shows a parameter comparison between an etched fin structure and a (re-)grown fin structure.

[0064] FIG. 5 shows an example of a III-V-on-Si ridge electro-optical device.

[0065] FIG. 6 shows an example of a III-V-on-Si ridge electro-optical device, with indicated carrier flows and exposed III-V surfaces.

DETAILED DESCRIPTION OF CERTAIN ILLUSTRATIVE EMBODIMENTS

[0066] FIG. 1 shows a monolithic integrated electro-optical device 10 according to an embodiment of the disclosed technology, in particular a cross-section of the electro-optical device 10. The device 10 is particularly a III-V-on-Si ridge electro optical device. The electro-optical device 10 of FIG. 1 may in particular be a laser, a LED, or an optical amplifier. The electro-optical device 10 may be fabricated using the nanoridge ART approach.

[0067] The device 10 particularly comprises a first-conductivity-type Si-based support region 11. The support region 11 may be a Si or Si-based (e.g., SiN) substrate. The support region 11 may also be a first-conductivity-type top region of an intrinsic Si or Si-based substrate, particularly of a SOI substrate.

[0068] The device 10 further comprises a III-V-semiconductor-material ridge structure 12 extending from the Si-based support region 11, wherein the ridge structure 12 contains a recombination region 13. The ridge structure 12 may be fabricated using the ART approach on the support region 11, i.e., may be grown in a high-aspect-ratio trench formed before in the support region. The ridge structure 12 may extend on the support region 11 along a direction, which is into the plane in the cross-section shown in FIG. 1.

[0069] The device 10 further comprises a III-V-semiconductor capping layer 14 having a higher band-gap than the III-V semiconductor material of the ridge structure 12 and being provided on an outer surface of the ridge structure 12. In FIG. 1, the capping layer 14 is shown to encapsulate the ridge structure 12. However, the capping layer 14 may also surround only part of the ridge structure 12, i.e., may only be provided on parts of the outer surface of the ridge structure 12. In particular, in some embodiments the ridge structure 12 comprises a narrower portion arranged on the support region 11, and a wider portion carried on the narrower portion. In this case, the capping layer 14 may at least be provided on the outer surface of the wider portion.

[0070] The device 10 further comprises at least one second-conductivity-type III-V-semiconductor fin structure 15, which is narrower than and extends upwards from the top surface of the ridge structure 12. In particular, it extends upwards through an opening 16 formed in the capping layer 15, which is provided on the top surface of the ridge structure 12. After the forming of this opening, capping layer material remains on the top surface on both sides of the opening. The fin structure 15 may be at least 50% narrower than the width of the top surface of the ridge structure, i.e., it may be half as wide as the ridge structure at its top surface. The fin structure 15 may even be 60%, 70% or even 80% narrower than the top surface of the ridge structure 12. Along the extension direction of the ridge structure 12 (i.e., into the plane in FIG. 1), the width of the fin structure 15 (left-right extension of the fin structure 15 in FIG. 1) may vary. For instance, the fin structure 15 width may vary periodically from wider to narrower and again wider. Along the extension direction of the ridge structure 12, there may even be arranged a plurality of fin structures 15 one after the other. In particular, there may be selected parts without fin structure 15 on the top surface of the ridge structure 12, and other selected parts with fin structure 15 on the top surface of the ridge structure 12. This arrangement can also be considered as a fin structure 15 with varying width along the extension direction of the ridge structure 12, wherein the width becomes zero in selected parts.

[0071] Since there is capping layer material on the top surface of the ridge structure 12, in the device 10 according to an embodiment of the disclosed technology, the fin structure 15 is not formed by etching as in the device shown in FIG. 5, but is provided on top of the ridge structure 12 after the ridge structure 12 and the capping layer 14 are made. In particular, the fin structure 12 may be regrown, i.e., grown on the ridge structure 12 after the ridge structure 12 is grown, and after an opening in the capping layer 14 on the ridge structure 12 is formed.

[0072] In the electro-optical device 10 shown in FIG. 1, the first-conductivity-type may be n-type and the second-conductivity-type p-type. First-conductivity-type charge carriers are thus electrons, and second-conductivity-type charge carriers are holed. However, these polarities could also be exchanged.

[0073] FIG. 2A shows an electro-optical device 10 according to an embodiment of the disclosed technology, in particular a cross-section of the electro-optical device, which builds on the device 10 shown in FIG. 1. Further, FIG. 2B shows an exemplary doping density in the device 10 shown in FIG. 2A. FIG. 2B exemplarily assumes that the first-conductivity-type is n-type, and the second-conductivity-type is p-type. Same elements in FIG. 1 and FIG. 2A share the same reference signs and function likewise. Accordingly, also the device 10 shown in FIG. 2A includes the Si-based support region 11, the III-V semiconductor material ridge structure 12, the III-V semiconductor capping layer 14, and the fin structure 15.

[0074] FIG. 2A further shows that the ridge structure 12 may include a narrower portion 23 arranged on the support region 11, e.g., in a STI trench and/or V-groove 26 formed in the support region 11, and a wider portion 22 arranged on top of the narrower portion 23. That is the wider portion 22 is freestanding supported by the narrower portion 23. The ridge structure 12 in other words is a freestanding ridge structure with a narrower foot and a wider body.

[0075] Further, FIG. 2A shows that the ridge structure 12, the capping layer 14 and the fin structure 15 may be surrounded by a dielectric 24, e.g., an oxide like SiO2. In particular, the fin structure 15 may be grown in a trench, which is provided in (e.g., etched into) the surrounding dielectric 24, wherein the dielectric trench is arranged above the ridge structure 12.

[0076] Further, the electro-optical device 10 may include a first electrode 21, which is in electrical contact with the fin structure 15. The first electrode 21 is particularly configured to inject second-conductivity-type charge carriers into the ridge structure 12, and also to collect excess first-conductivity-type charge carriers from the ridge structure 12, i.e., such first-conductivity-type charge carriers that did not recombine in the recombination region 13. The device 10 may also include a second electrode 25, which is in electrical contact with the support region 11. The second electrode 25 is configured to inject first-conductivity-type charge carriers into the ridge structure 12, and also to collect excess second-conductivity-type charge carriers from the ridge structure 12, i.e., such second-conductivity-type charge carriers that were injected by the first electrode 21 and did not recombine in the recombination region 13 with the first-conductivity-type charge carriers injected by the second electrode 25. The first and/or the second electrode may be a metal contact or plug, e.g., formed by using W, Cu or another suitable metal.

[0077] Like in the device 10 shown in FIG. 1, also in the device 10 of FIG.2 the fin structure 15, which is in particular not obtained by etching it from/out of the ridge structure 12, but the fin structure 15 is grown on top of the ridge structure 12, i.e., it is regrown after growing and further preparing the ridge structure 12. Thereby, a ridge structure/fin structure interface 20 is formed. A fabrication of the device 10, and in particular of the fin structure 15, may thus include the following steps: [0078] Before growing the capping layer 14 (e.g., based on InGaP), a sufficiently thick highly-doped layer of second-conductivity-type III-V semiconductor material (e.g., p-doped GaAs) may be grown as top region of the ridge structure 12. After that, the capping layer 14 is grown onto an outer surface of the ridge structure 12. [0079] After growing the III-V-semiconductor-material ridge structure 12, the dielectric 24 is deposited, in order to fill the space around and above the ridge structure 12 (and the capping layer 14). [0080] The dielectric 24 may then be planarized (e.g., by using Chemical Mechanical polishing (CMP)), while, in some embodiments, still keeping a sufficiently thick layer of dielectric 24 above the III-V ridge structure 12. [0081] Above the ridge structure 12, a narrow trench may then be formed, particularly etched, into the dielectric 24. Thereby, a part of the top surface of the III-V ridge structure is exposed. [0082] In the trench, also the capping layer 14 (e.g., InGaP) is removed, in order to expose the highly-doped second-conductivity-type layer of the ridge structure 12 mentioned above. Notably, the capping layer 14 may be removed by the dielectric etching step or by a separate step of e.g., selective capping layer etching. [0083] A second selective area epitaxy step (referred to as the regrowth step) may then be performed, in order to fill the newly created narrow trench in the dielectric 24 with, in some embodiments, highly-doped second-conductivity-type III-V semiconductor material. This step creates the fin structure 15. The doping density can be gradually or step-wise increased in this step, i.e., as the III-V semiconductor material fills the trench, i.e., as the growth of the fin structure 15 progresses. [0084] After the regrowth step of the fin structure 15, another planarization step can be carried out, and the fabrication process may proceed with standard contact and metallization steps, e.g., to provide the first electrode 21 and/or second electrode 25.

[0085] FIG. 3 shows schematically a method 30 for fabricating the device 10 according to an embodiment of the disclosed technology. The method 30 includes at least the following steps. A step 31 of providing a first-conductivity-type Si-based support region 11. A step 32 of growing a III-V-semiconductor-material ridge structure 12 containing a recombination region 13 onto the support region 11. A step 33 of growing a III-V-semiconductor capping layer 14 having a higher band-gap than the III-V semiconductor material of the ridge structure 12 onto an outer surface of the ridge structure 12. A step 34 of forming an opening in the capping layer 14 to expose a part of the top surface of the ridge structure 12. A step 35 of growing at least one second-conductivity-type III-V-semiconductor fin structure 15 narrower than the top surface of the ridge structure 13 onto the exposed part of the top surface of the ridge structure 12.

[0086] Notably, with the method 30, a plurality of electro-optical devices 10 may be fabricated in parallel, particularly by providing a plurality of ridge structures 12 at the same time next to another on the Si-based support region. For instance, the Si-based support region 11 may belong to (or be) a full wafer, particularly a 200 mm or 300 mm wafer. The wafer may then be diced, in order to separate individual electro-optical devices 10. If the ART approach is used to produce the electro-optical devices 10, a plurality of STI trenches may be formed in the support region 11, and a ridge structure 12 may be epitaxially grown in each of the STI trenches. The method 30 is, due to its relative simplicity, able to achieve high yields of fabricating the electro-optical devices 10.

[0087] The advantages provided by the above-described embodiments of the electro-optical device 10 and method 30 are at least those listed below: [0088] The regrown fin structure 15 may be designed much narrower than the ridge structure 12 (top surface), which allows it to more effectively act as a fin forcing the optical mode down into the ridge structure 12, and keeping it away from e.g., a metallic contact on top of the fin structure 15. [0089] Unlike in the fin etching approach described with respect to FIG. 5 and FIG. 6, the amount of removed capping layer material (e.g., the InGaP) is very small on the top surface of the ridge structure 12. This means that the ridge structure 12 is still largely protected by the capping layer 14 from surface recombination, in particular everywhere except for in the trench that serves as a seed for the regrown fin structure 15. The interface between the regrown fin structure 15 and the surface of the dielectric 24 is exposed, but if the regrown fin structure 15 is doped sufficiently high (e.g., with a second-conductivity-type doping of >1E+19 cm.sup.3), the electric field resulting at the depletion region between ridge structure 12 and fin structure 15 will be sufficiently strong to keep first-conductivity-type charge carriers from reaching into the regrown fin structure 15 and causing surface recombination. [0090] In some embodiments, either side of the ridge structure/fin structure interface 20 is highly doped (second-conductivity-type). The higher charge carrier concentration will result in narrower potential barriers, which are easier to tunnel through, thus significantly improving the quality of the electric interface 20. [0091] Moreover, by making sure that the top region of the ridge structure 12 is already highly-doped (second-conductivity type), the intrinsic/doped interface is arranged well below the ridge structure/regrown fin structure interface 20, thus preventing that first-conductivity-type charge carriers reach the ridge structure/fin structure interface and cause non-radiative charge carrier recombination.

[0092] FIG. 4 shows an overview of some parameters of the electro-optical device 10 including the regrown fin structure 15 comparison to the example device with the etched fin structure. It can be seen from the table shown in FIG. 4 that the device 10 according to embodiments of the disclosed technology shows better (lower) transparency current density, lower absorption loss, higher injection efficiency, and only a marginally higher series resistance.

[0093] In summary, the embodiments of the disclosed technology are based on forming the fin structure 15 on the ridge structure 12, instead of etching it from the ridge structure 12. Thus, the laser mode of the electro-optical device 10 will have lower absorption loss, because on the one hand the mode is pushed away from the electrode 21, but still has acceptable injection efficiency, because non-radiative recombination at the surface or defects is prevented.