METHOD AND APPARATUS FOR OPTICAL PULSE SEQUENCE GENERATION
20230006760 · 2023-01-05
Inventors
- Ke LI (Southampton, GB)
- David John THOMSON (Southampton,, GB)
- Shenghao LIU (Southampton,, GB)
- Graham Trevor REED (Southampton,, GB)
- Weiwei ZHANG (Southampton,, GB)
- Wei CAO (Southampton,, GB)
Cpc classification
International classification
Abstract
A method of generating multiple channels of optical pulses comprises: providing a continuous wave optical input having an optical power; dividing the optical power of the optical input into equal consecutive slices in the time domain; and allocating the consecutive slices sequentially to two or more optical outputs such that each output forms a channel of optical pulses of equal pulse repetition rate shifted in time relative to the or each other channel.
Claims
1. A method of generating multiple channels of optical pulses, comprising: providing a continuous wave optical input having an optical power; dividing the optical power of the optical input into equal consecutive slices in the time domain; and allocating the consecutive slices sequentially to two or more optical outputs such that each output forms a channel of optical pulses of equal pulse repetition rate shifted in time relative to the or each other channel.
2. A method according to claim 1, further comprising modulating the optical power amplitude of the optical pulses in at least one channel to encode information.
3. A method according to claim 1, in which the optical power amplitude is modulated to encode binary data, the method further comprising combining the channels by interleaving the optical pulses in time to form a multiplexed signal comprising all the optical pulses.
4. A method according to claim 1, in which the optical power amplitude is modulated to encode one or more analogue electrical signals, the method further comprising converting a power measurement of the optical pulses in each channel into a digital output signal.
5. A method according to claim 4, in which the one or more analogue electrical signals comprises an analogue electrical signal modulated onto the continuous wave optical input prior to formation of the optical pulses.
6. A method according to claim 4, in which the one or more analogue electrical signals are modulated onto each channel of optical pulses after formation of the pulses.
7. A method according to claim 1, in which dividing the optical power and allocating the consecutive slices comprises inputting the continuous wave optical input into an first electro-optic modulator, driving two arms of the electro-optic modulator with drive signals comprising a first pair of oscillating voltages with a phase difference of 180°, and passing the modulated optical input through a first optical combiner configured to pass alternate portions of the optical power to two output ports.
8. A method according to claim 7, in which the two output ports each output one of the channels of optical pulses, such that two channels of optical pulses are formed.
9. A method according to claim 7, further comprising inputting the output from each of the two output ports to a further electro-optic modulator, the two arms of which are driven with drive signals comprising a further pair of oscillating voltages with a phase difference of 180°, and a phase difference of 90° from the first pair of oscillating voltages, and passing the modulated output through a further optical combiner, such that the four output ports of the two further optical combiners each output one of the channels of optical pulses, so that four channels of optical pulses are formed.
10. A method according to claim 7, in which the first electro-optic modulator and the further electro-optic modulators comprises Mach-Zehnder modulators, and the first optical combiners and the further optical combiners comprise multimode interference structures.
11. A method according to claim 7, further comprising passing the optical pulses of each channel through a modulator module configured to modulate the optical power amplitude of the optical pulses to encode binary data, in which the binary data is embedded into drive signals for the modulator modules which are triggered with clock signals corresponding to the pairs of oscillating voltages used to drive the electro-optic modulators, in order to synchronise the modulation with the time and repetition rate of the optical pulses in each channel.
12. A method according to claim 11, further comprising passing the clock signals through variable delay lines to compensate for any optical propagation delay experienced by the optical pulses before arrival at the modulator modules.
13. A method according to claim 7, further comprising passing the optical pulses of each channel through a modulator module configured to modulate the optical power amplitude of the optical pulses to encode binary data, the modulator module comprising modulator arms with segmented drive electrodes, in which the binary data is embedded into drive signals for the segmented drive electrodes which have a pulse width equal to or greater than an optical propagation time for the optical pulses to propagate through the modulator arms.
14. A method according to claim 7, further comprising passing the optical pulses of at least one channel through a modulator module configured to modulate the optical power amplitude of the optical pulses to encode binary data, and passing the optical pulses of at least one other channel through a modulator module configured to modulate the optical power amplitude of the optical pulses to encode analogue data.
15. A method according to claim 11, further comprising combining the modulated optical pulses of each channel by interleaving the optical pulses in time to form a multiplexed signal.
16. A method according to claim 15, further comprising transmitting the multiplexed signal, receiving the multiplexed signal, and demultiplexing the multiplexed signal to separate the modulated optical pulses back into the channels.
17. A device for generating multiple channels of optical pulses, the device comprising: an electro-optic modulator configured to receive an input comprising a continuous wave optical input having an optical power; a signal generator configured to generate drive signals for the electro-optic modulator comprising a first pair of oscillating voltages with a phase difference of 180°; and an optical combiner configured to receive the modulated optical power from the electro-optic modulator and pass alternate portions of the optical power to two output ports; in order to divide the optical power of the optical input into equal consecutive slices in the time domain, and allocate the consecutive slices sequentially to the two output ports such that the output from each output port forms a channel of optical pulses of equal pulse repetition rate shifted in time relative to the other channel.
18. A device according to claim 17, in which the signal generator is further configured to generate a second pair of oscillating voltages with a phase difference of 180° and a phase difference of 90° from the first pair of oscillating voltages; and the device further comprises two further electro-optic modulators each configured to receive the optical pulses output from an output port of the optical combiner and driven with the second pair of oscillating voltages; and two further optical combiners each configured to receive the modulated optical pulses from one of the further electro-optic modulators, and pass alternate portions of the optical power to two output ports; such that the four output ports of the two further optical combiners each output a channel of optical pulses of equal pulse repetition rate shifted in time relative to the other channels.
19. A device according to claim 17, in which the electro-optic modulator or modulators comprise Mach-Zehnder modulators, and the optical combiner or combiners comprise multimode interference structures.
20. A device according to claim 17, further comprising modulator modules each configured to receive the optical pulses of a channel and modulate the optical power amplitude of the optical pulses to encode binary data, and drive modules for each modulator module configured to generate drive signals for the corresponding modulator module in which the binary data is embedded.
21. A device according to claim 20, in which the signal generator is configured to generate clock signals corresponding to the pairs of oscillating voltages, and the drive modules are configured to be triggered with the clock signals in order to synchronise the modulation with the time and repetition rate of the optical pulses in each channel.
22. A device according to claim 21, further comprising variable delay lines for the clock signals configured to compensate for any optical propagation delay experienced by the optical pulses before arrival at the modulator modules.
23. A device according to claim 20, in which each modulator module comprises modulator arms with segmented drive electrodes, and the drive modules are configured to generate drive signals which have a pulse width equal to or greater than an optical propagation time for the optical pulses to propagate through the modulator arms.
24. A device according to claim 17, further comprising modulator modules each configured to receive the optical pulses of a channel and modulate the optical power amplitude of the optical pulses to encode data, wherein at least one modulator module is configured to encode binary data and at least one modulator module is configured to encode analogue data.
25. A device according to claim 20, further comprising one or more optical combiners to receive the modulated optical pulses of each channel and combine the pulses to form a multiplexed signal by interleaving the pulses in time.
26. A device according to claim 25, further comprising an optical routing component configured to transmit the multiplexed signal to a required destination.
27. A device according to claim 26, further comprising a demultiplexing component configured to receive the multiplexed signal from the optical routing component and separate the modulated optical pulses into the channels.
28. A device according to claim 17, further comprising: modulator modules each configured to receive the optical pulses of a channel and modulate the optical power amplitude of the optical pulses with one or more analogue electrical signals; photodetectors each configured to detect the power of the optical pulses in a channel and output a corresponding electrical signal; and analogue-to-digital converters each configured to convert one of the electrical signals to a digital binary signal.
29. A device according to claim 28, in which the signal generator is configured to generate clock signals corresponding to the pairs of oscillating voltages, and the analogue-to-digital converters are configured to be triggered with the clock signals in order to synchronise the conversion with the time and repetition rate of the optical pulses in each channel.
30. A device according to claim 17, further comprising: a modulator module configured to modulate the continuous wave optical input with an analogue electrical signal before the continuous wave optical input is received by the electro-optic modulator; photodetectors each configured to detect the power of the optical pulses in a channel and output a corresponding electrical signal; and analogue-to-digital converters each configured to convert one of the electrical signals to a digital binary signal.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] For a better understanding of the invention and to show how the same may be carried into effect reference is now made by way of example to the accompanying drawings in which:
[0012]
[0013]
[0014]
[0015]
[0016]
[0017]
[0018]
[0019]
[0020]
[0021]
[0022]
[0023]
[0024]
[0025]
[0026]
[0027]
[0028]
[0029]
[0030]
[0031]
[0032]
[0033]
DETAILED DESCRIPTION
[0034] Aspects and features of certain examples and embodiments are discussed/described herein. Some aspects and features of certain examples and embodiments may be implemented conventionally and these are not discussed/described in detail in the interests of brevity. It will thus be appreciated that aspects and features of apparatus and methods discussed herein which are not described in detail may be implemented in accordance with any conventional techniques for implementing such aspects and features.
[0035]
[0036] The modulators 8 each output the modulated pulses sequences into a waveguide having an optical delay line 11 comprising one or more spiral waveguide portions 12, which act to increase the length of the respective waveguides and hence increase the propagation time for light in each channel. Recalling that the symbol period is Ts, each optical delay line 11 introduces a delay which is a multiple of the symbol period in order to offset the pulses between the channels by an appropriate amount to achieve the symbol rate fs. Hence, a first channel has no delay line so provide a zero delay, OTs, a second channel has a delay line that delays by Ts, a third channel delays by 2 Ts and the fourth channel delays by 3 Ts. In this example each spiral waveguide portion 12 is designed to delay by Ts, and each channel has a number of spiral waveguide portions 12 that gives the desired total delay. Hence, the output 13 from the delay lines 11 is the four pulse sequences each delayed relative to the original sequence timing by a multiple of Ts. In order to achieve the final multiplexed and modulated signal, the four channels are coupled into the input ports of two 2×1 optical combiners 14, the two output ports of which are fed to the input ports of a final 2×1 combiner 15, the output of which is delivered to an output coupler 16. The output coupler 16 outputs the multiplexed signal 17, which comprises the four channels combined, in which the relative delays of the channels mean that the pulses of the four channels are interleaved in a repeating sequence.
[0037] In the published report of this known example [1], data rates of 104 Gbaud and 208 Gbaud were reported for OOK and PAM-4 coding respectively. The electronic components, namely the modulators 8, operated at the much lower speed of 26 Gbaud (note this is one quarter of the OOK speed). This corresponds to a symbol period Ts of 9.6 ps. Hence, each spiral waveguide 12 provides this amount of delay, giving overall a 9.6 ps difference between adjacent channels. While this data rate is usefully high, it is also fixed at a given wavelength, according to the length of the spiral waveguides, and cannot be changed within a given system. Also, inevitable fabrication variations between systems intended to be identical will change the intended fixed rate slightly, giving inconsistencies.
[0038] This is problematic in the context of telecommunications, in which IEEE standards strictly define data rates that must be used. There is no tolerance for data rates within a range, since the applicable rate for any system defines a large number of operating parameters such as data-frame rate, clock speed and synchronisation. Accordingly, an OTDM device that does not comply with the standards will not be accepted for use in the telecommunications industry.
[0039] Also, there is an amplitude difference between successive bits in the multiplexed signal generated by the
[0040] Hence, it can be seen that the use of optical delay lines in an OTDM device has associated drawbacks.
[0041]
[0042] In this system, an optical source 20 in the form of a laser is configured to produce a continuous wave optical input 21 for the system. Note the contrast with the pulsed optical input of the
[0043] The
[0044] The present disclosure proposes to address this drawback by taking the total optical power originating from the optical source and dividing it by splitting it into consecutive portions or slices in the time domain, rather than in the power domain. Each slice has the same finite duration, so that all slices are substantially equal in time. For a continuous wave optical power input, a sequence of consecutive and contiguous slices of power with respect to time is hence achieved, where each slice has the same power amplitude, which is, importantly, the same as the power amplitude of the original optical input. Then, the slices can be allocated in a repeating sequence across the desired number of channels, in order to define the required channels, each slice becoming a pulse. Each channel comprises a sequence of pulses of the original power amplitude and having the same repetition rate (according to the equal duration of the slices and the number of channels to which the slices are allocated), but each sequence being shifted in time relative to the other channel sequences since each slice occupies a unique portion of time. The pulses of each channel can be separated out from those of the other channels in order to be utilised as required. For example, to achieve OTDM as described above, the pulses of each channel undergo amplitude modulation to receive the data to be carried by that channel, and the individual pulse sequences are then recombined to provide a multiplexed signal. This is an example of digital to analogue conversion (DAC), where digital data is carried by electrical drive signals for modulators used to perform the amplitude modulation, and hence converted into analogue data represented by the pulse amplitudes.
[0045]
[0046]
[0047] In reality, pulses produced according to the proposed time-slicing scheme will have slightly lower power or intensity than the original continuous wave input, but this is due to unavoidable optical loss inherent in the components used to generate the pulses. Such loss is common to the approaches of
[0048]
[0049] A first arm 43a of the MZM 43 receives an electrical drive signal 44a in the form of a clock signal 45a (that is, a signal comprising an oscillating voltage) with a period Ts, and a phase that we can designate as 0° for the purposes of explanation. The second arm 43b of the MZM 43 receives an electrical drive signal 44b in the form of a clock signal 45a which again has a period Ts, in other words, the same period as the first clock signal 45a. However, the second clock signal 45b is arranged to be in antiphase with the first clock signal 45a, in other words, it has a phase of 180°. A pair of equal and opposite clock signals such as these can be termed differential clock signals. The voltage of the clock signals is set so that the peak-to-peak differential voltage between the two arms, V.sub.ppd, is substantially equal to the half wave voltage (Vπ) of the MZM 43.
[0050] The outputs of the two arms 43a, 43b of the MZM 43 are coupled into the two input ports of a 2×2 MMI device 46. The action of the 2×2 MMI 46 (described further below) is to pass all the light from both input ports to one or other of its output ports depending on the phase of the light in one input port relative to the light in the other input port. Hence, if this relative phase, or the phase difference, between the input ports can be suitably arranged, the total light in both input ports can be alternately switched between the two output ports. Overall, therefore, the total CW power level entering the 1×2 MMI 42, which is split equally between the two arms of the MZM 43, can be recombined on an alternating and equal time basis at its original level between the two 2×2 MMI outputs 46a, 46b.
[0051] Hence, two output signals 47a, 47b are obtained which each comprise a sequence of pulses, corresponding to time slices from the original CW input, and each having the same power as the original CW power. However, the sequences are offset in time from one another (arising from the alternation of power at each output port 46a, 46b); the time during which a pulse is present in one sequence corresponds to zero power (no pulse) in the other sequence. The sequences 47a, 47b are therefore differential, in common with the two clock signals 44a, 44b. Each pulse in each sequence has a duration or pulse width of Ts/2, in other words, half the clock signal period Ts. This distribution of power between the two signals 47a, 47b makes ideal pulse sequences for OTDM; when combined, the pulses of the signals 47a, 47b will neatly interleave in the proposed manner shown in
[0052]
[0053] Hence, the original optical input power can be substantially preserved in the output pulses, maximising the available range for amplitude modulation. Additionally, the proposed arrangement allows flexibility and tunability. If the clock signals for the MZM are generated from a tunable arrangement, their frequency can be altered as desired, which in turn alters the pulse duration of the channel pulses. Hence, bit rate flexibility is available.
[0054] In this regard, limitations may arise between the electrical and optical bandwidths of the MZM, but suitable design of amplifiers for the electrical drive signals and of the modulator electrodes can provide matching over at least a narrow frequency range such as over about 10 GHz (such as 45 GHz to 55 GHz), offering some tunability. Resonant enhancement techniques such as inductor peaking and microwave stubs could be used to implement this.
[0055] In the
[0056]
[0057] In order to extend the apparatus for four channels, each of the two differential pulses signals 47a, 47b is delivered to a further MZM arrangement. The first differential signal 47a is delivered by coupling the first output 46a of the 2×2 MMI 46 to the input of a first further 1×2 MMI 48, which splits the optical power of the signal 47a substantially equally between two arms of a second MZM 50 (MZM2). The two arms of the second MZM 50 are respectively driven by electrical drive signals 51a, 51b. The drive signals are, as before, clock signals 52a, 52b which have the same period Ts as for the first MZM 43. Again, the two clock signals 52a, 52b are differential, in other words, have a phase difference of 180°. However, the phase of each clock signal 52a, 52b is set with reference to the phase of the clock signals 45a, 45b of the first MZM 43, so as be in quadrature phase. Hence, one clock signal 52a for the second MZM 50 has a phase of 90°, and the other clock signal 52b for the second MZM 50 has a phase of 270°.
[0058] The two arms of the second MZM 50 are coupled to the two input ports of a first further 2×2 MMI 53. This operates as before to alternate the total power entering the second MZM 50 between its two outputs 53a, 53b, owing to the differential phase relationship of the clock signals 52a, 52b. Hence, the power of each pulse in the input signal 47a entering the second MZM is divided in half in the time domain, to provide one pulse to the first output 53a and one pulse to the second output 53b, each having a pulse duration of Ts/4, in other words, half the pulse duration Ts/2 of the original input to the second MZM 50. Hence, the result is two pulse sequences 54a, 54b each comprising pulses of equal power to the original CW input power from the optical source 40, of duration Ts/4, and separated by 3 Ts/4 (made up of the Ts/4 duration of the corresponding pulse in the other sequence and the space between pulses Ts/2 in the input pulse sequence 47a). The pulses in the sequence 54b lag the pulses in the sequence 54a by the same duration Ts/4, so are contiguous in time thereto.
[0059] This arrangement is repeated for the second differential signal 47b from the first MZM 43. Hence, the second output 46b of the 2×2 MMI 46 is coupled to the input of a second further 1×2 MMI 49 which splits the optical power of the signal 47b substantially equally between two arms of a third MZM 60 (MZM3). The two arms of the third MZM 60 are respectively driven by electrical drive signals 61a, 61b in the form of clock signals 62a, 62b which match the clock signals 52a, 52b used to drive the second MZM 50. Hence, the clock signals 62a, 62b have the same period Ts, are differential, and respectively at 90° and 270° phase compared to the 0° clock signal 45a used at the first MZM 443. The two arms of the third MZM 60 are coupled to the two input ports of a second further 2×2 MMI 63, which operates as before to alternate the total power entering the third MZM 60 between its two output 63a, 63b, owing to the differential phase relationship of the clock signals 62a, 62b. As before, then, the power of each pulse in the input signal 47b entering the third MZM 60 is divided in half in the time domain, to provide one pulse to the first output 63a and one pulse to the second output 63b, each having a pulse duration of Ts/4 and a power equal to the original CW power. The pulses are separated by 3 Ts/4, in common with the pulses sequences 54a, 54b from the second MZM 50. However, because the pulse sequence 64a, 64b are derived from the second output 46b of the first MZM 43 instead of the first output 46a, their pulses occupy the time duration of the pulses in that second output 46b, and hence, as a pair, are delayed by Ts/2 compared to the corresponding pair of pulses in the pulses sequences 54a, 54b from the second MZM 50 which derive from the first output 46a of the first MZM 43.
[0060] Overall, therefore, the apparatus produces four pulse sequences 54a, 54b, 64a, 64b of pulses identical in power amplitude, duration and repetition rate, and each delayed with respect to the others such that the pulses of each sequence occupy a different portion of time compared to those of three other sequences, with all portions of time being contiguous. The pulses sequences can be described as being in quadrature, arising from the quadrature characteristic of the clock pulses 45a, 45b, 52a, 52b, 62a, 62b used to drive the MZMs 43, 50, 60. They are hence appropriate as channels to be combined together into a single multiplexed signal, since the pulses in each sequence interleave properly and without overlap with those of the other sequences.
[0061]
[0062] Appropriate technology for the generation of quadrature clock signals is available. Chip-level quadrature clock generation is common in modern radio frequency communication systems. In 2014, a quadrature-voltage-controlled-oscillator (QVCO) embedded into an phase-locked-loop (PLL) and operating between 57 and 68 GHz with a 65 nm CMOS process was reported [4]. In 2016, a QVCO operating between 72 and 88 GHz based on a 28 nm CMOS process was reported [5]. In 2019, the frequency range of QVCO has been pushed to 93 to 104 GHz [6]. The effects of possible timing jitter should be taken into account for the scheme proposed herein. The current state-of-art in this area has pushed the root-mean-square (RMS) jitter to less than 0.3% of the clock period. In 2019 a PLL generating 28 to 31 GHz with a RSM jitter at 76 fs using a 65 nm CMOS process was reported [7]. Accordingly, the development of on-chip clock generation functions (implemented as QVCO plus PLL) are adequately mature for the proposed pulse generation techniques both in terms of frequency accuracy and frequency range.
[0063] Following the generation of interleaved optical pulses using methods as described above, data modulation onto the individual channels to effect OTDM can be relatively straightforward, for example by employing conventional optical pulse modulation techniques. Typically, pulse modulation is achieved by passing the train of pulses in a channel through an electro-optic modulator, and driving the modulator electrodes with one or more electrical drive signals carrying the desired data. There is no limitation of the format of modulator that can be used for this, in combination with apparatus configured to generate channels of pulses by slicing optical power in the time domain. For example, further MZMs could be used, or alternatively electro-absorption modulator (EAM) types, or ring modulator types, or metal-oxide-semiconductor capacitor (MOSCAP) types, or carrier depletion types, or carrier injection types, or other electro-optic modulator types known to the skilled person. Similarly, any appropriate material may be used for the modulator, such as silicon, group III-V semiconductors and lithium niobate.
[0064] A particularly useful approach is to use the clock source that is already utilised to generate the clock signals for driving the MZM(s) used in the pulse generation to additionally provide a trigger signal or trigger clock at the same frequency and phase to trigger the data-carrying electric drive signals (data stream) for the modulators for each corresponding pulse sequence or channel. by controlling the timing of the data streams in this way, the modulator drive signals can be interleaved with the same phase as the various pulse sequences so that the drive signals are appropriately matched in time to the pulses in each channel.
[0065] It may be that a small amount of delay mismatch may occur owing to the propagation time (delay) of the pulses from the pulse generation components to the pulse modulators. To prevent the clock pulses at the pulse modulators being a little ahead of the pulses as they arrive for modulation, an on-chip timing control function to introduce a suitable delay (tau) into the clock pulses applied to control the timing of the data streams.
[0066]
[0067] The photonics chip 74 has an input port to which a CW optical signal 41 is supplied from an optical source (not shown). A pulse generator 76, configured as described with respect to
[0068] The two modulated pulse sequences 47a′, 47b′ are delivered via waveguides to the input ports of a 2×1 MMI 80, which combines the two modulated pulse sequences 47a′, 47b′ into a multiplexed signal 82 (amplitude modulation not shown) which comprising the pulses of the first modulated pulse sequence 47a′ interleaved with the pulses of the second modulated pulse sequence 47b′, as previously described. The multiplexed signal is delivered to an output 84 of the photonics chip 74.
[0069] The electronics chip 72 comprises an on-chip clock generator 90 comprising a phase locked loop (although other clock signal generator formats may be used if preferred), and a clock signal amplifier if necessary to achieve a suitable power level for the clock signals. Under the action of external control signals 92, the nature of which will be apparent to the skilled person, the clock generator 90 operates to generate a pair of differential clock signals (phase designated as 0° and 180° as before). The clock operates at a frequency Fs, to provide clock pulses with a period of Ts=1/Fs. The differential clock signals are provided to the photonics chip as the drive signals 45a, 45b for the MZM 43 in the pulse generator 76. Accordingly, the generated pulse sequences have a pulse duration of Ts/2, as previously described.
[0070] Copies of the differential clock signals at Ts and 0°/180° are also used to trigger the modulation applied to the pulse sequences 47a, 47b by the modulators 78a, 78b. To effect this, the electronics chip also comprises a first driver module 94a, preferably co-designed for operation with the first modulator 78a, and a second driver module 94b, preferably co-designed for operation with second modulator 78b. The driver modules 94a, 94b are configured to provide electric drive signals to the modulators 78a, 78b on the photonics chip 74 The first driver module 94a receives an external first data stream 96a, comprising data to be modulated onto the first pulse sequence or channel 47a. The modulation can utilise any known data modulation scheme, for example OOK or PAM-4. The first driver module formulates the first data stream 96a into appropriate electric drive signals 98a to drive electrodes in the first modulator 78a, and delivers these drive signals to the first modulator 78a on the photonics chip 74. Additionally, the first driver module 94a receives a copy 100a of the differential clock signal at 0° phase, which is responsible for the positions in time of the pulses in the first pulse sequence 47a, and this is used to trigger the electrical drive signals 98a for the first modulator 78a, in order that the modulation is synchronised with the timing of the pulse sequence. In order to adjust for any optical delay in the arrival of the pulses at the first modulator 78a, a variable electrical delay line 102a is provided in the supply of the clock signal 100a to the first driver module 94a. Similarly, the second driver module 94b receives an external second data stream 96b, comprising data to be modulated onto the second pulse sequence or channel 47b. The second driver module formulates the second data stream 96b into appropriate electrical drive signals 98b for the electrodes in the second modulator 78b, and delivers these to the second modulator 78b. Additionally, a copy 100b of the differential clock signal at 180° phase is provided to the second driver module 94b to trigger the drive signals 98b for the second modulator 78b, to ensure synchronicity with the timing of the second pulse sequence 47b. A second variable electrical delay line 102b can be provided to compensate for any optical delay experienced by the second pulse sequence in arriving at the second modulator 78b.
[0071] The electrical chip 72 can be three-dimensionally integrated with the photonics chip 74, in order to provide a compact and efficient OTDM device. Monolithic integration may also be used, in which the electrical components shown as being on the electrical chip 72 are monolithically fabricated with the photonics components shown as being on the photonics chip 74.
[0072]
[0073] The electrical chip 112 is configured as the electrical chip 72 in the example device of
[0074] Devices such as those in
[0075]
[0076] The presently proposed pulse generation scheme readily enables integrated device configurations such as those shown in
[0077] An example of this is a device configured to implement the known PAM-N data modulation scheme. An existing technique for this uses a continuous optical wave as an input to an electro-optic modulator. The electrodes providing modulation in the two arms of the modulator have a segmented design, comprising a series of electrode segments arranged in sequence along the length of the arms. The electrode segments are driven with signals carrying different binary inputs, as binary pulses, to be modulated onto the optical input. In order for each segment to modulate the correct part of the optical input, it is necessary to apply individual timing control functions to the drive signals for each segment, to delay the drive signals and match them to the arrival time of the optical input at that segment following its propagation delay from travelling along the modulator arm through the series of segments.
[0078] The presently proposed approach can allow the timing control to be dispensed with. A narrow optical pulse can be generated within a pulse sequence, as described above, and used as an input to the segmented modulator in place of the continuous wave input currently employed. The optical pulse will have a propagation time (delay) to travel through the modulator, passing the series of electrode segments. If the binary drive signals for the electrode segments are configured to have a pulse width which is greater than the propagation delay of the optical pulse, the optical pulse will coincide with the drive pulses of every electrode segment without any need for timing control. Hence, there is no need to match the optical and electrical delays so problems associated with delay matching are removed, and timing control functions for the drive signals can be eliminated from the device. Additionally, the wider pulse width of the electrical signals corresponds to a lower speed (frequency) for the electrical signals, which is a simpler design specification for both the driver modules and the modulator, which can be co-designed to operate at the lower speed.
[0079]
[0080]
[0081] The example modulators of
[0082] The pulse modulation is operated as optical sampling of the analogue input. In existing photonic (optically-based) analogue to digital converters (ADC), sampling in the optical domain by using optical pulse trains is used to overcome aperture jitter in electrical sampling ADC schemes; this is considered generally advantageous. Typically, such systems are based on discrete components. In contrast, arrangements proposed herein offer chip-level ADC products able to operate with an accumulated sampling rate in excess of 100 GB/s, combined with the benefit of frequency tunability discussed above with regard to the OTDM systems.
[0083]
[0084] Central to the system 200 is a quadrature optical pulse generator 206, configured in line with the
[0085] In order to effect conversion of the optical analogue samples into the digital domain, each pulse sequence 54a, 54b, 64a, 64b is delivered to a corresponding photodetector 214 (such as a photodiode) on the photonics chip. These detect the optical power of the pulse sequences 54a, 54b, 64a, 64b and output correspond electrical signals 215a-215d. Each electrical signal 215a-215d is routed to a corresponding electrical amplifier, such as a transimpedance amplifier 216a-216d, the outputs of which, being amplified versions of the electric signals 215a-215d are delivered to corresponding electrical analogue-to-digital converters (ADC) 217a-217d also on the electrical chip 202. The ADCs 217a-217d operate in the conventional manner to convert the input electrical signals 215a-215d, being analogue signals representing each optical pulse sequence 54a, 54b, 64a, 64b, into electrical binary signal outputs. Each binary output is passed to a single digital signal processor 218, which may also comprises memory for storage of the binary signals. The processor 218 is configured to perform any signal processing deemed necessary for the binary signals, and provide the result as a series of electrical digital binary outputs 219, being the final digital output of the system 200. In order to ensure that the operation of the ADCs 217a, 217d is properly synchronised with the relative timings of each pulse sequence 54a, 54b, 64a, 64b the ADCs are triggered with clock signals 100 from the clock generator 90 matching the quadrature clock signals 45a, 45b, 52a, 52b used to drive the pulse generator MZMs 43, 50, 60, optionally passed through variable electrical delay lines 102 to compensate for optical propagation delays on the photonics chip 204. This is analogous to the timing control used to trigger the OTDM modulators 78 in the
[0086]
[0087] The output from the modulators 254 are therefore four channels of time interleaved quadrature optical pulse sequences 54a′, 54b′, 64a′, 64b′, modulated to carry the electrical analogue inputs 258. The conversion to digital signals is carried out in the same manner as in the
[0088] As will be appreciated from a comparison of
[0089] Various experimental work has been carried out to demonstrate the practicality of the disclosed pulse generation technique and associated modulation methods. The production, in terms of fabrication and packaging, of commercially suitable optoelectronic devices and systems will require significant development work, but nevertheless it is possible to demonstrate the disclosed concepts with real devices. Therefore, a previously fabricated silicon modulator array on a chip has been used a core module component for proof of principle demonstrations. This silicon modulator chip, in which four individual MZMs are fabricated as an array, was wire-bonded onto a printed circuitry board (PCB). External electrical clocks and data streams were routed to the modulators via radio frequency (RF) tracks (grounded coplanar waveguide) on the PCB. RF losses in the PCB and parasitic effects introduced by the device packaging limited the modulators to operation up to a few Gb/s, which is nevertheless useful to allow proof of concept.
[0090] Three demonstrations were made: generation of differential optical pulses (corresponding to
[0091]
[0092]
[0093]
[0094] Consequently, the principle described with respect to
[0095] This experimental work was based on general discrete component at hand, for the purpose of proof of concept only. Neither the operation speed nor the signal integrity demonstrated correspond to those of modern optical communication links, but the demonstrated devices can be readily scaled and enhanced to provide performance up to and beyond current communications link operating parameters. As noted, devices to implement the described methods and techniques can fabricated by monolithic integration of electrical components into silicon photonics platforms or via three-dimensional packaging of optoelectronic systems.
[0096] Optical pulse generation in accordance with the method proposed herein can be understood with reference to the flow chart shown in
[0097] A variety of apparatus configurations for generating optical pulses of this form have been described herein, together with additional features for enabling applications such as digital to analogue conversion, analogue to digital conversion and optical time domain multiplexing. However, it is envisaged that other configurations of apparatus, comprising various photonic and electrical components and devices, may alternatively be used to generate pulses in accordance with a method as set out in
[0098] For example, the various pulse generators described herein in detail comprise Mach Zehnder modulators (MZMs). Other electro-optic modulators that achieve the same results as MZMs are known, and may be used instead as preferred. The various components may be differently distributed between one or more chips to produce a complete device, with individual chips integrated together in any known manner considered practical and convenient. While devices in a chip-based format are compact, robust and convenient, a device or apparatus configured to achieve the proposed pulse generation could be implemented to include one or more bulk optical or electrical components.
[0099] The example OTDM transmitters described above with regard to
[0100] However, the transmitters are not limited in this regard. A particular benefit of the approach described herein is that different modulation techniques can be applied to different channels generated in the same OTDM device, and/or different data types can be modulated onto the different channels, without any impact on the ability to multiplex the channels and transmit the final output signal. All that is required are appropriate drive signals that can carry the desired data streams, and suitable modulators or signal processing units able to imprint or encode that data onto the optical pulses. In particular, it is possible to modulate individual channels in the same transmitter simultaneously with either digital signals or analogue signals. This is a highly beneficial flexibility enabled by the use of optical signals to carry the data. Similar electrical multiplexing systems, such as electrical serialisers/deserialisers (SERDES) are typically built from semiconductor logic gates (complementary metal-oxide-semiconductors (CMOS), for example) and are hence only able to handle binary information and are therefore limited to digital applications. Devices according to the present disclosure are not limited in this way, and both digital data and analogue data can be encoded onto the optical pulse sequences by use of suitable modulators. For example, the pulses of one channel can be modulated with a binary signal, pulses in another channel can be modulated with an analogue signal such as a radio frequency signal, and pulses in yet further channels can be modulated according to other modulation schemes such as pulse-amplitude modulation (PAM) or quadrature amplitude modulation (QAM). Once individually modulated, the channels can be multiplexed and later demultiplexed free from interference with one another (channel cross-talk). This capability to handle different signal types and formats has the potential to greatly enhance and improve computing architecture; allowing the efficient routing of many signals, with reduced requirements for analogue-to-digital conversion and digital-to-analogue conversion. This is merely one example application, however, and the invention is not limited in this regard.
[0101] An OTDM device as proposed herein can be thought of an optical serialiser (the serialising or multiplexing side of a SERDES system), and offers several advantages over conventional logic-gate based electrical serialisers. An electrical device typically suffers from latency induced by latch-up in the CMOS components; an optical system eliminates this. Higher throughput can be achieved in an optical arrangement compared with an electrical arrangement. The optical signals are immune to electromagnetic interference. Also, the use of optical signals gives compatibility with optical wavelength division multiplexing schemes.
[0102] To fully implement SERDES or other schemes that transmit, convey or propagate the multiplexed signal, demultiplexing or deserialisation is required, wherein the multiplexed signal is received and demultiplexed or deserialised back into its individual component channels so that the data carried by the optical pulses in each channel can be extracted and utilised, or the pulses of any channel can be separately further conveyed elsewhere.
[0103]
[0104] The components may be variously fabricated on one or more chips depending on the application. For example, if the multiplexed signal is to be propagated a significantly greater distance than typical chip dimensions, or propagated for a distance unknown in advance, the optical pulse generator component 302 and the multiplexing component 304 may be formed on a first chip 310, and the demultiplexing component 308 may be formed on a separate, second chip 312. This gives flexibility in locating the multiplexing and the demultiplexing functionality of the system 300. The routing component 306 can be fabricated as required according to the type and distance of propagation, and optically coupled to the first chip 310 and the second chip 312. In another example, all the components may be fabricated on single chip 314 in order to provide a monolithic optical SERDES system.
[0105]
[0106] For demultiplexing, a similar arrangement is employed to that used to generate the multiple channels of pulses from the original CW optical input, with the multiplexed signal 84 being treated as the CW input. Compare
[0107] An optical SERDES or multiplex/demultiplex system in line with the examples herein offers a variety of possible functionalities and benefits. It is attractive for use in computing architecture, for example. In conventional electronics-based computing architecture, data is transmitted and processed in the form of binary logic bits represented by 0 and 1; data is limited to this format. In a photonics-based system, on the other hand, data is transmitted and processed in the form of optical pulses, which can carry complex degrees of freedom, thereby removing restrictions created by binary bits. However, the devices described herein are additionally compatible with traditional binary signals (which are merely one of many data formats that can be carried by optical pulses), offering a smooth transition between electrical and optical devices and systems. While generally useful, this is attractive for current fields of interest such as analogue computing, optical machine learning and artificial intelligence.
[0108] The various embodiments described herein are presented only to assist in understanding and teaching the claimed features. These embodiments are provided as a representative sample of embodiments only, and are not exhaustive and/or exclusive. It is to be understood that advantages, embodiments, examples, functions, features, structures, and/or other aspects described herein are not to be considered limitations on the scope of the invention as defined by the claims or limitations on equivalents to the claims, and that other embodiments may be utilised and modifications may be made without departing from the scope of the claimed invention. Various embodiments of the invention may suitably comprise, consist of, or consist essentially of, appropriate combinations of the disclosed elements, components, features, parts, steps, means, etc., other than those specifically described herein. In addition, this disclosure may include other inventions not presently claimed, but which may be claimed in the future.
REFERENCES
[0109] [1] J Verbist et al, “4:1 silicon photonic serializer for data center interconnects demonstrating 104 Gbaud OOK and PAM4 transmission”, Journal of Lightwave Technology, vol. 37, pp 1498-1503, 2019 [0110] [2] J Meier and T Schneider, “Precise, High-bandwidth digital-to-analog conversion by optical sinc-pulse sequences”, 2019 12.sup.th German Microwave Conference (GEMiC), March 2019 [0111] [3] MA Soto et al, “Generation of Nyquist sinc pulses using intensity modulators”, Conference on Lasers and Electro-optics, 2015 [0112] [4] X. Yi, C. C. Boon, H. Liu, J. F. Lin, and W. M. Lim, “A 57.9-to-68.3 GHz 24.6 mW Frequency Synthesizer With In-Phase Injection-Coupled QVCO in 65 nm CMOS Technology”, IEEE Journal of Solid-State Circuits, vol. 49, no. 2, pp. 347-359, February 2014. [0113] [5] M. Vigilante, and P. Reynaert, “Analysis and Design of an E-Band Transformer-Coupled Low-Noise Quadrature VCO in 28-nm CMOS”, IEEE Transactions on Microwave Theory and Techniques, vol. 64, no. 4, pp. 1122-1132, April 2016. [0114] [6] X. Yi, “A 93.4-104.8-GHz 57-mW Fractional-N Cascaded PLL With True In-Phase Injection-Coupled QVCO in 65-nm CMOS Technology”, IEEE Transactions on Microwave Theory and Techniques, vol. 67, no. 6, pp. 2370-2381, June 2019. [0115] [7] J. Kim, H. Yoon, Y. Lim, Y. Lee, Y. Cho, T. Seong, and J. Choi, “A 76 fs(rms) Jitter and-40 dBc Integrated-Phase-Noise 28-to-31 GHz Frequency Synthesizer Based on Digital Sub-Sampling PLL Using Optimally Spaced Voltage Comparators and Background Loop-Gain Optimization”, IEEE International Solid State Circuit Conference 2019, p. 258