PULSE GENERATING CIRCUIT, AND ELECTROSURGICAL GENERATOR INCORPORATING THE SAME

Abstract

The present invention relates to a pulse generating circuit for an electrosurgical generator, for generating a waveform suitable for causing electroporation of biological tissue. The pulse generating circuit comprises a voltage source connectable to a load via a switching element, and an open circuit coaxial transmission line connected between the switching element and the voltage source to be charged by the voltage source when the switching element is in an OFF state and to be discharged when the switching element is in an ON state. The switching element comprises a plurality of series connected avalanche transistors, and a trigger pulse generator configured to generate a trigger pulse to activate the plurality of series connected avalanche transistors. Furthermore, the impedance of the coaxial transmission line is configured to match a sum of (i) the impedance the plurality of series connected avalanche transistors, and (ii) the impedance of the load.

Claims

1. A pulse generating circuit for an electrosurgical generator, the pulse generating circuit comprising: a voltage source connectable to a load via a switching element; an open circuit coaxial transmission line connected between the switching element and the voltage source to be charged by the voltage source when the switching element is in an OFF state and to be discharged when the switching element is in an ON state, wherein the switching element comprises: a plurality of series connected avalanche transistors; and a trigger pulse generator configured to generate a trigger pulse to activate the plurality of series connected avalanche transistors, wherein the impedance of the coaxial transmission line is configured to match a sum of (i) the impedance of the plurality of series connected avalanche transistors, and (ii) the impedance of the load.

2. A pulse generating circuit according to claim 1, wherein the coaxial transmission line has a length selected to provide a line delay equal to or less than 5 ns.

3. A pulse generating circuit according to claim 1, wherein the coaxial transmission line is charged by the voltage source through a resistor.

4. A pulse generating circuit according to claim 1, wherein the trigger pulse generator comprises a TTL device.

5. A pulse generating circuit according to claim 1, wherein the trigger pulse has a voltage less than the emitter-base breakdown voltage of each of the plurality of avalanche transistors.

6. A pulse generating circuit according to claim 1, wherein the trigger pulse generator is connected to the plurality of series connected avalanche transistors via a transformer.

7. A pulse generating circuit according to claim 1, wherein the trigger pulse is applied between the collector and emitter of a first transistor of the plurality of series connected avalanche transistors.

8. A pulse generating circuit according to claim 7, wherein the first transistor is furthest from the coaxial transmission line.

9. A pulse generating circuit according to claim 1, wherein a diode is connected in parallel with each of the plurality of series connected avalanche transistors to clamp the voltage across each transistor to less than its collector-base breakdown voltage.

10. A pulse generating circuit according to claim 1, wherein each transistor in the plurality of series connected avalanche transistors is identical.

11. A pulse generating circuit according to claim 1, wherein the load is an electrosurgical instrument.

12. An electrosurgical generator having a pulse generating circuit according to claim 1.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Embodiments of the invention are discussed below with reference to the accompanying drawings, in which:

[0020] FIG. 1 is a schematic diameter that illustrates the principle of a discharge line generator with an ideal switch;

[0021] FIG. 2A is a graph showing a voltage waveform at (i) the transmission line, and (ii) the load in FIG. 1;

[0022] FIG. 3A is a schematic diagram representing the open circuit transmission line of FIG. 1 in a DC model;

[0023] FIG. 3B is a schematic diagram representing the open circuit transmission line of FIG. 1 in a transmission line model;

[0024] FIG. 4 is a schematic diagram of showing the open circuit transmission line of FIG. 1 with an avalanche transistor to generate an ultrashort electric field pulse;

[0025] FIG. 5 is a diagram of a simulated LTSpice circuit of a monopolar ultrashort electric field pulse generator;

[0026] FIG. 6 is a graph showing pulses of various durations generated from the LTSpice circuit of FIG. 5; and

[0027] FIG. 7 is a monopolar pulse observed with a matched 35Ω load, from circuit in FIG. 5.

DETAILED DESCRIPTION, FURTHER OPTIONS AND PREFERENCES

[0028] Generation of ultra-short pulses is possible by using an open circuit coaxial transmission line as a high-Q storage element consisting of distributed series of inductors and shunt capacitors with minimal resistance and shunt conductance. Discharging an open ended delay line via a fast switching element provides a means of producing a ‘flat-top’ rectangular pulse with steep fall times of less than 2 ns in a simple and affordable manner. The co-axial transmission line with a characteristic impedance Z.sub.0 a length of l and a dielectric constant ε.sub.r is charged to a voltage level V.sub.cc, through a high impedance resistor R.sub.c. The line will have and associated delay time T given by the following equation:

[00001] $T = \frac{l \sqrt{ε_{r}}}{c}$

[0029] where c is the speed of light (2.99×10.sup.8 m/s).

[0030] It follows from this that the pulse duration associated with the transmission line is:

[00002] $2 T = 2 \frac{l \sqrt{ε_{r}}}{c}$

[0031] An ultrashort electric field pulse can be generated on a load, R.sub.L, by discharging the transmission line through R.sub.L by closing a switching element. The switching element determines the rise time of the ultrashort electric field pulse whilst the transmission line determines the pulse duration (or width) and the fall time.

[0032] As explained above, the duration of the pulse at the load will be twice the associated delay time of the transmission line.

[0033] FIG. 1 illustrates the principle of an open circuit transmission line technique with an ideal switch as the switching element.

[0034] FIG. 2 shows the voltage waveforms obtained from the system of FIG. 1 at (i) the transmission line Z.sub.0 and (ii) load R.sub.L.

[0035] The relationship between the characteristic impedance of the transmission line Z.sub.0 and the load R.sub.L is integral to the performance of an open circuit coaxial transmission line technique in two ways, which can be understood by modelling the configuration using direct circuit (DC) theory and transmission line theory.

[0036] In DC theory, the relationship between A.sub.0 and R.sub.L imitates a potential divider, as shown in FIG. 3A. Their relationship determines the pulse amplitude at the load V.sub.L:

[00003] $V_{L} = (\frac{R_{L}}{R_{L} + Z_{0}}) V_{cc}$

[0037] If the impedance Z.sub.0 is the same as R.sub.L, the maximum amplitude of the pulse at the load, V.sub.Lmax, will be half the voltage the to which the transmission line is charged:

[00004] $\begin{matrix} if R_{L} = Z_{0}, & V_{L \max} \end{matrix} = \frac{V_{cc}}{2}$

[0038] Using a transmission line model, the system can be represented as shown in FIG. 3B. In this model, the relationship between Z.sub.0 and R.sub.L determines the reflection coefficient, and therefore the pulse shape at the load. If R.sub.L is the same as Z.sub.0, the reflection coefficient will be zero and no secondary pulse or reflection of the primary pulse will be seen at the load:

[00005] $\begin{matrix} Γ = (\frac{R_{L} - Z_{0}}{R_{L} + Z_{0}}) & ∴ \end{matrix} if R_{L} = Z_{0}, Γ = 0$

[0039] Thus, the relationship of Z.sub.0 and R.sub.L determine two key aspects of the pulse at a load: (i) the pulse amplitude, and (ii) pulse shape (caused by any reflection). It follows from the analysis above, that the best pulse shape and parameters, the characteristic impedance of the transmission line Z.sub.0 and the load R.sub.L should match.

[0040] Other features of the pulse are controlled by other parameters of the circuit. For example, the pulse risetime is determined by the behavioural of the switching element, whilst the pulse width is determined by the length of the transmission line, as discussed above.

[0041] This switching element in embodiments of the invention is preferably provided by a stacked array of avalanche transistors. An avalanche transistor is known to provide reliable and repeatable high-speed switching of high voltages with rise times as low as 300 ps, which can be achieved in practice if microwave component layout techniques are considered when the circuit are implemented. Avalanche transistors utilize the negative-resistance characteristics region of bipolar junction transistors, which result from operation in the common-emitter breakdown region. The avalanche region lies between collector emitter (V.sub.CEO) and collector base (V.sub.CBO) voltage when the base current I.sub.B=0 A and emitter current I.sub.E=0 A.

[0042] FIG. 4 is a schematic diagram of a pulse generating circuit 100 that utilises an open circuit transmission line technique in combination with an avalanche transistor as a fast switching element. The circuit function is based on the discharge of the open-circuit transmission line across an avalanche transistor into a load R.sub.L.

[0043] A single avalanche transistor circuit can be configured to have a bi-stable operation, where the maximum pulse amplitude at the output is limited to half the value of the transistor's collector-emitter breakdown voltage, BV.sub.CES, if Z.sub.0=R.sub.L. A supply voltage V.sub.cc above the transistor's BV.sub.CES would permanently breakdown and damage the avalanche transistors as a switching element.

[0044] Initially, energy is stored in a co-axial transmission line via a small current flow in loop 1. A positive trigger on the base of the transistor will suddenly switch the transistor ‘on’. The energy stored in the transmission line will simultaneously be released as a high current along loop 2, producing a pulse on R.sub.L. The width of the trigger on the base is longer than 2T, i.e. the required pulse width at the load.

[0045] FIG. 5 shows a pulse generation circuit 200 that is an embodiment of the invention. The pulse generation circuit 200 is similar to the circuit shown in FIG. 4, except that in place of the single avalanche transistor, there is a plurality (five in this example) of series-connected avalanche transistors. The plurality of series-connected avalanche transistors effectively operate in combination as a single avalanche transistor. This means that the discharge of the open-circuit transmission line is across the stacked transistors to the load, thereby resulting in a cascade effect that causes a proportionally higher pulse amplitude at the load. In this example, each of the avalanche transistors is identical so that the supply voltage V.sub.cc is equally distributed across each of the avalanche transistor in the series chain.

[0046] In this arrangement, the maximum pulse amplitude that can be generated is dependent on the number of stacked avalanche transistor n. The number of avalanche transistors required to generate a specific pulse amplitude V.sub.L can be expressed as

[00006] $V_{L} = {nBV}_{CBO} (\frac{R_{L}}{R_{L} + Z_{0}})$

[0047] where BV.sub.CBO is the collector-base breakdown voltage of each avalanche transistor. If R.sub.L=Z.sub.0, a maximum pulse amplitude V.sub.Lmax can thus be expressed as

[00007] $V_{L \max} = \frac{n B V_{CBO}}{2}$

[0048] In the pulse generating circuit 200 five FMMT417 avalanche transistor are stacked. Each transistor has an collector-emitter breakdown voltage BV.sub.CEO of 100 V and a collector-base breakdown voltage BV.sub.CBO of 320 V. The circuit shown in FIG. 5 was simulated using LTSpice models. The Spice model of the FMMT417 was directly taken from the manufacture's website. The source resistance R.sub.c is 1 MΩ, characteristic impedance of the transmission line Z.sub.0 is 50Ω, source voltage V.sub.cc is 1.5 kV.

[0049] The circuit may include a diode (not shown) connected in parallel with each transistor to clamp the voltage to ensure that the voltage across each transistor does not exceed its collector-base breakdown voltage. Doing so can increase the lifespan of the transistors and ensure that triggering occurs by the trigger signal.

[0050] The trigger signal may be provided by any suitable source. Preferably the trigger signal is generated by a TTL source or a microcontroller. In this example, the trigger signal comprises a pulse having a duration of 600 ns and a 5 V amplitude and pulse period (period of repetition) of 20 ms. It is advantageous to have a 5 V trigger signal because it is less than the emitter-base breakdown voltage of the transistors.

[0051] The pulse width of trigger signal is arranged to be longer than the pulse desired to be generated from the transmission line. The duration of 600 ns was chosen in this case to provide a safe margin to allow the whole transmission line to discharge.

[0052] The trigger signal repetition rate (pulse period) is limited by the time it takes for the open-circuit charged transmission line to charge up again to full capacity.

[0053] A transformer is disposed between the trigger signal generator and the base and emitter of the first transistor in the stack (i.e. the transistor furthest from the transmission line). This configuration means that the trigger pulse is floating, and therefore should be the same between the base and emitter of the first transistor no matter the voltage through the transistor and onto the load. As a result, the amplitude of the pulse at the load ought to increase linearly with the number of transistors in the stack. The transformer may be a 1-EMR-046 Gate Drive Transformer having a 1:1 winding ratio and high voltage isolation.

[0054] In use, the five stacked avalanche transistors are initially in their off-state, with each transistor having 300 V across them (i.e. V.sub.cc/n). When a positive trigger signal is applied to the base of the first transistor Q1, Q1 is turned ‘on’ and places its collector voltage near ground potential. This results in the second transistor Q2 having twice the collector-emitter voltage, thus creating the desired condition in terms of overvolting and therefore causes a non-destructive avalanching of Q2 and places its collector near ground potential. This creates a sequential ‘knock-on’ effect on the next transistor in the chain resulting in the overvolting of the first avalanche transistors, Q1, to the final avalanche transistors, Q5 near the charged open circuit transmission line. When Q5 is turned ‘on’, a fast rise time is produced at the load (<2 ns), therefore allowing the charged open circuit transmission line to discharge through the load producing a pulse with a width of 2T and a maximum amplitude of V.sub.cc/2, if R.sub.L=Z.sub.0.

[0055] The pulse generating circuit 200 may thus be used to generate monopolar ultrashort electric field pulses.

[0056] Although not shown in FIG. 5, the pulse generating circuit 200 may further comprise a capacitor connected in parallel with the high impedance resistor R.sub.c. This acts as a current reservoir to enable high current to be provided for a short period of time without causes a significant voltage drop. For example, if it is desired to produce a pulse having a 1 kV peak voltage, the driving current I.sub.d required can be calculated as

[00008] $I_{d} = C \frac{d V}{dt},$

where C is the load capacitance (i.e. the combined capacitance of the coaxial transmission line and R.sub.L), and

[00009] $\frac{d V}{d t}$

is the desired change in voltage over the pulse rise time. The driving current I.sub.d may be 1500 A or more, e.g. 2000 A. The reservoir capacitor prevents the voltage of the pulse from dropping significantly through the duration of the pulse. The capacitance value C.sub.res of the reservoir capacitor can be calculated by considering an acceptable drop in voltage

[00010] $\frac{d V}{d t}$

(say 1 V over a 10 ns pulse) for the driving current I.sub.d. The capacitance value C.sub.res may be 1.5 to 2.5 μF, for example.

[0057] FIG. 6 is a graph showing voltage pulses obtained for a range of transmission line lengths. In FIG. 6, the transmission line lengths are characterised by the line delay T. The graph demonstrate that the transmission line length determines the pulse width of 2T, i.e. transmission lines having line delays of 5 ns, 25 ns, 50 ns and 100 ns produce pulse widths of 10 ns, 50 ns, 100 ns and 200 ns respectively. Additionally, the rise times of all four pulses are the same and less than 2 ns, which emphasises that the switching element, i.e. the five avalanche transistors, determines this factor.

[0058] The graph in FIG. 6 suggests that a 50Ω load does not match the transmission line characteristic impedance because secondary pulse of lower amplitude to the primary pulse is seen on each signal. This suggested an unmatched load due to reflection, i.e. Γ≠0. The inventors have realised that it is necessary to compensate for the impedance of the transistors in order to optimise the pulse generation circuit. In the example shown in FIG. 5, each individual transistor has an impedance of −3Ω. Therefore, a total of ˜15Ω is across the transistor stack. The reflection coefficient can thus be expressed as

[00011] $Γ = (\frac{R_{Σ} - Z_{0}}{R_{Σ} + Z_{0}}) = (\frac{(R_{L} + n R_{A}) - Z_{0}}{(R_{L} + n R_{A}) + Z_{0}})$

[0059] wherein the R.sub.Σ is the total impedance of the circuit, and R.sub.A is the impedance of a signal avalanche transistor.

[0060] This explains the reflection observed in the pulses shown in FIG. 6, as Γ=0.13, and the amplitude of the reflection pulse is ˜13% of the primary pulse (R.sub.L=50Ω, nR.sub.A=(3Ω×5)=15Ω and Z.sub.0=50Ω). The additional impedance of nR.sub.A also affects the DC component of the design, which can be rewritten as:

[00012] $V_{L} = (\frac{R_{L}}{Z_{0} + R_{A} + R_{L}}) V_{cc}$

[0061] Taking this into account, the impedance of the load R.sub.L was adjusted to 35Ω. This resulted in a single monopolar pulse at the load with zero reflection and no secondary pulse, as shown in FIG. 7.

REFERENCES

[0062] [1] W. Meiling and F. Stary, Nanosecond pulse techniques. New York: Gordon and Breach, 1970, p. 304. [0063] [2] Q. Yang, X. Zhou, Q.-g. Wang and M. Zhao, “Comparative analysis on the fast rising edge pulse source with two kinds of avalanche transistor,” in Cross Strait Quad-Regional Radio Science and Wireless Technology Conference, Chengdu, 2013. [0064] [3] G. Yong-sheng et al., “High-speed, high-voltage pulse generation using avalanche transistor,” Review of Scientific Instruments, vol. 87, no. 5, p. 054708, 2016.

PULSE GENERATING CIRCUIT, AND ELECTROSURGICAL GENERATOR INCORPORATING THE SAME

Inventors

Cpc classification

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H03K3/335

ELECTRICITY

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A61B2018/1286

HUMAN NECESSITIES

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A61B2018/00755

HUMAN NECESSITIES

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A61B2017/00154

HUMAN NECESSITIES

Classification Explorer

A61B2018/00708

HUMAN NECESSITIES

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A61B18/1206

HUMAN NECESSITIES

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H03K3/53

ELECTRICITY

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A61B2018/126

HUMAN NECESSITIES

International classification

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A61B18/12

HUMAN NECESSITIES

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H03K3/335

ELECTRICITY

Abstract

Claims

Description