Half-bridge driver circuit, related integrated circuit and system

Abstract

A half-bridge driver circuit is configured to generate drive signals based on control signals. A processing circuit is configured to generate high side and low side control signals based on a control signal. An edge detector is configured to generate first and second signals in response to rising and falling edges in the control signal. A state machine transitions between states in response to the first and second signals, and is configured to sequentially, in response to the first signal, set the high side and low side control signals low; in response to the second signal, set the high side control signal high and the low side control signal low; in response to the first signal, set the high side and low side control signals low; and in response to the second signal, set the high side control signal low and the low side control signal high.

Claims

1. A half-bridge driver circuit comprising: a high side output terminal configured to provide a high side drive signal for a high side switch; a low side output terminal configured to provide a low side drive signal for a low side switch; a high side driver circuit configured to generate the high side drive signal as a function of a high side control signal; a low side driver circuit configured to generate the low side drive signal as a function of a low side control signal; an input terminal configured to receive a control signal; an edge detector configured to generate a first signal in response to a first type of edge in the control signal, and a second signal in response to a second type of edge in the control signal, the second type of edge being opposed to the first type of edge; and a state machine comprising a plurality of states, wherein transition between the states occurs in response to the first signal and the second signal, and wherein the state machine is configured to sequentially: in response to the first signal, set the high side control signal and the low side control signal to a first logic level, in response to the second signal, set the high side control signal to a second logic level and the low side control signal to the first logic level, in response to the first signal, set the high side control signal and the low side control signal to the first logic level, and in response to the second signal, set the high side control signal to the first logic level and the low side control signal to the second logic level.

2. The half-bridge driver circuit of claim 1, wherein the control signal is a periodic signal comprising first and second pulses for each switching cycle, wherein the high side control signal and the low side control signal are generated as PWM signals, wherein the low side control signal corresponds to an inverted version of the high side control signal with a first delay between a falling edge of the low side control signal and a following rising edge of the high side control signal and with a second delay between a falling edge of the high side control signal and a following rising edge of the low side control signal.

3. The half-bridge driver circuit of claim 2, wherein the first type of edge is a rising edge and the second type of edge is a falling edge, wherein a duration of the first delay corresponds to a duration of the first pulse of the control signal and a duration of the second delay corresponds to a duration of the second pulse of the control signal.

4. The half-bridge driver circuit of claim 1, wherein the first logic level is low and the second logic level is high.

5. The half-bridge driver circuit of claim 1, wherein the state machine comprises: a first state in which the high side control signal and the low side control signal are set to the first logic level; a second state in which the high side control signal is set to the second logic level and the low side control signal is set to the first logic level; a third state in which the high side control signal and the low side control signal are set to the first logic level; and a fourth state in which the high side control signal is set to the first logic level and the low side control signal is set to the second logic level.

6. The half-bridge driver circuit of claim 5, wherein the state machine is configured to: proceed from the first state to the second state in response to the second signal; proceed from the second state to the third state in response to the first signal; proceed from the third state to the fourth state in response to the second signal; and proceed from the fourth state to the first state in response to the first signal.

7. The half-bridge driver circuit of claim 5, wherein the state machine is configured to proceed to one of the first, second, third, or fourth states in response to a reset signal.

8. The half-bridge driver circuit of claim 7, wherein the state machine is configured to proceed to the fourth state in response to a reset signal.

9. The half-bridge driver circuit of claim 7, further comprising a further input terminal configured to receive the reset signal.

10. The half-bridge driver circuit of claim 1, wherein the state machine comprises: a first state in which the high side control signal and the low side control signal are set to the first logic level; a second state in which the high side control signal is set to the second logic level and the low side control signal is set to the first logic level; and a third state in which the high side control signal is set to the first logic level and the low side control signal is set to the second logic level.

11. The half-bridge driver circuit of claim 10, wherein the state machine is configured to: receive a synchronization signal; when the synchronization signal has a first logic level, proceed from the first state to the second state in response to the second signal; when the synchronization signal has a second logic level, proceed from the first state to the third state in response to the second signal; proceed from the second state to the first state in response to the first signal; and proceed from the third state to the first state in response to the first signal.

12. The half-bridge driver circuit of claim ii, further comprising a further input terminal configured to receive the synchronization signal.

13. The half-bridge driver circuit of claim 10, wherein the state machine is configured to proceed to one of the first, second or third states in response to a reset signal.

14. The half-bridge driver circuit of claim 1, further comprising: two further input terminals configured to receive two further control signals; four further output terminals configured to provide two further high side drive signals for two further high side switches and two further low side drive signals for two further low side switches; two further high side driver circuits configured to generate the two further high side drive signals as a function of two further high side control signal; two further low side driver circuits configured to generate the two further low side drive signals as a function of two further low side control signal; and two further circuits configured to generate the two further high side control signal and the two further low side control signal as a function of the two further control signals.

15. The half-bridge driver circuit of claim 14, further comprising the high side switch, the low side switch, the two further high side switches, and the two further low side switches coupled to the half-bridge driver circuit.

16. The half-bridge driver circuit of claim 1, wherein the half-bridge driver circuit is integrated in a monolithic integrated circuit.

17. A system comprising: a half-bridge comprising a high side switch, a low side switch, and an output, wherein the output of the half-bridge is configured to be coupled to a phase of a motor; a high side output terminal configured to provide a high side drive signal to the high side switch; a low side output terminal configured to provide a low side drive signal to the low side switch; a high side driver circuit configured to generate the high side drive signal as a function of a high side control signal; a low side driver circuit configured to generate the low side drive signal as a function of a low side control signal; a signal generator configured to generate a control signal; an edge detector configured to generate a first signal in response to a first type of edge in the control signal, and a second signal in response to a second type of edge in the control signal, the second type of edge being opposed to the first type of edge; and a state machine comprising a plurality of states, wherein transition between the states occurs in response to the first signal and the second signal, and wherein the state machine is configured to sequentially: in response to the first signal, set the high side control signal and the low side control signal to a first logic level, in response to the second signal, set the high side control signal to a second logic level and the low side control signal to the first logic level; in response to the first signal, set the high side control signal and the low side control signal to the first logic level, and in response to the second signal, set the high side control signal to the first logic level and the low side control signal to the second logic level.

18. The system of claim 17, further comprising the motor, wherein the output of the half-bridge is coupled to a phase of the motor.

19. The system of claim 18, wherein the motor is a multi-phase motor.

20. A method comprising: providing a high side drive signal to a high side switch of a half-bridge; providing a low side drive signal to a low side switch of the half-bridge; generating the high side drive signal as a function of a high side control signal; generating the low side drive signal as a function of a low side control signal; receiving a control signal; generating the high side control signal and the low side control signal as a function of the control signal; generating a first signal in response to a first type of edge in the control signal; generating a second signal in response to a second type of edge in the control signal, the second type of edge being opposed to the first type of edge; and sequentially, in response to the first signal, setting the high side control signal and the low side control signal to a first logic level, in response to the second signal, setting the high side control signal to a second logic level and the low side control signal to the first logic level, in response to the first signal, setting the high side control signal and the low side control signal to the first logic level, and in response to the second signal, setting the high side control signal to the first logic level and the low side control signal to the second logic level.

21. The method of claim 20, further comprising driving a three-phase motor with the half-bridge.

22. The method of claim 20, further comprising: receiving two further control signals; providing two further high side drive signals to two further high side switches; providing two further low side drive signals to two further low side switches; generating the two further high side drive signals as a function of two further high side control signal; generating the two further low side drive signals as a function of two further low side control signal; and generating the two further high side control signal and the two further low side control signal as a function of the two further control signals.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Embodiments of the present disclosure will now be described with reference to the annexed drawings, which are provided purely by way of non-limiting example and in which:

(2) FIGS. 1, 2, 3 and 4 show solutions for driving a motor;

(3) FIGS. 5 and 6 show an example of a half-bridge driver;

(4) FIG. 7 shows an embodiment of a half-bridge driver circuit comprising a processing circuit configured to generate high side and low side control signals as a function of a control signal;

(5) FIGS. 8, 9, 10 and 11 show an embodiment of the processing circuit of FIG. 7;

(6) FIG. 12 shows a further embodiment of a half-bridge driver circuit comprising a processing circuit configured to generate high side and low side control signals as a function of a control signal; and

(7) FIG. 13 show an embodiment of the processing circuit of FIG. 12.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

(8) In the following description, numerous specific details are given to provide a thorough understanding of embodiments. The embodiments can be practiced without one or several specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the embodiments.

(9) Reference throughout this specification to one embodiment or an embodiment means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrases in one embodiment or in an embodiment in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

(10) The headings provided herein are for convenience only and do not interpret the scope or meaning of the embodiments.

(11) In the following FIGS. 7 to 13, parts, elements or components which have already been described with reference to FIGS. 1 to 6 are denoted by the same references previously used in such Figures; the description of such previously described elements will not be repeated in the following in order not to overburden the present detailed description.

(12) As mentioned in the foregoing, the present disclosure relates to a half-bridge driver circuit, such as a half-bridge driver IC.

(13) As described in the foregoing, in the architecture shown in FIGS. 5 and 6, the signal generation circuit 30, such as a microcontroller, is configured to generate six PWM signals IN.sub.1 . . . IN.sub.6, which are provided at respective inputs to a driver IC 22. For example, when driving a three-phase motor M.sub.3 as shown in FIG. 3, the various outputs OUT.sub.a, OUT.sub.b and OUT.sub.c are sequentially connected to the supply voltage Vdd (and Ground GND), as described e.g., in document AN1088APPLICATION NOTEL6234 THREE PHASE MOTOR DRIVER, STMicroelectronics, April 2001, which is incorporated herein by reference.

(14) However, this solution is complex because two control signals have to be provided to the driver circuit 22 for each half-bridge. For example, this may result in additional complexity when the signal generator 30 and/or the driver circuit 22 should also monitor the PWM control signals for detecting errors. For example, a possible solution for monitoring PWM signals is described in Italian patent application IT102016000049920, which is incorporated herein by reference. Specifically, in this document, circuits able to monitor the period, switch-on and switch-off duration of a PWM signal are described.

(15) Accordingly, when using such a solution in the signal generator 30 and/or driver circuit 22, six error detection circuits would be required.

(16) Various embodiments of the present disclosure relate to a driver circuit 22a that may operate with a reduced number of control signals such that the signal generator 30 (e.g., a microcontroller) generates less control signals.

(17) For example, FIG. 7 shows an embodiment of a driver circuit 22a, such as an integrated circuit, configured to receive at an input a single control signal CTR for each half-bridge, and the driver circuit 22a is configured to generate a high side drive signal for a respective high side switch and a low side drive signal for a respective low side switch as a function of the control signal CTR. Specifically, in the embodiment considered, the driver circuit 22a comprises a respective high side drive circuit for generating the high side drive signal as a function of a high side control signal and a low side drive circuit for generating the low side drive signal as a function of a low side control signal. Accordingly, in various embodiment, the driver circuit 22a comprises a processing circuit 208 configured to generate the high side control signal and the low side drive signal for the high side and low side drivers as a function of the respective control signal CTR.

(18) For example, in the embodiment considered, the driver circuit 22a is again configured to drive three half bridges. Accordingly, the driver circuit is configured to receive three control signals CTR.sub.1, CTR.sub.2 and CTR.sub.3 and generate respective drive signals DRV.sub.1, DRV.sub.3 and DRV.sub.5 for three high side switches SW.sub.1, SW.sub.3 and SW.sub.5 and respective drive signals DRV.sub.2, DRV.sub.4 and DRV.sub.6 for three low side switches SW.sub.2, SW.sub.4 and SW.sub.6.

(19) More specifically, the driver circuit 22a comprises three circuits 2081, 2082 and 208.sub.3 configured to generate for each control signals CTR.sub.1, CTR.sub.2 and CTR.sub.3 a respective high side control signal IN.sub.1, IN.sub.3 and IN.sub.5 and a respective low side control signal IN.sub.2, IN.sub.4 and IN.sub.6.

(20) Generally, the implementation of the driver circuit 22a for generating a drive signal DRV as a function of the control signal IN may correspond to the architecture of the circuit 22 shown in FIG. 5 and the respective description fully applies. For example, in the embodiment considered, the driver circuit 22a comprises three high side drivers 200.sub.1, 200.sub.3 and 200.sub.5 configured to generate the drive signals DRV.sub.1, DRV.sub.3 and DRV.sub.5 for three high side switches SW.sub.1, SW.sub.3 and SW.sub.5 and three low side drivers 200.sub.2, 200.sub.4 and 200.sub.6 configured to generate the drive signals DRV.sub.2, DRV.sub.4 and DRV.sub.6 for three low side switches SW.sub.2, SW.sub.4 and SW.sub.6. Optionally, the driver circuit 22a may also comprise the electronic converter 204 configured to generate the supply voltage Vdd and/or the differential amplifiers 206 for measuring the current flowing through the motor phases.

(21) Accordingly, in the embodiment considered, the driver circuit 22a is arranged to drive N=.sub.3 half-bridges, where the driver circuit 22a comprises for each half-bridge a respective high side driver and a respective low side driver. Generally, the driver circuit 22a could also be configured to drive less (e.g., one or two) or more half-bridges.

(22) Moreover, even though being arranged to drive N=.sub.3 half-bridges, the driver circuit 22a may also be used to drive a motor M.sub.1 connected between the output of a half-bridge and ground GND (see FIG. 1). For example, for this purpose, only two drive signals (e.g., DRV.sub.1 and DRV.sub.2) of the driver circuit 22a may be used. Similarly, the driver circuit 22a may also be used to drive a motor M.sub.2 connected between the outputs of two half-bridge (see FIG. 2). For example, for this purpose, only four drive signals (e.g., DRV.sub.1 . . . DRV.sub.4) of the driver circuit 22a may be used. Thus, generally the driver circuit 22a may be configured to drive a single-phase motor via one or two half-bridges, or a multi-phase motor (e.g., a three-phase motor) via a corresponding number of half-bridges.

(23) As described in the foregoing, in various embodiments, the driver circuit 22a comprises for each half-bridge a single input for receiving a respective control signal (CTR and a circuit 208 configured to generate a respective high side control signal (e.g., signal IN.sub.1) and a respective low side control signal (e.g., signal IN.sub.2), which are provided to a high side driver (e.g., 200.sub.1) and a low side driver (e.g., 200.sub.2), respectively.

(24) FIG. 8 shows a first embodiment of the circuit 208, such as the circuit 208.sub.1 configured to generate the signals IN.sub.1 and IN.sub.2 as a function of the control signal CTR.sub.1. Generally, the same architecture may be used also for the other circuits 208.

(25) Specifically, in the embodiment considered, the circuit 208.sub.1 comprises a rising edge detector 2080 configured to generate a signal RE by analyzing the control signal CTR.sub.1, i.e., the signal RE indicates a rising edge in the signal CTR.sub.1. Moreover, the circuit 208.sub.1 comprises a falling edge detector 208.sub.2 configured to generate a signal FE by analyzing the control signal CTR.sub.1, i.e., the signal FE indicates a falling edge in the signal CTR.sub.1. Generally, the edge detectors 2080 and 2082 may also be combined in a single edge detector providing both signals RE and FE. In the embodiment considered, the signal RE and FE are provided to a (finite) state machine 2084 configured to generate the high side control signal IN.sub.1 and the low side control signal IN.sub.2.

(26) FIG. 9 shows an embodiment of the operation of the processing circuit 208.

(27) Specifically, in the embodiment considered, the control signal CTR.sub.1 is not a traditional PWM signal, but the signal generator 30 is configured to generate a control signal CTR.sub.1 comprising pulses in correspondence to the delays T.sub.ONDT and T.sub.OFFDT, i.e., the signal CTR.sub.1 is a periodic signal with a given duration T.sub.PWM comprising:

(28) a first pulse with duration T.sub.ONDT, where the first pulse starts after the switch-off duration (T.sub.OFFaT.sub.ONDT) from the beginning of the corresponding PWM cycle; and

(29) a second pulse with duration T.sub.OFFDT, where the second pulse starts after the switch-on duration T.sub.ON from the end of the first pulse.

(30) Accordingly, assuming that the PWM cycle starts at an instant t.sub.0, the signal CTR.sub.1 comprises:

(31) a rising edge at an instant t.sub.1=T.sub.OFFaT.sub.ONDT;

(32) a falling edge at an instant t.sub.2=t.sub.1+T.sub.ONDT=T.sub.OFFa;

(33) a rising edge at an instant t.sub.3=t.sub.2+T.sub.ON; and

(34) a falling edge at an instant t.sub.4=t.sub.3+T.sub.OFFDT.

(35) Generally, the signal CTR.sub.1 and thus the above edges may also be inverted. Accordingly, generally, the edge detector 2080 is configured to generate a signal RE indicative of a first type of edge (e.g., rising in the embodiment considered) and the edge detector 2082 is configured to generate a signal FE indicative of a second type of edge opposed to the first type of edge (e.g., falling in the embodiment considered).

(36) Generally, the edge detectors 2080 and 2082 may be implemented with asynchronous or synchronous edge detectors. For example, a synchronous edge detector may sample the signal CTR.sub.1 in order to determine a bit sequence. Accordingly, a rising edge may be detected when the bit sequence has the value 01 for a two-bit sequence, or 001 or 011 for a three-bit sequence, etc. Similarly, a falling edge may be detected when the bit sequence has the value 10 for a two-bit sequence, or 100 or 110 for a three-bit sequence, etc.

(37) FIG. 10 shows an embodiment of the state machine 2084, which, e.g., may be implemented with a sequential logic circuit.

(38) Specifically, in the embodiment considered, the state machine comprises at least four states S1 . . . S4, in particular:

(39) state S1 is used to generate the control signals IN.sub.1/IN.sub.2 during the duration T.sub.ONDT, i.e., IN.sub.1=0 and IN.sub.2=0;

(40) state S2 is used to generate the control signals IN.sub.1/IN.sub.2 during the duration T.sub.ON, i.e., IN.sub.1=1 and IN.sub.2=0;

(41) state S3 is used to generate the control signals IN.sub.1/IN.sub.2 during the duration T.sub.OFFDT, i.e., IN.sub.1=0 and IN.sub.2=0;

(42) state S4 is used to generate the control signals IN.sub.1/IN.sub.2 during the remaining duration T.sub.OFF (in particular the duration T.sub.OFFT.sub.OFFDTT.sub.ONDT), i.e., IN.sub.1=0 and IN.sub.2=1.

(43) In various embodiments, after a reset of the circuit 208, the state machine 2084 may move to one of the states S1 . . . S4. For example, based on the application, the state machine may move to the states S1 or S3, where the half-bridge switches are switched off, or preferably the state S4, where only the low side switch is closed. In various embodiments, the circuit 208 may be configured to render the initial state after a reset programmable. For example, in various embodiments, the driver circuit 22a may comprise a communication interface 210 connected to one or more interface terminals IF (see FIG. 7). For example, the communication interface 210 may be serial communication interface, such as Inter-Integrated Circuit (I2C), Serial Peripheral Interface bus (SPI), or Universal asynchronous receiver-transmitter (UART).

(44) The operation of the state machine 2084 will now be described at a typical switching cycle, assuming the state machine is in the state S4 at the beginning of a new switching cycle, i.e., instant t.sub.0. Specifically, in the state S4, the high side switch SW.sub.1 is opened (IN.sub.1=0) and the low side switch SW.sub.2 is closed (IN.sub.2=1).

(45) The state machine is configured to remain in the state S4 until a new (rising) edge is signaled by the circuit 2080 via the signal RE (instant t.sub.1). Accordingly, once the signal RE is set, the state machine proceeds to the state S1, in which the high side switch SW.sub.1 and the low side switch SW.sub.2 are opened (IN.sub.1=0 and IN.sub.2=0).

(46) The state machine is configured to remain in the state S1 until a new (falling) edge is signaled by the circuit 2082 via the signal FE (instant t.sub.2). Accordingly, once the signal FE is set, the state machine proceeds to the state S2, in which the high side switch SW.sub.1 is closed (IN.sub.1=1) and the low side switch SW.sub.2 is opened (IN.sub.2=0).

(47) The state machine is configured to remain in the state S2 until a new (rising) edge is signaled by the circuit 2080 via the signal RE (instant t.sub.3). Accordingly, once the signal RE is set, the state machine proceeds to the state S3, in which the high side switch SW.sub.1 and the low side switch SW.sub.2 are opened (IN.sub.1=0 and IN.sub.2=0).

(48) Finally, the state machine is configured to remain in the state S3 until a new (falling) edge is signaled by the circuit 2082 via the signal FE (instant t.sub.4). Accordingly, once the signal FE is set, the state machine proceeds again to the state S4, in which the high side switch SW.sub.1 is opened (IN.sub.1=0) and the low side switch SW.sub.2 is closed (IN.sub.2=1).

(49) Accordingly, in response to the rising and falling edges in the control signal CM, the state machine evolves sequentially through the states S1 . . . S4.

(50) For example, FIG. 11 shows a possible implementation of the state machine 2084.

(51) In the embodiment considered, the state machine is implemented with a Moore state machine comprising:

(52) a state register 2086 configured to store the value of a current state S, where the value of a next states NS is stored in response to a clock signal CLK;

(53) a combinational logic 2088 circuit configured to generating the next state signal NS as a function of the current state S (at the output of the states register 2086) and the input signals, i.e., signals RE and FE; and

(54) a combinational logic circuit 2090 configured to generating the output signals IN.sub.1 and IN.sub.2 as a function of the current state S (at the output of the states register 2086).

(55) Moreover, as mentioned before, the state register 2086 may support a reset, e.g., via a reset signal RST, which sets the content of the register 2086 to a reset value, e.g., corresponding to the bit sequence associated with the state S4.

(56) For example, in various embodiments, the register 2086 has three bits and the following encoding is used for the states:

(57) S1: S=000;

(58) S2: S=110;

(59) S3: S=100; and

(60) S4: S=001.

(61) For example, by using this encoding, the circuit 2090 may select the second bit of state S as the control signal IN.sub.1 and the third/last bit of state S as the control signal IN.sub.2.

(62) Generally, the state machine 2084 may also be configured to monitor incongruent input signals. For example, the state machine may monitor in the states S1 and S3 whether the signal RE is set and possibly proceed to an error state. Similarly, the state machine may monitor in the states S3 and S4 whether the signal FE is set and possibly proceed to an error state.

(63) Similarly, the state machine 2084 may monitor the state signal S in order to determine incongruent states. For example, in the embodiment considered, the states 011 and 111 may be incongruent states, because the last two bits should not be set contemporaneously to 1. Also in this case, the state machine may proceed to an error state.

(64) Accordingly, in the embodiment considered, the state machine 2084 performs transitions in response to the signals RE and FE (i.e., in response to the rising and falling edges in the signal the signal CTR.sub.1), thereby sequentially passing through the states S1 . . . S4 starting from a given reset state.

(65) However, when loosing synchronization, e.g., due to errors/glitches in the control signal CTR the state machine may skip one of the two pulses in the control signal CTR.sub.1 resulting in an inversion of the control signals IN.sub.1 and IN.sub.2, i.e., an incorrect driving of the half-bridge. To detect this type of fault, different counter measures can be implemented. For example, in various embodiments, the circuit 208 may comprise an internal watchdog timer. For example, the internal watchdog timer may be reset by the signal RE (or by the signal FE) and it communicates an error if the timer reaches a programmable threshold. For example, in various embodiments, the threshold is set via the interface 210. Generally, the threshold should be greater than MAX(T.sub.PWMT.sub.ONDT,T.sub.PWMT.sub.OFFDT) and smaller than T.sub.PWM.

(66) FIG. 12 shows a further embodiment of the driver circuit 22a comprising an additional terminal for receiving a further control/synchronization signal CTR.sub.0.

(67) Specifically, the control signal CTR.sub.0 is arranged to identify the respective switching cycle.

(68) For example, the control signal CTR.sub.0 may be a left-aligned PWM signal having again the switching period T.sub.PWM. For example, the control signal CTR.sub.0 may comprise a short pulse (with a duration being smaller than T.sub.OFFa) and the state machine 2084 may be configured to move to the state S4 in response to the control signal CTR.sub.0, e.g., by using the signal CTR.sub.0 as reset signal RST for the state register 2086.

(69) Alternatively, the control signal CTR.sub.0 may be a left-aligned PWM signal having a switch-on duration being greater than T.sub.OFFa and smaller than T.sub.OFFa+T.sub.ON, such as a PWM signal with 50% duty cycle. Accordingly, by providing the control signal CTR.sub.0 to the control circuits 208, in particular the state machines 2084, each state machine may determine whether a given (rising or falling) edge belongs to the interval T.sub.ONDT or T.sub.OFFDT. For example, in this case, the state machine may directly use the logic level of the control signal CTR.sub.0 in order to determine e.g.:

(70) whether the state machine 2084 should proceed either to the state S1 (e.g., CTR.sub.0=1) or S3 (e.g., CTR.sub.0=0) in response to a rising edge (RE=1); and

(71) whether the state machine 2084 should proceed either to the state S2 (e.g., CTR.sub.0=1) or S4 (e.g., CTR.sub.0=0) in response to a falling edge (FE=1).

(72) For example, a modified state machine is shown in FIG. 13.

(73) Specifically, in the embodiment considered, the states S1 and S3 have been combined in a single state S1.

(74) For example, again assuming that the state machine 2084 is in the state S4 at the beginning of a new switching cycle, i.e., instant t.sub.0, the high side switch SW.sub.1 is opened (IN.sub.1=0) and the low side switch SW.sub.1 is closed (IN.sub.2=1).

(75) The state machine is configured to remain in the state S4 until a new (rising) edge is signaled by the circuit 2080 via the signal RE. Accordingly, once the signal RE is set, the state machine proceeds to the state S1, in which the high side switch SW.sub.1 and the low side switch SW.sub.2 are opened (IN.sub.1=0 and IN.sub.2=0).

(76) The state machine is configured to remain in the state S1 until a new (falling) edge is signaled by the circuit 2082 via the signal FE. Accordingly, once the signal FE is set, the state machine proceeds either:

(77) to the state S2 when the signal CTR.sub.0 is set; or

(78) to the state S4 when the signal CTR.sub.0 is not set.

(79) Specifically, in the state S2 the high side switch SW.sub.1 is again closed (IN.sub.1=1) and the low side switch SW.sub.2 is opened (IN.sub.2=0).

(80) Generally, the control/synchronization signal CTR.sub.0 may have inverted logic levels. Moreover, a single control/synchronization signal CTR.sub.0 may be used for all circuits 208. For example, in this case, a driver circuit 22a for three half-bridges may receive at respective inputs four control signals instead of the six control signals shown in FIG. 5 in the context of prior-art solutions.

(81) Of course, without prejudice to the principle of the invention, the details of construction and the embodiments may vary widely with respect to what has been described and illustrated herein purely by way of example, without thereby departing from the scope of the present invention, as defined by the ensuing claims.