SAMPLING SIGNALS

Abstract

An asynchronous circuit portion for sampling an input signal is provided. The circuit portion comprises a sampling circuit portion arranged to sample the input signal to generate a sanitized output signal corresponding to the input signal; a comparison circuit portion arranged to compare the sanitized output signal with the input signal and to generate a change signal if the sanitized output signal does not correspond to the input signal; and a control circuit portion arranged to trigger the sampling circuit portion to sample the input signal to generate an updated sanitized output signal, in response to the change signal.

Claims

1. An asynchronous circuit portion for sampling an input signal comprising: a sampling circuit portion arranged to sample the input signal to generate a sanitized output signal corresponding to the input signal; a comparison circuit portion arranged to compare the sanitized output signal with the input signal and to generate a change signal if the sanitized output signal does not correspond to the input signal; and a control circuit portion arranged to trigger the sampling circuit portion to sample the input signal to generate an updated sanitized output signal, in response to the change signal.

2. The asynchronous circuit portion of claim 1, wherein the control circuit portion is arranged to trigger the sampling circuit portion to sample the input signal to generate an updated sanitized output signal every time a change signal is generated.

3. The asynchronous circuit portion of claim 1, wherein the sampling circuit portion comprises a first sampling element configured to generate a first sample signal if the input signal has a first state, a second sampling element configured to generate a second sample signal if the input signal has a second state, and arbitration logic arranged to detect an earliest sample signal from the first and second sample signals and to generate the sanitized output signal corresponding to the earliest sample signal.

4. The asynchronous circuit portion of claim 1, wherein the control portion is arranged to trigger a new sample by issuing a start command to the sampling circuit portion.

5. The asynchronous circuit portion of claim 1, wherein the circuit portion is operable in a hold mode in which the sanitized output signal is held constant, regardless of changes to the input signal.

6. The asynchronous circuit portion of claim 5, wherein the control circuit portion is arranged to ignore change signals in the hold mode.

7. The asynchronous circuit portion of claim 5, arranged to enter the hold mode in response to receiving a hold request signal.

8. The asynchronous circuit portion of claim 7, comprising a mutual-exclusion element arranged to take the hold request signal as a first input and the change signal as a second input.

9. The asynchronous circuit portion of claim 1, wherein the comparison circuit portion comprises an Exclusive-OR logic gate.

10. The asynchronous circuit portion of claim 1 wherein the comparison circuit portion is arranged to send the change signal to the control circuit portion only when a change signal request signal is asserted.

11. The asynchronous circuit portion of claim 1, arranged to output a ready signal when the sanitized output signal corresponds to the input signal.

12. A method of asynchronously sampling an input signal comprising: sampling the input signal at a first time to generate a sanitized output signal corresponding to the input signal at the first time: comparing the sanitized output signal with the input signal at a second time; and if the sanitized output signal does not correspond to the input signal at the second time, sampling the input signal again to generate an updated sanitized output signal.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0031] One or more non-limiting examples will now be described, by way of example only, and with reference to the accompanying figures in which:

[0032] FIG. 1 is a schematic diagram of a circuit portion according to an embodiment of the invention;

[0033] FIG. 2 is a schematic diagram of the control circuit portion shown in FIG. 1;

[0034] FIGS. 3 and 4 are timing diagrams illustrating active mode operation of the circuit portion of FIG. 1;

[0035] FIG. 5 is a timing diagram illustrating hold mode operation of the circuit portion of FIG. 1; and

[0036] FIG. 6 is a schematic diagram of the sampling circuit portion shown in FIG. 1.

DETAILED DESCRIPTION

[0037] FIG. 1 shows a circuit portion 2 comprising a sampling circuit portion 4, a comparison circuit portion 6 and a control circuit portion 8. The circuit portion \2 comprises an input 10 at which a potentially-glitchy input signal is received, and a sanitized output 14 from which a sanitized output signal is provided. The output \14 is connected to an external circuit 50. The circuit portion 2 also comprises a reset input 18.

[0038] The comparison circuit portion 6 comprises a comparator 7 (e.g. an XOR logic gate) and a handshake portion 9. The comparator 7 takes the input 10 and sanitized output 14 as inputs and sends an output sigChanged to the handshake portion 9. The handshake portion 9 of the comparison circuit portion 6 outputs a change signal ackSigChanged from a change output 12 if the input 10 and the sanitized output 14 are different (i.e. if the input signal and the sanitized output signals are different), and a change signal request signal reqSigChanged is asserted.

[0039] The control circuit portion 8 is shown in more detail in FIG. 2. The control circuit portion 8 receives and issues various control signals within the circuit portion 2 and externally (e.g. to and from the external circuit 50). The external connections of the control circuit portion 8 comprise the reset input 18, a sample ready output 21, a hold request input 22, a run request input 24, a run acknowledge output 26 and a hold acknowledge output 28. The internal connections of the control circuit portion 8 comprise a sample ready input 20, a sample trigger output 30, a signal change request output 32 and a signal change acknowledge input 34. In this embodiment the control circuit portion 8 passes signals received from the sample ready input 20 to the sample ready output 21. In other embodiments the sampling circuit portion 4 may provide a sample ready connection directly to the external circuit 50.

[0040] The circuit portion 8 also comprises a MUTEX element 23 that has the hold request input 22 as a first input r1 and the signal change acknowledge input 34 as a second input r2 (see FIG. 2). The first output g1 of the MUTEX element 23 provides the hold acknowledge output 28 and the second output g2 of the MUTEX element 23 is connected to circuitry leading to the signal change request output 32, the sample ready output 21 and the sample trigger output 30. The MUTEX is configured to assert a signal on only one output g1, g2 at a time, according to which input r1, r2 receives an asserted signal first.

[0041] The circuit portion 2 is switched on by receiving a run request signal reqRun on the run request input 24, on receipt of which the control circuit portion 8 asserts a run acknowledge signal ackRun on run acknowledge output 26. The circuit portion 2 is operable in an active mode and a hold mode under the control of the external circuit 50. When the control circuit portion 8 receives a hold request signal reqHoldSample at the hold request input 22 it enters the circuit portion 2 into the hold mode and asserts an acknowledgement signal ackHoldSample on the hold acknowledge output 28. When the hold request signal reqHoldSample is lowered by the external circuit 50 the control circuit portion 8 enters the circuit portion 2 into the active mode and lowers the acknowledgement ackHoldSample. It will be appreciated that the run request signal and/or run acknowledge signal are not essential. For instance, in some embodiments the circuit portion 2 is simply always on when it is powered. The circuit portion 2 may operate in the active mode as a default mode and operate in the hold mode when a hold request signal is received.

[0042] The active mode of operation will be described first, with additional reference to the timing diagrams shown in FIGS. 3 and 4. As will be explained in more detail, in the active mode the circuit portion 2 continuously compares the input 10 and the sanitized output 14 and the control circuit portion 8 triggers the sampling circuit 4 portion to take a new sample of the input 10 whenever the input signal differs from the sanitized output signal (i.e. whenever the input changes). This keeps the sanitized output signal continuously up-to-date.

[0043] Referring now to the operation illustrated in the timing diagram of FIG. 3, at a first time t.sub.0 the run request input 24 is high, the hold request input 22 is low and so the circuit portion 2 is in the active mode. The input signal at the input 10 is low and the sanitized output 14 is also low (i.e. from a previous sampling of the input 10). Because the input signal and the sanitized output signal are the same, the comparison circuit portion 6 does not assert the change signal at the change output 12. The reqSigChanged signal is being asserted on the signal change request output 32 by the control circuit portion 8. The reqSigChanged signal indicates that the control circuit 8 is ready to react to changes in state of the input signal.

[0044] At a time t.sub.1, the input 10 goes high. The input and output signals are now different and at t.sub.2, after a short delay for the logic in the comparison circuit portion 6 to react, the change signal ackSigChanged is asserted by the comparison circuit portion 6 at change output 12. The short delay in the comparison circuit portion 6 helps to avoid transient changes in the input signal triggering the change signal ackSigChanged.

[0045] In response to the change signal ackSigChanged, the control circuit portion 8 triggers the sampling circuit portion 4 to sample the input 10 and thus update the sanitized output signal by briefly lowering the startSample signal. The sampling circuit portion 4 lowers the readySample signal input to the sample ready input 20 and begins the sampling process. The operation of the sampling circuit portion 4 is described in more detail below with reference to FIG. 6. The lowered readySample signal is output from the sample ready output 21 and indicates to the external circuit that the current sanitized output 14 is different to the current input 10, i.e. that the current sanitized output signal is not up-to-date.

[0046] At t.sub.3, the sampling circuit portion 4 has completed the sampling process and the sanitized output 14 goes high to match the sampled input 10. The control circuit portion 8 then re-asserts the ready signal to indicate to the external circuit portion 50 that the output signal is once again up-to-date. Because the input 10 and the sanitized output 14 are now in correspondence, the control circuit portion 8 lowers the reqSigChanged signal, and the comparison circuit portion 6 consequently lowers the change signal ackSigChanged on the change output 12. The control circuit portion 8 then re-asserts the reqSigChanged signal to wait for the next change of the input signal.

[0047] FIG. 4 illustrates a corresponding set of operations for the situation in which the input 10 changes from high to low at time t.sub.0 and the sanitized output 14 accordingly goes low at t.sub.3. The operation of the circuit portion 2 is otherwise the same as that described with reference to FIG. 3.

[0048] FIGS. 3 and 4 illustrate how, in the active mode, the circuit portion 2 provides a continuously updated sanitized output signal to the external circuit 50. The external circuit 50 does not need to specifically request updates but is instead simply provided with these automatically.

[0049] Hold mode operation of the circuit portion 2 will now be described with reference to the timing diagram in FIG. 5. The hold mode may be of use for periods of time when the external circuit 50 is not able to (or simply does not need to) react to changes to the sanitized output 14.

[0050] At t.sub.4, the external circuit 50 is asserting a hold request signal reqHoldSample, which is received at the hold request input 22 of the control circuit portion 8. In response, the control circuit portion 8 puts the circuit portion 2 into the hold mode and outputs a hold acknowledge signal ackHoldSample from the hold acknowledge output 28. At t.sub.4, the input 10 and the sanitized output 14 are both high.

[0051] At t.sub.5, the external circuit 50 lowers the hold request signal reqHoldSample. The input signal 10 has not changed during the hold mode (e.g. because it comes from a stable source), and so the change signal ackSigChanged is low at the change signal output 12.

[0052] The sanitized output signal is thus already in correspondence with the input signal and no new sample needs to be taken. Both inputs to the MUTEX element 23 are now low and it immediately indicates that no new sample needs to be taken by not asserting a signal on either of its outputs. The external circuit 50 is thus provided with an up-to-date sample of the input 10 as soon as the hold request acknowledge signal is lowered (i.e. very shortly after ts). This represents a significant speed increase over prior art approaches that require a new sample to be taken to be confident that the input signal corresponds to the output signal. For instance, in one simulation of the circuit portion 4 the control circuit portion 8 took an average of 0.208 ns to lower the hold request acknowledge signal in response to the lowering of the hold request signal, but took an average of 1.745 ns to take a new sample of the input signal with the sampling circuit portion 6. Thus in at least some situations the invention may be approximately eight times faster than previous approaches. The sampling circuit portion 6 is shown in more detail in FIG. 6. The sample circuit portion 6 comprises two sampling elements 1202, 1204 that are used to detect the state of the input signal sig on receipt of the start signal startSample. The first sampling element 1202 outputs a logic high signal when the input signal goes low, and the second sampling element 1204 outputs a logic high signal when the input signal goes high. The outputs of these sampling elements 1202, 1204 feed into additional logic including a mutual exclusion element 1206 and several Muller-C elements 1208, which are arranged to produce a first stable output 1210 that is logic high when the sampled signal is logic low and a second stable output 1212 that is logic high when the sampled signal is logic high.

[0053] The sampling circuit portion 6 further comprises an RS latch 1214 that receives the first stable output 1210 and the second stable output 1212 and produces the sanitised output signal at output 1216.

[0054] While the invention has been described in detail in connection with only a limited number of embodiments, it should be readily understood that the invention is not limited to such disclosed embodiments. Rather, the invention can be modified to incorporate any number of variations, alterations, substitutions or equivalent arrangements not heretofore described, but which are commensurate with the scope of the invention. Additionally, while various embodiments of the invention have been described, it is to be understood that aspects of the invention may include only some of the described embodiments. Accordingly, the invention is not to be seen as limited by the foregoing description, but is only limited by the scope of the appended claims.