Four-way Doherty amplifier and mobile telecommunications base station

Abstract

The present invention relates to a four-way Doherty amplifier. The invention further relates to a mobile telecommunications base station. The invention proposes a new Doherty combiner topology that allows peak efficiencies to be reached at deeper back-off levels than conventional Doherty combiners.

Claims

1. A four-way Doherty amplifier, comprising: an input terminal (1) for receiving a signal to be amplified by the four-way Doherty amplifier; a main amplifier (M) having a main input and a main output; a first peak amplifier (P1) having a first input and a first output; a second peak amplifier (P2) having a second input and a second output; a third peak amplifier (P3) having a third input and a third output; an input distribution network (3) for distributing the signal received at the input terminal to the main amplifier, the first peak amplifier, the second peak amplifier, and the third peak amplifier; and a Doherty combiner (4) for combining, at a first combining node (N1), signals received from the main amplifier, the first peak amplifier, the second peak amplifier, and the third peak amplifier, said Doherty combiner comprising: a second branch (b2) between the first combining node (N1) and a second combining node (N2) and comprising a second impedance inverter (Z.sub.02), wherein the third output is connected to the first combining node (N1) via a first branch (b1); a third branch (b3) between the second combining node (N2) and the main output and comprising a third impedance inverter (Z.sub.03); a fourth branch (b4) between the second combining node (N2) and a third combining node (N3) and comprising a fourth impedance inverter (Z.sub.04), wherein the second output is connected to the third combining node (N3) via a sixth branch (b6); and a fifth branch (b5) between the first output and the third combining node (N3) and comprising a fifth impedance inverter (Z.sub.05) wherein maximum power capacities of the main amplifier, the first peak amplifier, the second peak amplifier, and the third peak amplifier are substantially identical, wherein a supply voltage supplied to the main amplifier, the first peak amplifier, the second peak amplifier, and the third peak amplifier is substantially identical, and wherein the first, second, and third peak amplifiers are configured to turn-on at substantially the same power level of the signal inputted to the Doherty amplifier.

2. The four-way Doherty amplifier of claim 1, wherein a signal outputted by the second peak amplifier first combines with a signal outputted by the first peak amplifier at the third combining node to thereby form a first combined signal; wherein a signal outputted by the main amplifier first combines with the first combined signal at the second combining node to thereby form a second combined signal; and wherein a signal outputted by the third peak amplifier first combines with the second combined signal at the first combining node.

3. The four-way Doherty amplifier of claim 1, wherein the input distribution network and the Doherty combiner are configured such that the signals amplified by the main amplifier, the first peak amplifier, the second peak amplifier, and the third peak amplifier, add substantially in-phase at the first combining node.

4. The four-way Doherty amplifier of claim 1, further comprising an output terminal (2) for outputting the combined signals to a load (R.sub.LOAD), and an output impedance inverter (Z.sub.OUT) arranged in between the first combining node (N1) and the output terminal (2).

5. The four-way Doherty amplifier of claim 1, wherein the input distribution network comprises: a seventh branch between the input terminal and the third input; an eighth branch in between the input terminal and the main input; a ninth branch between the input terminal and the first input; a tenth branch between the input terminal and the second input; wherein: the seventh branch is configured to introduce a phase delay between the input terminal and the third input that substantially equals (270+(n.sub.7180) degrees); the eighth branch is configured to introduce a phase delay between the input terminal and the main input that substantially equals (90+(n.sub.8180) degrees); the ninth branch is configured to introduce a phase delay between the input terminal and the first input that substantially equals (n.sub.9180 degrees); and the tenth branch is configured to introduce a phase delay between the input terminal and the second input that substantially equals (90+(n.sub.10180) degrees) wherein n.sub.7, n.sub.8, n.sub.9, and n.sub.10 are integer numbers.

6. The four-way Doherty amplifier of claim 5, wherein: the seventh branch comprises a seventh impedance inverter; the eighth branch comprises an eighth impedance inverter; and the tenth branch comprises a tenth impedance inverter.

7. The four-way Doherty amplifier of claim 1, wherein the input distribution network comprises a first quadrature hybrid coupler (H1), a second quadrature hybrid coupler (H2), and a third quadrature hybrid coupler (H3), each of the first, second, and third quadrature hybrid couplers comprising a coupler input node, a first coupler output node, a second coupler output node, and a coupler isolated node that is terminated with a predefined load, wherein: the input terminal is connected to the coupler input node of the first quadrature hybrid coupler; the second coupler output node of the first quadrature hybrid coupler is coupled to the coupler input node of the second quadrature hybrid coupler, and the first coupler output node of the first quadrature hybrid coupler is coupled to the coupler input node of the third quadrature hybrid coupler; the first coupler output node of the second quadrature hybrid coupler is coupled to the main input; the first coupler output node of the third quadrature hybrid coupler is coupled to second input; the second coupler output node of the second quadrature hybrid coupler is coupled to third input; the second coupler output node of the third quadrature hybrid coupler is coupled to first input; wherein the input distribution network further comprises an ninth impedance inverter (Z.sub.09) arranged in between the first coupler output node of the second quadrature hybrid coupler and the main input.

8. The four-way Doherty amplifier according to claim 1, wherein each amplifier of the main amplifier, the first peak amplifier, the second peak amplifier, and the third peak amplifier, comprises a power transistor (10, 11, 12, 13) having a transistor input and a transistor output; the four-way Doherty amplifier further comprising: a main input matching network Zin0.sub.match connected to the transistor input of the power transistor of the main amplifier; a first input matching network Zin1.sub.match connected to the transistor input of the power transistor of the first peak amplifier; a second input matching network Zin2.sub.match connected to the transistor input of the power transistor of the second peak amplifier; a third input matching network Zin3.sub.match connected to the transistor input of the power transistor of the third peak amplifier; a main output matching network Zout0.sub.match connected to the transistor output of the power transistor of the main amplifier; a first output matching network Zout1.sub.match connected to the transistor output of the power transistor of the first peak amplifier; a second output matching network Zout2.sub.match connected to the transistor output of the power transistor of the second peak amplifier; and a third output matching network Zout3.sub.match connected to the transistor output of the power transistor of the third peak amplifier, wherein the first, second, third, fourth, and fifth impedance inverters comprise a quarter-wavelength transmission line, such as a quarter-wavelength micro-strip line, or an electrical equivalent thereof; wherein the first branch is configured to introduce a phase delay between the third output and the first combining node (N1) that substantially equals n.sub.1180 degrees; wherein the second branch is configured to introduce a phase delay between the second combining node (N2) and the first combining node (N1) that substantially equals (90+(n.sub.2180) degrees); wherein the third branch is configured to introduce a phase delay between the main output and the second combining node that substantially equals (90+(n.sub.3180) degrees); wherein the fourth branch is configured to introduce a phase delay between the third combining node and the second combining node that substantially equals (90+(n.sub.4180) degrees); wherein the fifth branch is configured to introduce a phase delay between the first output and the third combining node that substantially equals (90+(n.sub.4180) degrees); wherein the sixth branch is configured to introduce a phase delay between the second output and the third combining node (N3) that substantially equals n.sub.6180 degrees; wherein n.sub.1, n.sub.2, n.sub.3, n.sub.4, n.sub.5, and n.sub.6 are integer numbers, and wherein the main output matching network Zout0.sub.match substantially forms the third impedance inverter (Z.sub.03), and wherein the first output matching network Zout1.sub.match substantially forms the fifth impedance inverter (Z.sub.05), and wherein the first branch comprises said third output matching network Zout3.sub.match and a phase delay component (Z.sub.01) for introducing a phase delay equaling 90+(n.sub.1180) degrees, and wherein the sixth branch comprises said second output matching network Zout2.sub.match and a phase delay component (Z.sub.06) for introducing a phase delay equaling 90+(n.sub.6180) degrees, wherein n.sub.1 and n.sub.6 are integer numbers.

9. The four-way Doherty amplifier according to claim 8, wherein at least two of the main input matching network Zin0.sub.match, the first input matching network Zin1.sub.match, the second input matching network Zin2.sub.match, and the third input matching network Zin3.sub.match, are identical; and wherein at least two of the main output matching network Zout0.sub.match, the first output matching network Zout1.sub.match, the second output matching network Zout2.sub.match, and the third output matching network Zout3.sub.match, are identical.

10. The four-way Doherty amplifier according to claim 8, wherein the power transistors of the main amplifier and the third peak amplifier are arranged on a single semiconductor die (14), and/or wherein the power transistors of the first peak amplifier and the second peak amplifier are arranged on a single semiconductor die (15), or wherein the power transistors of the main amplifier, the first peak amplifier, the second peak amplifier, and the third peak amplifier are integrated on a single die.

11. The four-way Doherty amplifier according to claim 8, wherein at least part of the input and/or output matching network corresponding to the power transistor of the main amplifier, the first peak amplifier, the second peak amplifier, and the third peak amplifier are integrated on the same die as said power transistor.

12. The four-way Doherty amplifier according to claim 8, wherein the power transistors of the main amplifier and the third amplifier are integrated in a single package (16), and/or wherein the power transistors of the first amplifier and the second amplifier are integrated in a single package (17), or wherein the power transistors of the main amplifier, the first peak amplifier, the second peak amplifier, and the third peak amplifier are integrated in a single package.

13. The four-way Doherty amplifier according to claim 12, wherein at least part of the input and/or output matching network corresponding to the power transistor of the main amplifier, the first peak amplifier, the second peak amplifier, and the third peak amplifier are integrated in the same package as said power transistor.

14. The four-way Doherty amplifier according to claim 8, wherein the main amplifier, the first peak amplifier, the second peak amplifier, and the third peak amplifier are identical.

15. A mobile telecommunications base station comprising the four-way Doherty amplifier as defined in claim 1.

Description

(1) Next, the present invention will be described referring to the appended drawings, wherein:

(2) FIG. 1 illustrates a schematic layout of an amplifier in accordance with the present invention;

(3) FIG. 2 illustrates an electrical equivalent circuit to be used for the electrical analysis of the amplifier in FIG. 1;

(4) FIG. 3 illustrates the efficiency of the amplifier in FIG. 1 as a function of output power;

(5) FIG. 4 illustrates a schematic layout of an implementation of an amplifier in accordance with the present invention;

(6) FIG. 5 illustrates the gain and efficiency of the amplifier in FIG. 4 as a function of output power for three distinct frequencies in a given communication band; and

(7) FIG. 6 illustrates possible die and package implementations to be used with the amplifier of the present invention.

(8) FIG. 1 illustrates a schematic layout of an amplifier in accordance with the present invention. This architecture provides a novel way of combining the outputs of the main, first peak, second peak and third peak amplifiers resulting in a small load modulation factor of the main amplifier while obtaining a high efficiency at large back-off operation. In FIG. 1, a signal inputted at input terminal 1 of the Doherty amplifier, is split using an input distribution network 3 to a main M, first peak P1, second peak P2, and third peak P3 amplifier. The signals amplified by these amplifiers are collected and combined by Doherty combiner 4 and are delivered at an output terminal 2 to a load R.sub.LOAD.

(9) Combiner 4 comprises a first branch b1 that extends from the output of third peak amplifier P3 to a first combining node N1. This node is connected via an impedance inverter Z.sub.OUT to load R.sub.LOAD.

(10) Combiner 4 further comprises a second branch b2 that extends between a second combining node N2 and first combining node N1. Second branch b2 comprises an impedance inverter Z.sub.02. A third branch extends between an output of main amplifier M to second combining node N2, which branch comprises an impedance inverter Z.sub.03. A fourth branch b4 extends from second combining node N2 to a third combining node N3. This branch comprises an impedance inverter Z.sub.04. The output of first peak amplifier P1 is connected, via an impedance inverter Z.sub.05 comprised in a fifth branch b5, to third combining node N3. This latter node is also connected via a sixth branch b6 to the output of second peak amplifier P2.

(11) Input distribution network 3 comprises a seventh b7, eighth b8, ninth b9, and tenth b10 branch to distribute the signals to the amplifiers P3, M, P1, P2, respectively. These branches comprise an impedance inverter Z.sub.07, an impedance inverter Z.sub.08, no impedance inverter, and an impedance inverter Z.sub.10, respectively.

(12) In FIG. 1, the notation n/4 denotes a phase delay introduced by an impedance inverter that is equal to n times a quarter-wavelength, wherein n is an integer number.

(13) A simulation study on the layout of FIG. 1 has revealed that favorable values can be obtained if the power ratio of the amplifiers is set to 1:1:1:1 at the same supply voltage and if the peak amplifiers are configured to turn-on at the same power level of the signal inputted to the Doherty amplifier. In these cases, a single maximum efficiency point at 9.5 dB power back-off may be obtained while not exceeding a load modulation factor of 2.25 for the main amplifier.

(14) Next, the abovementioned simulation study will be explained in more detail referring to FIG. 2, which illustrates an electrical equivalent circuit of the layout in FIG. 1 with the exception that impedance inverter Z.sub.OUT and R.sub.LOAD are replaced by a single load R.sub.L. The analysis will provide design equations for the characteristic impedances of the impedance inverters in output combiner. In the analysis, it is assumed that each amplifier has been designed to provide optimal performance, in terms of efficiency and/or maximum power, when it is connected to a 50 Ohm load.

(15) The impedance inverters in Doherty combiner 4 can be described by the relationship between the input and output currents and voltages:

(16) $\begin{array}{cc}\left[\begin{array}{c}{V}_m\\ -{\mathrm{jI}}_m\end{array}\right]=\left[\begin{array}{cc}0& {\mathrm{jZ}}_{03}\\ j/Z_{03}& 0\end{array}\right]\left[\begin{array}{c}{V}_p\\ I_{o1}\end{array}\right]& \left(1\right)\\ \left[\begin{array}{c}{V}_{p1}\\ I_{p1}\end{array}\right]=\left[\begin{array}{cc}0& {\mathrm{jZ}}_{05}\\ j/Z_{05}& 0\end{array}\right]\left[\begin{array}{c}{V}_{p2}\\ I_{o2}\end{array}\right]& \left(2\right)\\ \left[\begin{array}{c}{V}_{p2}\\ I_{o2}-{\mathrm{jI}}_{p2}\end{array}\right]=\left[\begin{array}{cc}0& {\mathrm{jZ}}_{04}\\ j/Z_{04}& 0\end{array}\right]\left[\begin{array}{c}{V}_p\\ I_{o3}\end{array}\right]& \left(3\right)\\ \left[\begin{array}{c}{V}_p\\ I_{o4}\end{array}\right]=\left[\begin{array}{cc}0& {\mathrm{jZ}}_{02}\\ j/Z_{02}& 0\end{array}\right]\left[\begin{array}{c}{V}_{p3}\\ I_{o5}\end{array}\right]& \left(4\right)\end{array}$

(17) Applying Kirchhoff's law at nodes p and q:

(18) $\begin{array}{cc}{I}_{o1}+I_{o3}-I_{o4}=0& \left(5\right)\\ I_{o5}+{\mathrm{jI}}_{p3}-\frac{V_{p3}}{R_L}=0V_{p3}=V_o& \left(6\right)\end{array}$

(19) wherein the maximum voltage at node p is not restricted by any of the current sources but determined by the choice of the characteristic impedances Z.sub.03, Z.sub.02, and Z.sub.04. This implies that one of these values has to be set in advance in the design process.

(20) The currents of the amplifiers are assumed to be fundamental current amplitudes I.sub.m, I.sub.p1, I.sub.p2, and I.sub.p3, at any given input signal amplitude v.sub.in, where I.sub.m=f.sub.m(v.sub.in) and I.sub.p=f.sub.p(v.sub.in), wherein f.sub.m and f.sub.p are assumed to be simple piecewise linear functions. A short circuit termination is assumed for the harmonics.

(21) The output current and voltage of each impedance inverter can be expressed as a function of the input current and voltage from (1)-(4):

(22) $\mathrm{From}\left(1\right)\text{:}\{\begin{array}{ccccc}{V}_m={\mathrm{jZ}}_{03}{I}_{o1}& \left(8\right)& \mathrm{hence}& I_{o1}=\frac{V_m}{{\mathrm{jZ}}_{03}}& \left(9\right)\\ I_m=-V_p/Z_{03}& \left(10\right)& \mathrm{hence}& V_p=-Z_{03}{I}_m& \left(11\right)\end{array}\mathrm{From}\left(2\right)\text{:}\{\begin{array}{ccccc}{V}_{p1}={\mathrm{jZ}}_{05}{I}_{o2}& \left(12\right)& \mathrm{hence}& I_{o2}=\frac{V_{p1}}{{\mathrm{jZ}}_{05}}& \left(13\right)\\ I_{p1}={\mathrm{jV}}_{p2}/Z_{05}& \left(14\right)& \mathrm{hence}& V_{p2}=-{\mathrm{jZ}}_{05}{I}_{p1}& \left(15\right)\end{array}\mathrm{From}\left(3\right)\text{:}\{\begin{array}{ccccc}{V}_{p2}={\mathrm{jZ}}_{04}{I}_{o3}& \left(16\right)& \mathrm{hence}& I_{o3}=\frac{V_{p2}}{{\mathrm{jZ}}_{04}}& \left(17\right)\\ I_{o2}-{\mathrm{jI}}_{p2}={\mathrm{jV}}_p/Z_{04}& \left(18\right)& \mathrm{hence}& V_p=-{\mathrm{jZ}}_{04}\left(I_{o2}-{\mathrm{jI}}_{p2}\right)& \left(19\right)\end{array}\mathrm{From}\left(4\right)\text{:}\{\begin{array}{ccccc}{V}_p={\mathrm{jZ}}_{02}{I}_{o5}& \left(20\right)& \mathrm{hence}& I_{o5}=\frac{V_p}{{\mathrm{jZ}}_{02}}& \left(21\right)\\ I_{o4}={\mathrm{jV}}_{p3}/Z_{02}& \left(22\right)& \mathrm{hence}& V_{p3}=-{\mathrm{jZ}}_{02}{I}_{o4}& \left(23\right)\end{array}$

(23) The relationship between R.sub.L and R.sub.mF, which is the optimal load to be presented at the output of the main amplifier, can be determined under full power conditions. In this case, the total output power of the Doherty amplifier P.sub.o_tot can be computed using:

(24) $P_{o\_\mathrm{tot}}=\frac{V_{o\max }^2}{2R_L}=\frac{V_{\mathrm{mF}}^2}{2R_{\mathrm{mF}}}+\frac{V_{p1F}^2}{2R_{p1F}}+\frac{V_{p2F}^2}{2R_{p2F}}+\frac{V_{p3F}^2}{2R_{p3F}}\mathrm{in}\mathrm{which}{V}_{o\max }=V_{p3F}=V_{\mathrm{dd}}$

(25) wherein V.sub.o_max is the maximum voltage at the output, V.sub.mF the voltage at the output of the main amplifier under full power conditions, and V.sub.p1F, V.sub.p2F, V.sub.p3F the corresponding voltages at the first, second, and third peak amplifiers, and wherein R.sub.p1F, R.sub.p2F, R.sub.p3F the optimal load to be presented at the output of the first, second, and third peak amplifier, respectively, under full power conditions.

(26) As a single supply voltage and a power ration of 1:1:1:1 are assumed, the following holds:
R.sub.mF=R.sub.p1F=R.sub.p2F=R.sub.p3F

(27) and therefore:

(28) $\begin{array}{cc}\frac{R_{\mathrm{mF}}}{R_L}=4& \left(7\right)\end{array}$

(29) A linear dependency between I.sub.m and the RF input voltage v.sub.in is assumed. The main amplifier current at back-off (I.sub.mB) can therefore be expressed as I.sub.mB=kI.sub.mF, wherein k is the input voltage under back-off conditions at which maximum efficiency is achieved. Next, expressions for the impedance inverters will be derived.

(30) Substituting (9), (17), and (22) in (5) gives:

(31) $I_{o1}+I_{o3}-I_{o4}=0\left(5\right)\frac{V_m}{{\mathrm{jZ}}_{03}}+\frac{V_{p2}}{{\mathrm{jZ}}_{04}}-\frac{{\mathrm{jV}}_{p3}}{Z_{o2}}=0$

(32) Further substituting equation (15) gives:

(33) $\begin{array}{cc}\frac{V_m}{{\mathrm{jZ}}_{03}}-\frac{Z_{05}{I}_{p1}}{Z_{04}}-\frac{{\mathrm{jV}}_{p3}}{Z_{o2}}=0& \left(24\right)\end{array}$

(34) Substituting equation (21) in equation (6) gives:

(35) $\begin{array}{cc}{I}_{o5}+{\mathrm{jI}}_{p3}-\frac{V_{p3}}{R_L}=0\frac{V_p}{{\mathrm{jZ}}_{02}}+{\mathrm{jI}}_{p3}-\frac{V_{p3}}{R_L}=0& \left(25\right)\end{array}$

(36) Further substituting equation (11) provides:

(37) $\begin{array}{cc}\frac{-Z_{03}{I}_m}{{\mathrm{jZ}}_{02}}+{\mathrm{jI}}_{p3}-\frac{V_{p3}}{R_L}=0& \left(26\right)\end{array}$

(38) And from equation (26) it can be derived that:

(39) 0$\begin{array}{cc}{V}_{p3}={\mathrm{jR}}_L{I}_{p3}-\frac{Z_{03}{R}_L{I}_m}{{\mathrm{jZ}}_{02}}& \left(27\right)\end{array}$

(40) Substituting equation (27) in equation (24) gives:

(41) $\begin{array}{cc}\frac{V_m}{{\mathrm{jZ}}_{03}}-\frac{Z_{05}{I}_{p1}}{Z_{04}}+\frac{R_L{I}_{p3}}{Z_{02}}+\frac{Z_{03}{R}_L{I}_m}{Z_{02}^2}=0& \left(28\right)\end{array}$

(42) Evaluation of equation (28) at back-off and full power will provide the first relationships between the characteristic impedances of the impedance inverters.

(43) At the back-off point the following conditions apply:
V.sub.mB=jV.sub.dd, I.sub.mB=I.sub.mFk, I.sub.p1B=I.sub.p2B=I.sub.p3B=0

(44) Substituting in equation (28) provides:

(45) $\begin{array}{cc}\frac{V_{\mathrm{mB}}}{{\mathrm{jZ}}_{03}}-\frac{Z_{05}{I}_{p1B}}{Z_{04}}+\frac{R_L{I}_{p3B}}{Z_{02}}+\frac{Z_{03}{R}_L{I}_{\mathrm{mB}}}{Z_{02}^2}=0\frac{-{\mathrm{jV}}_{\mathrm{dd}}}{{\mathrm{jZ}}_{03}}+\frac{Z_{03}{R}_L{I}_{\mathrm{mF}}k}{Z_{02}^2}=0.Math.\frac{V_{\mathrm{dd}}}{Z_{03}}=\frac{Z_{03}{R}_L{I}_{\mathrm{mF}}k}{Z_{02}^2}.Math.\frac{V_{\mathrm{dd}}{Z}_{02}^2}{R_L{I}_{\mathrm{mF}}k}=Z_{03}^2.Math.\frac{Z_{03}}{Z_{02}}=\sqrt{\frac{R_{\mathrm{mF}}}{R_{L}k}}& \left(29\right)\end{array}$

(46) At full power, the following conditions apply:
V.sub.mF=jV.sub.dd, V.sub.p1F=V.sub.dd, V.sub.p2F=jV.sub.dd, V.sub.p3F=jV.sub.dd
I.sub.m=I.sub.mF, I.sub.p1=I.sub.p1F, I.sub.p2=I.sub.p2F, I.sub.p3=I.sub.p2F
Where it is assumed that:
I.sub.mF=I.sub.p1F=I.sub.p2F=I.sub.p2F

(47) Substituting in equation (28) gives:

(48) $\begin{array}{cc}\frac{V_{\mathrm{mF}}}{{\mathrm{jZ}}_{03}}-\frac{Z_{05}{I}_{p1F}}{Z_{04}}+\frac{R_L{I}_{p3F}}{Z_{02}}+\frac{Z_{03}{R}_L{I}_{\mathrm{mF}}}{Z_{02}^2}=0\frac{-{\mathrm{jV}}_{\mathrm{dd}}}{{\mathrm{jZ}}_{03}}-\frac{Z_{05}{I}_{\mathrm{mF}}}{Z_{04}}+\frac{R_L{I}_{\mathrm{mF}}}{Z_{02}}+\frac{Z_{03}{R}_L{I}_{\mathrm{mF}}}{Z_{02}^2}=0.Math.\frac{-V_{\mathrm{dd}}}{Z_{03}}=\frac{Z_{05}{I}_{\mathrm{mF}}}{Z_{04}}-\frac{R_L{I}_{\mathrm{mF}}}{Z_{02}}-\frac{Z_{03}{R}_L{I}_{\mathrm{mF}}}{Z_{02}^2}\frac{-R_{\mathrm{mF}}}{Z_{03}}=\frac{Z_{05}}{Z_{04}}-\frac{R_L}{Z_{02}}-\frac{Z_{03}{R}_L}{Z_{02}^2}.Math.\frac{Z_{05}}{Z_{04}}=\frac{R_L}{Z_{02}}+\frac{Z_{03}{R}_L}{Z_{02}^2}-\frac{R_{\mathrm{mF}}}{Z_{03}}& \left(30\right)\end{array}$

(49) Substituting equation (13) in equation (19) gives:

(50) $\begin{array}{cc}{V}_p=-{\mathrm{jZ}}_{04}\left(I_{o2}-{\mathrm{jI}}_{p2}\right)V_p=-{\mathrm{jZ}}_{04}\left(\frac{V_{p1}}{{\mathrm{jZ}}_{05}}-{\mathrm{jI}}_{p2}\right)& \left(31\right)\end{array}$

(51) Substituting equation (31) in equation (25) gives:

(52) $\begin{array}{cc}\frac{V_p}{{\mathrm{jZ}}_{02}}+{\mathrm{jI}}_{p3}-\frac{V_{p3}}{R_L}=0j\frac{Z_{04}{V}_{p1}}{Z_{02}{Z}_{05}}+j\frac{Z_{04}{I}_{p2}}{Z_{02}}+{\mathrm{jI}}_{p3}-\frac{V_{p3}}{R_L}=0& \left(32\right)\end{array}$

(53) At the back-off point the following conditions apply:
V.sub.mB=jV.sub.dd, I.sub.mB=I.sub.mFk, I.sub.p1B=I.sub.p2B=I.sub.p3B=0, V.sub.p3B=jbV.sub.dd

(54) wherein b is the back-off output voltage where maximum efficiency occurs. Substituting in equation (32) gives:

(55) $\begin{array}{cc}\frac{Z_{04}{V}_{p1B}}{Z_{02}{Z}_{05}}+j\frac{Z_{04}{I}_{p2B}}{Z_{02}}+{\mathrm{jI}}_{p3B}-\frac{V_{p3B}}{R_L}=0j\frac{Z_{04}{V}_{p1B}}{Z_{02}{Z}_{05}}-\frac{{\mathrm{jbV}}_{\mathrm{dd}}}{R_L}=0.Math.\frac{Z_{04}}{Z_{02}{Z}_{05}}=\frac{{\mathrm{bV}}_{\mathrm{dd}}}{V_{p1B}{R}_L}& \left(33\right)\end{array}$

(56) Substituting equations (11) and (13) in equation (19) gives:

(57) $\begin{array}{cc}{V}_p=-{\mathrm{jZ}}_{04}\left(I_{o2}-{\mathrm{jI}}_{p2}\right)-Z_{03}{I}_m=-{\mathrm{jZ}}_{04}\left(\frac{V_{p1}}{{\mathrm{jZ}}_{05}}-{\mathrm{jI}}_{p2}\right)& \left(34\right)\end{array}$

(58) At the back-off point the following conditions apply:
V.sub.mB=jV.sub.dd, I.sub.mB=I.sub.mFk, I.sub.p1B=I.sub.p2B=I.sub.p3B=0

(59) Substituting in equation (34) gives:

(60) $\begin{array}{cc}-Z_{03}{I}_{\mathrm{mB}}=-{\mathrm{jZ}}_{04}\left(\frac{V_{p1B}}{{\mathrm{jZ}}_{05}}-{\mathrm{jI}}_{p2B}\right)Z_{03}{I}_{\mathrm{mF}}k=\frac{Z_{04}{V}_{p1B}}{Z_{05}}.Math.V_{p1B}=\frac{Z_{03}{Z}_{05}}{Z_{04}}{I}_{\mathrm{mF}}k& \left(35\right)\end{array}$

(61) Substituting equation (35) in equation (33) provides:

(62) $\begin{array}{cc}\frac{Z_{04}}{Z_{02}{Z}_{05}}=\frac{{\mathrm{bV}}_{\mathrm{dd}}}{V_{p1B}{R}_L}\frac{Z_{04}}{Z_{02}{Z}_{05}}=\frac{{\mathrm{bV}}_{\mathrm{dd}}}{I_{\mathrm{mF}}{\mathrm{kR}}_L}\frac{Z_{04}}{Z_{03}{Z}_{05}}.Math.\frac{Z_{03}}{Z_{02}}=\frac{{\mathrm{bR}}_{\mathrm{mF}}}{{\mathrm{kR}}_L}& \left(36\right)\end{array}$

(63) Equating equations (29) and (36) gives:

(64) 0$\begin{array}{cc}\sqrt{\frac{R_{\mathrm{mF}}}{R_{L}k}}=\frac{{\mathrm{bR}}_{\mathrm{mF}}}{{\mathrm{kR}}_L}.Math.\frac{R_{\mathrm{mF}}}{R_{L}k}={\left(\frac{{\mathrm{bR}}_{\mathrm{mF}}}{{\mathrm{kR}}_L}\right)}^2.Math.1=\frac{b^2{R}_{\mathrm{mF}}}{{\mathrm{kR}}_L}.Math.k=\frac{b^2{R}_{\mathrm{mF}}}{R_L}& \left(38\right)\end{array}$

(65) At full power, the following conditions apply:
V.sub.mF=jV.sub.dd, V.sub.p1F=V.sub.dd, V.sub.p2F=jV.sub.dd, V.sub.p3F=jV.sub.dd
I.sub.m=I.sub.mF, I.sub.p1=I.sub.p1F, I.sub.p2=I.sub.p2F, I.sub.p3=I.sub.p2F
Assuming
I.sub.mF=I.sub.p1F=I.sub.p2F=I.sub.p2F

(66) Substituting in equation (34) gives:

(67) $\begin{array}{cc}-Z_{03}{I}_{\mathrm{mF}}=-{\mathrm{jZ}}_{04}\left(\frac{V_{p1F}}{{\mathrm{jZ}}_{05}}-{\mathrm{jI}}_{p2F}\right)-Z_{03}{I}_{\mathrm{mF}}=-{\mathrm{jZ}}_{04}\left(\frac{V_{\mathrm{dd}}}{{\mathrm{jZ}}_{05}}-{\mathrm{jI}}_{\mathrm{mF}}\right)Z_{03}{I}_{\mathrm{mF}}=\frac{V_{\mathrm{dd}}{Z}_{04}}{Z_{05}}+I_{\mathrm{mF}}{Z}_{04}.Math.Z_{03}=\frac{R_{\mathrm{mF}}{Z}_{04}}{Z_{05}}+Z_{04}.Math.Z_{04}=\frac{Z_{03}}{\frac{R_{\mathrm{mF}}}{Z_{05}}+1}& \left(39\right)\end{array}$

(68) Substituting equation (39) in equation (30) gives:

(69) $\frac{Z_{05}}{Z_{03}}\left(\frac{R_{\mathrm{mF}}}{Z_{05}}+1\right)=\frac{R_L}{Z_{02}}+\frac{Z_{03}{R}_L}{Z_{02}^2}-\frac{R_{\mathrm{mF}}}{Z_{03}}.Math.R_{\mathrm{mF}}+Z_{05}=\frac{R_L{Z}_{03}}{Z_{02}}+\frac{Z_{03}^2{R}_L}{Z_{02}^2}-R_{\mathrm{mF}}.Math.Z_{05}=\frac{R_L{Z}_{03}}{Z_{02}}+\frac{Z_{03}^2{R}_L}{Z_{02}^2}-2R_{\mathrm{mF}}$

(70) Substituting equation (29) gives an explicit expression for Z.sub.05:

(71) $\begin{array}{cc}{Z}_{05}=R_L\sqrt{\frac{R_{\mathrm{mF}}}{R_{L}k}}+R_L\frac{R_{\mathrm{mF}}}{R_{L}k}-2R_{\mathrm{mF}}{Z}_{05}=\sqrt{\frac{R_L{R}_{\mathrm{mF}}}{k}}+\frac{R_{\mathrm{mF}}}{k}-2R_{\mathrm{mF}}& \left(40\right)\end{array}$

(72) The design flow for combiner 4 can be described in the following manner. First, back-off output voltage b is chosen. When targeting at maximum efficiency at 9.5 dB back-off, b can be calculated using:

(73) $b={10}^{\frac{-9.5}{20}}=\frac{1}{3}$

(74) Choosing the relationship between R.sub.mF and R.sub.L:

(75) $\begin{array}{cc}\frac{R_{\mathrm{mF}}}{R_L}=4& \left(7\right)\end{array}$

(76) Allows k to be computed using:

(77) $\begin{array}{cc}k=\frac{b^2{R}_{\mathrm{mF}}}{R_L}& \left(38\right)\end{array}$

(78) Selecting a value for Z.sub.03 allows the remaining characteristic impedances to be calculated using:

(79) $\begin{array}{cc}{Z}_{02}=Z_{03}\sqrt{\frac{R_{L}k}{R_{\mathrm{mF}}}}& \left(29\right)\\ Z_{05}=\sqrt{\frac{R_L{R}_{\mathrm{mF}}}{k}}+\frac{R_{\mathrm{mF}}}{k}-2R_{\mathrm{mF}}& \left(40\right)\\ Z_{04}=\frac{Z_{04}}{\frac{R_{\mathrm{mF}}}{Z_{06}}+1}& \left(39\right)\end{array}$

(80) The load modulation (VSWR.sub.main) experienced by the main amplifier can be expressed as:

(81) $\begin{array}{cc}{\mathrm{VSWR}}_{\mathrm{main}}=\frac{R_{\mathrm{mB}}}{R_{\mathrm{mF}}}=\frac{V_{\mathrm{mB}}/I_{\mathrm{mB}}}{V_{\mathrm{mF}}\text{/}{I}_{\mathrm{mF}}}=\frac{V_{\mathrm{dd}}\text{/}\left(I_{\mathrm{mF}}k\right)}{V_{\mathrm{dd}}\text{/}{I}_{\mathrm{mF}}}{\mathrm{VSWR}}_{\mathrm{main}}=\frac{1}{k}& \left(43\right)\end{array}$

NUMERICAL EXAMPLE

(82) As a numerical example the following design parameters were set:

(83) R.sub.mF=1

(84) R.sub.L=

(85) Z.sub.03=1

(86) Back off for peak efficiency=BO=9.542 dB

(87) Using the equations above, the following characteristics can be computed:

(88) b=

(89) k= 4/9

(90) VSWR.sub.main=2.25

(91) Z.sub.02=

(92) Z.sub.05=1

(93) Z.sub.04=

(94) where the impedances were normalized using 50 Ohm. In other words, Z.sub.02=16.7 Ohm, Z.sub.03=50 Ohm, Z.sub.04=25 Ohm, and Z.sub.05=50 Ohm.

(95) The numerical example demonstrates that with the layout of the present invention, peak efficiencies can be reached at deep back-off levels without requiring a large load modulation for the main amplifier.

(96) FIG. 4 illustrates a schematic layout of an implementation of a Doherty amplifier in accordance with the present invention. Here, input distributing network 3 is realized using quadrature hybrid couplers H1-H3. Each of these couplers comprises an input port, a first output port that has a phase delay of about 0 degrees relative to the input port, a second output port that has a phase delay of about 90 degrees relative to the input port, and an isolated port that is terminated with the characteristic impedance that corresponds to the coupler, which in most cases equals 50 Ohm.

(97) The network of hybrid couplers introduces phase delays in the various branches. These phase delays should be matched with the phase delays introduced in Doherty combiner 4 such that the amplified signals combine in phase at first combining node N1.

(98) In addition, compared to FIG. 1, amplifiers M, P1, P2, P3 have been replaced with power transistors TM, TP1, TP2, TP3 that are not designed to provide optimal efficiency and/or power when implemented in a 50 Ohm environment. For that reason, input matching networks Zinx.sub.match and output matching networks Zoutx.sub.match are provided at the inputs and outputs of the power transistors, respectively, that provide the required impedance match to 50 Ohm. These matching networks generally act as impedance inverters as they introduce a phase delay that approximates 90 degrees. Hence, the inclusion of these matching networks needs to be compensated for. More in particular, comparing FIGS. 1 and 4, first branch b1 now comprises output match Zout3.sub.match, which introduces a phase delay of about 90 degrees. In FIG. 1, branch b1 does not, in itself, comprise impedance transforming elements other than a transmission line that introduces a phase delay equaling a multiple times 180 degrees. Therefore, to get the same phase response, a phase delay element Z.sub.01 having an electrical length of a 90 degrees is included in branch b1. Phase delay element Z.sub.01 could be realized using a quarter-wavelength transmission line with a characteristic impedance of 50 Ohm. The combination of power transistor TP3 and output matching network Zout3.sub.match behaves, at least at the output, as an amplifier that is designed to provide optimal performance when connected to a load of 50 Ohm, which amplifier is connected to a quarter-wavelength transmission line of 50 Ohm.

(99) On the other hand, impedance inverters Z.sub.03, Z.sub.05 from FIG. 1 have been replaced with output matching networks Zout3.sub.match and Zout5.sub.match, respectively. These matches already provide the required impedance inversion and phase delay. In the numerical example above, both Z.sub.03, Z.sub.05 were set/computed to be 50 Ohm. In other words, according to the numerical example, amplifiers M and P1 in FIG. 1 are connected to a 50 Ohm quarter-wavelength transmission line. However, power transistor TM combined with output matching network Zout0.sub.match and power transistor TP1 combined with output matching network Zout1.sub.match both behave as an amplifier that is designed for 50 Ohm and which is connected to a 50 Ohm quarter-wavelength transmission line. Additional components are therefore not required.

(100) If the numerical example resulted in any of the impedances Z.sub.03, Z.sub.05 being unequal to 50 Ohm, for example Z.sub.05 would have equaled 25 Ohm, the same output matching network Zout1.sub.match could have been used albeit in combination with a 50 Ohm quarter-wavelength transmission line and a 25 Ohm quarter-wavelength transmission line connected in series.

(101) By using the quadrature hybrid couplers, the input power is optimally distributed if each of the output ports of H2 and H3 is matched to 50 Ohm. This is achieved using the various input matching networks. The main purpose of distribution network 3 is to distribute the inputted power. Unlike Doherty combiner 4, load modulation is not, or not as much, required in distribution network 3.

(102) Branch b7 in FIG. 1 requires a phase delay of 270 degrees plus a multiple times 180 degrees. In FIG. 4, couplers H1 and H2 already introduce a 180 degrees phase delay in total. The missing 90 degrees is provided by input matching network Zin3.sub.match. Similar as above, the combination of input matching network Zin3.sub.match and TP3, which has not been designed to optimally perform when connected to a 50 Ohm environment at its input, behaves as an amplifier that has been designed to optimally perform in a 50 Ohm environment and which amplifier is connected to a 50 Ohm quarter-wavelength transmission line. Similar considerations hold for branches b9 and b10.

(103) In branch b8, couplers H1 and H2 already introduce a phase delay of 90 degrees, whereas FIG. 1 indicates that phase delay of 90 degrees plus a multiple of 180 degrees is required in total for branch b8. Here, input matching network Zin0.sub.match introduces an additional 90 degrees. For that reason, an additional quarter-wavelength is introduced by means of phase delay element Z.sub.09, which could be realized using a 50 Ohm quarter-wavelength transmission line.

(104) In the numerical example above, R.sub.L was set to , which corresponds to 12.5 Ohm. In the FIG. 4 implementation, impedance inverter Z.sub.OUT is realized using a quarter-wavelength transmission line having a characteristic impedance of 25 Ohm to provide a match to the 50 Ohm load of the Doherty amplifier.

(105) FIG. 5 illustrates the gain and efficiency of the amplifier in FIG. 4 as a function of output power for three distinct frequencies in a given communication band. Peak power is achieved at roughly 58.5 dBm and the efficiency peak under back-off conditions lies roughly at 51.5 dBm. This demonstrates that the present invention allows peak efficiencies to be obtained at deeper back-off levels than with conventional Doherty topologies.

(106) FIG. 6 illustrates possible die and package implementations to be used with the amplifier of the present invention. The power transistors TP3 and TM can be realized on a single semiconductor die 14. Moreover, this die can be placed in a package 16 that also includes at least part of the required input and output matching networks. In some embodiments, part of the matching networks is arranged on semiconductor die 14.

(107) Similar considerations hold for power transistors TP1 and TP2. They can also be realized on a single semiconductor die 15. This die can be placed in a package 17 that also includes at least part of the required input and output matching networks. In some embodiments, part of the matching networks is arranged on semiconductor die 15.

(108) The present invention does neither exclude embodiments wherein each power transistor is realized on a separate die, which die is mounted in a separate package, nor embodiments wherein all power transistors are realized on the same die.

(109) If an equal power capacity is used for the power transistors, substantially identical dies and packages can be used. This considerably reduces the costs of manufacturing.

(110) In the description above, electrical elements were presented that have a specific purpose. The skilled person in the art is aware that alternative elements may be used as long as these elements have the same purpose or display substantially the same electrical behavior. For example, a quarter-wavelength transmission line can be replaced by a pi-network as discussed above. The invention is therefore not limited to a particular implementation of a given electrical element.

(111) Moreover, the skilled person will understand that the scope of the present invention is not limited to the embodiments discussed here, but is defined by the appended claims and their equivalents.