High-sensitivity clocked comparator and method thereof

Abstract

A clocked comparator includes a first clocked transconductance amplifier configured to receive a first voltage signal and output a first current signal to an internal node in accordance with a clock; a clocked regenerative load configured to enable a second voltage signal at the internal node to self-regenerate in accordance with the clock; a SR (set-reset) latch configured to receive the second voltage signal at the internal node and output a third voltage signal; and a second clocked transconductance amplifier configured to receive the third voltage signal and output a second current signal to the internal node.

Claims

1. A clocked comparator comprising: a first clocked transconductance amplifier configured to receive a first voltage signal and output a first current signal to an internal node in accordance with a clock; a clocked regenerative load configured to enable a second voltage signal at the internal node to self-regenerate in accordance with the clock; a SR (set-reset) latch configured to receive the second voltage signal at the internal node and output a third voltage signal; and a second clocked transconductance amplifier configured to receive the third voltage signal and output a second current signal to the internal node.

2. The clocked comparator of claim 1, wherein the third voltage signal conforms to the same state of the second voltage signal when the second voltage is in a resolved state, and otherwise remains in a previous state.

3. The clocked comparator of claim 2, wherein the first clocked transconductance amplifier comprises a first clocked common-source amplifier configured to receive the first voltage signal and output a fourth voltage signal in accordance with the clock, and a first common-gate amplifier configured to receive the fourth voltage signal and output the first current signal.

4. The clocked comparator of claim 3, wherein the first common-gate amplifier is of a cross-coupling topology.

5. The clocked comparator of claim 4, wherein: the second clocked transconductance amplifier comprises a second clocked common-source amplifier configured to receive the third voltage signal and output a fifth voltage signal in accordance with the clock, and a second common-gate amplifier configured to receive the fifth voltage signal and output the second current signal.

6. The clocked comparator of claim 5, wherein the second common-gate amplifier is of a cross-coupling topology.

7. The clocked comparator of claim 6, wherein when the clock is in a first logical state, the first clocked common-source amplifier and the second clocked common-source amplifier are turned off, consequently turning off the first common-gate amplifier and the second common-gate amplifier and zeroing the first current signal and the second current signal, the clocked regenerative load is turned off, and the second voltage signal is reset to a null state.

8. The clocked comparator of claim 7, wherein upon a transition of the clock from the first logical state to a second logical state, the first clocked common-source amplifier and the second clocked common-source amplifier are turned on to develop the fourth voltage signal and the fifth voltage signal in accordance with the first voltage signal and the third voltage signal and consequently develop the first current signal and the second current signal via the first common-gate amplifier and the second common-gate amplifier, respectively, and the second voltage signal develops in accordance with the first current signal and the second current signal and self-regenerates into a resolved state.

9. The clocked comparator of claim 2, wherein the SR latch and the second clocked transconductance amplifier forms a negative feedback to help toggling a state of the third voltage signal upon the transition of the clock from a first logical state to a second logical state.

10. The clocked comparator of claim 9, wherein the first current signal and the second current signal are summed at the internal node with opposite polarity.

11. A method comprising: converting a first voltage signal into a first current signal directed to an internal node using a first clocked transconductance amplifier controlled by a clock; enabling a second voltage signal at the internal node to self-regenerate and develop into a resolved state using a clocked regenerative load controlled by the clock; imposing the resolved state of the second voltage signal onto a third voltage signal using a SR (set-reset) latch; and converting the third voltage signal into a second current signal directed to the internal node using a second clocked transconductance amplifier controlled by the clock.

12. The method of claim 11, wherein the third voltage signal conforms to the same state of the second voltage signal when the second voltage is in a resolved state, and otherwise remains in a previous state.

13. The method of claim 12, wherein the first clocked transconductance amplifier comprises a first clocked common-source amplifier configured to receive the first voltage signal and output a fourth voltage signal in accordance with the clock, and a first common-gate amplifier configured to receive the fourth voltage signal and output the first current signal.

14. The method of claim 13, wherein the first common-gate amplifier is of a cross-coupling topology.

15. The method of claim 14, wherein: the second clocked transconductance amplifier comprises a second clocked common-source amplifier configured to receive the third voltage signal and output a fifth voltage signal in accordance with the clock, and a second common-gate amplifier configured to receive the fifth voltage signal and output the second current signal.

16. The method of claim 15, wherein the second common-gate amplifier is of a cross-coupling topology.

17. The method of claim 16, wherein when the clock is in a first logical state, the first clocked common-source amplifier and the second clocked common-source amplifier are turned off, consequently turning off the first common-gate amplifier and the second common-gate amplifier and zeroing the first current signal and the second current signal, the clocked regenerative load is turned off, and the second voltage signal is reset to a null state.

18. The method of claim 17, wherein upon a transition of the clock from the first logical state to a second logical state, the first clocked common-source amplifier and the second clocked common-source amplifier are turned on to develop the fourth voltage signal and the fifth voltage signal in accordance with the first voltage signal and the third voltage signal and consequently develop the first current signal and the second current signal via the first common-gate amplifier and the second common-gate amplifier, respectively, and the second voltage signal develops in accordance with the first current signal and the second current signal and self-regenerates into a resolved state.

19. The method of claim 12, wherein the SR latch and the second clocked transconductance amplifier forms a negative feedback to help toggling a state of the third voltage signal upon the transition of the clock from a first logical state to a second logical state.

20. The method of claim 19, wherein the first current signal and the second current signal are summed at the internal node with opposite polarity.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 shows a schematic diagram of a prior art clocked comparator.

(2) FIG. 2 shows a schematic diagram of a clocked comparator in accordance with an embodiment of the present disclosure.

(3) FIG. 3 shows a flow diagram of a method in accordance with an embodiment of the present disclosure.

DETAILED DESCRIPTION OF THIS DISCLOSURE

(4) The present disclosure is directed to clocked comparator circuits and methods. While the specification describes several example embodiments of the disclosure considered favorable modes of practicing the invention, it should be understood that the invention can be implemented in many ways and is not limited to the particular examples described below or to the particular manner in which any features of such examples are implemented. In other instances, well-known details are not shown or described to avoid obscuring aspects of the disclosure.

(5) Persons of ordinary skill in the art understand terms and basic concepts related to microelectronics that are used in this disclosure, such as voltage, current, node, signal, clock, comparator, clocked comparator, CMOS (complementary metal oxide semiconductor), NMOS (N-channel metal oxide semiconductor) transistor, PMOS (N-channel metal oxide semiconductor) transistor, single-ended signal, differential signal, differential pair, pseudo-differential pair, latch, inverter, SR (set-reset) latch common-source amplifier, common-gate amplifier, transconductance amplifier, logical signal, inverter, pull up, and pull down. Terms like these are used in a context of microelectronics, and the associated concepts are apparent to those of ordinary skills in the art and thus will not be explained in detail here. Those of ordinary skill in the art can also recognize a symbol of a NMOS transistor and a symbol of a PMOS transistor and identify the source, the gate, and the drain terminals thereof. Those of ordinary skills in the art also can read schematics of a circuit comprising NMOS transistors and/or PMOS transistors without the need of a verbose description about how one transistor connects with another in the schematics. Those of ordinary skills in the art also understand units such as micron and nanometer.

(6) This present disclosure is disclosed in an engineering sense (e.g., from the perspective of one having ordinary skill in the art). For instance, X is equal to Y means a difference between X and Y is smaller than a specified engineering tolerance; X is much smaller than Y means X divided by Y is smaller than an engineering tolerance; and X is zero means X is smaller than a specified engineering tolerance.

(7) In this disclosure, a signal is either a voltage or a current that represents an information.

(8) A clock signal (or simply a clock) is a logical signal that cyclically toggles between a low state and a high state.

(9) Throughout this disclosure, V.sub.DD denotes a power supply node. For convenience, V.sub.DD can also refer to a power supply voltage provided at the power supply node. That is, V.sub.DD is 0.9V means a power supply voltage at the power supply node V.sub.DD is 0.9V. By way of example but not limitation, throughout this disclosure a circuit is fabricated using a 28 nm CMOS (complementary metal oxide semiconductor) process and V.sub.DD is 0.9V.

(10) Throughout this disclosure, a differential signaling scheme is used. A differential voltage signal comprises two single-ended voltage signals denoted with suffixes + and , respectively, attached in subscript, and a value of the differential voltage signal is represented by a difference between said two single-ended voltages. For instance, V.sub.1 (V.sub.2, V.sub.3, V.sub.4, V.sub.5, V.sub.6) comprises V.sub.1+ (V.sub.2+, V.sub.3+, V.sub.4+, V.sub.5+, V.sub.6+) and V.sub.1 (V.sub.2, V.sub.3, V.sub.4, V.sub.5, V.sub.6) and a value of V.sub.1 (V.sub.2, V.sub.3, V.sub.4, V.sub.5, V.sub.6) is represented by a difference between V.sub.1+ (V.sub.2+, V.sub.3+, V.sub.4+, V.sub.5+, V.sub.6+) and V.sub.1 (V.sub.2, V.sub.3, V.sub.4, V.sub.5, V.sub.6). Likewise, a differential current signal comprises two currents denoted with suffixes + and , respectively, attached in subscript. For instance, I.sub.1 (I.sub.2) comprises I.sub.1+ (I.sub.2+) and I.sub.1 (I.sub.2) and a value of I.sub.1 (I.sub.2) is represented by a difference between I.sub.1+ (I.sub.2+) and I.sub.1 (I.sub.2). A circuit node pertaining to a differential voltage signal comprises two nodes denoted with suffixes + and , respectively, attached in subscript. For instance, circuit node 201 comprises nodes 201.sub.+ and 201.sub..

(11) A single-ended logical signal is a single-ended voltage signal of two possible states: a high state and a low state. A single-ended logical signal is said to be in the high (low) state when a level of said single-ended logical signal is above (below) a certain trip point pertaining to said single-ended logical signal. When we state that (the single-ended logical signal) X is high, we are stating it in a context of logical signal and what we mean is: X is in the high state. When we state that (the single-ended logical signal) X is low, we are stating it in a context of logical signal and what we mean is: X is in the low state. The high state is also known as the 1 state, and the low state is also known as the 0 state. When we state that (the single-ended logical signal) X is 1, we are stating it in a context of logical signal and what we mean is: X is in the high state. Likewise, when we state that (the single-ended logical signal) X is 0, we are stating it in a context of logical signal and what we mean is: X is in the low state.

(12) A differential logical signal is made up of two single-ended logical signals including a first single-ended logical signal and a second single-ended logical signal and has three possible states: a 1 state, when the first single-ended logical signal is 1 and the second single-ended logical signal is 0; a 0 state, when the first single-ended logical signal is 0 and the second single-ended logical signal is 1; and a null state, when the first single-ended logical signal and the second single-ended signal are of the same state, either 1 or 0. The null state is an unresolved state, while both the 1 state and the 0 state are a resolved state.

(13) For brevity, a signal, voltage or current, is simply referred to as a signal without explicitly specifying whether it is differential or single-ended if it is obvious to those of ordinary skill in the art from the context.

(14) A PMOS (NMOS) transistor pair comprises a first PMOS (NMOS) transistor and a second PMOS (NMOS) transistor. The PMOS (NMOS) transistor pair is said to be cross-coupling if the drain of the first PMOS (NMOS) transistor connects to the gate of the second PMOS (NMOS) transistor, while the drain of the second PMOS (NMOS) transistor connects to the gate of the first PMOS (NMOS) transistor. A PMOS (NMOS) transistor pair configured in a cross-coupling topology exhibits a regenerative nature, as a positive feedback loop is formed.

(15) A schematic diagram of a clocked comparator 200 in accordance with an embodiment of the present disclosure is shown in FIG. 2. Clocked comparator 200 comprises: a first clocked transconductance amplifier CTA1 configured to receive a first voltage signal V.sub.1 and output a first current signal I.sub.1 to an internal node 201, at which a second voltage signal V.sub.2 is established, in accordance with a clock V.sub.CK; a clocked regenerative load CRL configured to provide a regenerative load at the internal node 201 in accordance with the clock V.sub.CK; a SR (set-reset) latch SRL configured to receive the second voltage signal V.sub.2 from the internal node 201 and output a third voltage signal V.sub.3; and a second clocked transconductance amplifier CTA2 configured to receive the third voltage signal V.sub.3 and output a second current signal I.sub.2 to the internal node 201. When the clock V.sub.CK is low, the first clocked transconductance amplifier CTA1 and the second clocked transconductance amplifier CTA2 are in a reset state, wherein I.sub.1 and I.sub.2 are all reset to zero, V.sub.2 is reset to null, and V.sub.3 is latched at a previous state. Upon a low-to-high transition of the clock V.sub.CK, the first clocked transconductance amplifier CTA1 outputs I.sub.1 in accordance with V.sub.1, the second clocked transconductance amplifier CTA2 outputs I.sub.2 in accordance with V.sub.3, the clocked regenerative load CRL enables V.sub.2 to self-regenerate into a resolved state in accordance with a sum of I.sub.1 and I.sub.2, and the SR latch SRL latches V.sub.2 into V.sub.3 once V.sub.2 develops into the resolved state.

(16) The first clocked transconductance amplifier CTA1 comprises a first clocked common-source amplifier CCSA1 configured to receive the first voltage signal V.sub.1 and output a fourth voltage signal V.sub.4 in accordance with the clock V.sub.CK, and a first common-gate amplifier CGA1 configured to receive the fourth voltage signal V.sub.4 and output the first current signal I.sub.1 to the internal node 201. The second clocked transconductance amplifier CTA2 comprises a second clocked common-source amplifier CCSA2 configured to receive the third voltage signal V.sub.3 and output a fifth voltage signal V.sub.5 in accordance with the clock V.sub.CK, and a second common-gate amplifier CGA2 configured to receive the fifth voltage signal V.sub.5 and output the second current signal I.sub.2 to the internal node 201. For brevity, hereafter the first clocked transconductance amplifier CTA1 is simply referred to as CTA1, the second clocked transconductance amplifier CTA2 is simply referred to as CTA2, the first clocked common-source amplifier CCSA1 is simply referred to as CCSA1, the second clocked common-source amplifier CCSA2 is simply referred to as CCSA2, the first common-gate amplifier CGA1 is simply referred to as CGA1, the second common-gate amplifier CGA2 is simply referred to as CGA2, the clocked regenerative load CRL is simply referred to as CRL, the SR latch SRL is simply referred to as SRL, the first (second, third, fourth, fifth) voltage signal V.sub.1 (V.sub.2, V.sub.3, V.sub.4, V.sub.5) is simply referred to as V.sub.1 (V.sub.2, V.sub.3, V.sub.4, V.sub.5), and the first (second) current signal I.sub.1 (I.sub.2) is simply referred to as I.sub.1 (I.sub.2). From the context of FIG. 2, it is understood by those of ordinary skill in the art that V.sub.1, V.sub.2, V.sub.3, V.sub.4, V.sub.5, I.sub.1, and I.sub.2 are all differential signals and thus the term differential is dropped herein for brevity.

(17) The clocked comparator 200 works in a two-phase manner in accordance with the clock V.sub.CK. When the clock V.sub.CK is low, the clocked comparator 200 is in a frozen phase, wherein V.sub.2, which is a differential logical signal, is reset to a null state and V.sub.3, which is also a differential logical signal, is latched to a previous state. Upon a low-to-high transition of the clock V.sub.CK, the clocked comparator 200 enters in a resolving phase, wherein V.sub.2 is resolved and changes from the null state into either the 1 state or the 0 state in accordance with a sign of V.sub.1, and then the state of V.sub.2 is latched into a present state of V.sub.3. In the resolving phase, once V.sub.2 is resolved, V.sub.2 represents a decision of a sign of V.sub.1, which is either 1 (if V.sub.2+ is high and V.sub.2 is low, indicating the sign of V.sub.1 is positive) or 0 (if V.sub.2+ is low and V.sub.2 is high, indicating the sign of V.sub.1 is negative). Note that when both V.sub.2+ and V.sub.2 are high, V.sub.2 is in an unresolved state. After V.sub.2 is resolved to either the 1 or the 0 state, the state will be loaded into a state of V.sub.3 by SRL.

(18) CCSA1 comprises NMOS transistors 211, 213, and 214, and PMOS transistors 215 and 216. NMOS transistors 213 and 214 form a differential pair, which is biased via NMOS transistor 211 controlled by the clock V.sub.CK, and are configured to receive V.sub.1+ and V.sub.1 and output V.sub.4 and V.sub.4+, respectively. CGA1 comprises NMOS transistors 217 and 218 configured in a cross-coupling topology to receive V.sub.4 and V.sub.4+ and output I.sub.1 and I.sub.1+ to nodes 201.sub. and 201.sub.+, respectively. When the clock V.sub.CK is low, NMOS transistor 211 is turned off, causing NMOS transistors 213 and 214 to be turned off and allowing PMOS transistors 215 and 216 to pull up V.sub.4 and V.sub.4+, respectively, to V.sub.DD without resistance, and consequently NMOS transistors 217 and 218 are also turned off. Upon a low-to-high transition of the clock V.sub.CK, NMOS transistor 211 is turned on and PMOS transistors 215 and 216 are turned off, allowing the differential pair formed by NMOS transistors 213 and 214 to pull down V.sub.4 and V.sub.4+ in accordance with V.sub.1+ and V.sub.1, respectively: if V.sub.1+ is higher than V.sub.1, V.sub.4 will fall down faster than V.sub.4+ and causes I.sub.1 to be greater than I.sub.1+, otherwise V.sub.4+ will fall down faster than V.sub.4 and causes I.sub.1+ to be greater than I.sub.1.

(19) Verbose descriptions regarding connections among circuit elements and/or signals in FIG. 2 such as the source, the gate, and the drain of PMOS transistor 215 connect to V.sub.DD, V.sub.CK, and V.sub.4 are omitted since they are understood to those of ordinary skill in the art.

(20) CCSA2 comprises NMOS transistors 221, 223, and 224. NMOS transistors 223 and 214 form a differential pair, which is biased via NMOS transistor 221 controlled by the clock V.sub.CK, and are configured to receive V.sub.3 and V.sub.3+ and output V.sub.5+ and V.sub.5, respectively. CGA2 comprises NMOS transistors 225 and 226 configured in a cross-coupling topology to receive V.sub.5+ and V.sub.5 and output I.sub.2+ and I.sub.2 to nodes 201.sub. and 201.sub.+, respectively. When the clock V.sub.CK is low, NMOS transistor 221 is turned off, causing NMOS transistors 223 and 224 to be turned off and consequently NMOS transistors 225 and 226 are also turned off. Upon a low-to-high transition of the clock V.sub.CK, NMOS transistor 221 is turned on, allowing the differential pair formed by NMOS transistors 223 and 224 to pull down V.sub.5+ and V.sub.5 in accordance with V.sub.3 and V.sub.3+, respectively: if V.sub.3 is higher than V.sub.3+, V.sub.5+ will fall down faster than V.sub.5 and cause I.sub.2+ to be greater than I.sub.2, otherwise V.sub.5 will fall down faster than V.sub.5+ and cause I.sub.2 to be greater than I.sub.2+.

(21) CRL comprises PMOS transistors 251, 252, 253, and 254. PMOS transistors 251 and 252 are configured in a cross-coupling topology to provide a regenerative load across nodes 201.sub.+ and 201.sub.. PMOS transistors 253 and 254 are controlled by the clock V.sub.CK. When the clock V.sub.CK is low, V.sub.2 and V.sub.2+ are pulled up to V.sub.DD by PMOS transistors 253 and 254, respectively, causing PMOS transistors 251 and 252 to be turned off. In the meanwhile, I.sub.1+, I.sub.1, I.sub.2+, and I.sub.2 are zero because NMOS transistors 217, 218, 225, and 226 are turned off, as explained earlier. Upon a low-to-high transition of the clock V.sub.CK, PMOS transistors 253 and 254 are turned off, V.sub.4, V.sub.4+, V.sub.5+, and V.sub.5 starts falling down, causing I.sub.1+, I.sub.1, I.sub.2+, and I.sub.2 to rise and both V.sub.2 and V.sub.2+ to fall down. If I.sub.1+I.sub.2+ is greater than I.sub.1++I.sub.2, V.sub.2 will fall faster than V.sub.2+, and once falling sufficiently low it will turn off NMOS transistors 218 and 226, thus shutting off I.sub.1+ and I.sub.2 and prevent V.sub.2+ to fall; eventually, V.sub.2 will fall to nearly ground and at the same time pull up V.sub.2+ to nearly V.sub.DD via PMOS transistor 252. On the other hand, if I.sub.1++I.sub.2 is greater than I.sub.1+I.sub.2+, V.sub.2+ will fall faster than V.sub.2, and once falling sufficiently low it will turn off NMOS transistors 217 and 225, thus shutting off I.sub.1 and I.sub.2+ and prevent V.sub.2 to fall; eventually, V.sub.2+ will fall to nearly ground and at the same time pull up V.sub.2 to nearly V.sub.DD via PMOS transistor 251. A resolved state of V.sub.2 of either 1 (V.sub.2+ is high and V.sub.2 is low) or 0 (V.sub.2+ is low and V.sub.2 is high) thus emerges, and it's determined by which of the two currents, I.sub.1+I.sub.2+ and I.sub.1++I.sub.2, is greater upon the low-to-high transition of the clock V.sub.CK. Once the state of V.sub.2 is resolved, it is latched into a state of V.sub.3 by SRL.

(22) SRL comprises an inverter pair comprising a first inverter made up of NMOS transistor 263 and PMOS transistor 265 and a second inverter made up of NMOS transistor 264 and PMOS transistor 266; a first pseudo-differential pair comprising NMOS transistors 261 and 262; and a cross-coupling pair comprising PMOS transistors 267 and 268. The inverter pair receives V.sub.2 and output a sixth voltage signal V.sub.6 (which is a differential logical signal comprising V.sub.6+ and V.sub.6). The first pseudo-differential pair made up of NMOS transistors 261 and 262 receives the sixth voltage signal V.sub.6 and outputs V.sub.3. The cross-coupling pair made up of PMOS transistors 267 and 268 is used to latch a state of V.sub.3. If the state of V.sub.2 is 1, the sixth voltage signal V.sub.6 will be 1 (i.e. V.sub.6+ is high and V.sub.6 is low), and V.sub.3 will be latched to 1. If the state of V.sub.2 is 0, the sixth voltage signal V.sub.6 will be 0 (i.e. V.sub.6+ is low and V.sub.6 is high), and the state of V.sub.3 will be latched to 0. In a further embodiment, SRL further comprises a second pseudo-differential pair comprising PMOS transistors 269 and 270 configured to receive V.sub.2 and outputs V.sub.3 jointly with the first pseudo-differential pair made up of NMOS transistors 261 and 262. This further embodiment can increase a speed of SRL, as the second pseudo-differential pair can directly impose a resolved state of V.sub.2 onto V.sub.3.

(23) If CTA2 were removed, clocked comparator 200 is not much different from the prior art clocked comparator 100 of FIG. 1. With the inclusion CTA2, however, the hysteresis issue in the prior art clocked comparator 100 mentioned earlier is advantageously alleviated. Upon a low-to-high transition of the clock V.sub.CK, CTA1 outputs I.sub.1 in accordance with V.sub.1 to resolve V.sub.2, while CTA2 outputs I.sub.2 in accordance with V.sub.3 to participate in the resolving of V.sub.2, wherein V.sub.3 is a previous resolved state of V.sub.2 as latched by SRL. However, I.sub.2 is summed with I.sub.1 with an opposite polarity (since I.sub.2 is summed with I.sub.1+ at node 201.sub.+, while I.sub.2+ is summed with I.sub.1 at node 2014, and CTA2 and SRL forms a negative feedback. If V.sub.3 is 1, I.sub.2 will be negative (i.e. I.sub.2 is greater than I.sub.2+) and helping to resolve V.sub.2 into 0 (i.e. V.sub.2+ is low and V.sub.2 is low) and consequently toggle V.sub.3 to 1. On the other hand, if V.sub.3 is 0, I.sub.2 will be positive (i.e. I.sub.2+ is greater than I.sub.2) and helping to resolve V.sub.2 into 1 (i.e. V.sub.2+ is high and V.sub.2 is low) and consequently toggle V.sub.3 to 0. The hysteresis makes it harder for V.sub.3 to toggle, while the negative feedback makes it easier for V.sub.3 to toggle. The hysteresis issue is thus alleviated.

(24) Caution must be taken, however, about using CTA2, which is used to alleviate hysteresis of CTA1 when |V.sub.1+V.sub.1| is small but should not dominate over CTA1 when |V.sub.1+V.sub.1| is large. To prevent CTA2 from dominating over CTA1, a transconductance of CTA2 must be smaller than a transconductance of CTA1.

(25) By way of example but not limitation: the dimensions are devices in FIG. 2 are shown in the following table.

(26) TABLE-US-00001 Width Length Devices (in microns) (in nanometers) NMOS transistor 211 2.88 30 NMOS transistors 213 & 214 3.84 30 PMOS transistors 215 & 216 0.48 30 NMOS transistors 217 & 218 3.84 30 NMOS transistor 221 0.48 30 NMOS transistors 223 & 224 0.24 30 NMOS transistors 225 & 226 0.12 30 PMOS transistors 251, 252, 253, & 254 1.92 30 NMOS transistors 263 & 264 0.12 30 PMOS transistors 265 & 266 0.72 30 NMOS transistors 261 & 262 0.36 30 PMOS transistors 267 & 268 0.12 30 PMOS transistors 269 & 270 0.48 30

(27) It is clear that width-to-length ratios of transistors in CTA2 are smaller than those in CTA1. This way, a transconductance of CTA2 is smaller than a transconductance of CTA1, and therefore CTA2 will not dominate over CTA1.

(28) As shown in a flow diagram depicted in FIG. 3, a method in accordance with an embodiment of the present disclosure comprises the following steps: (step 310) converting a first voltage signal into a first current signal directed to an internal node using a first clocked transconductance amplifier controlled by a clock; (step 320) enabling a second voltage signal at the internal node to self-regenerate and develop into a resolved state using a clocked regenerative load controlled by the clock; (step 330) imposing the resolved state of the second voltage signal onto a third voltage signal using a SR (set-reset) latch; and (step 340) converting the third voltage signal into a second current signal directed to the internal node using a second clocked transconductance amplifier controlled by the clock.

(29) This present disclosure can be very useful in a high-speed serial link receiver, wherein a decision must be resolved within a very short period and thus often highly hindered by hysteresis.

(30) Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the disclosure. Accordingly, the above disclosure should not be construed as limited only by the metes and bounds of the appended claims.