Latched comparator and analog-to-digital converter making use thereof

Abstract

A latched comparator comprises a pre-amplifier stage with a positive input (V.sub.in,p), a negative input (V.sub.in,n); and a differential output (V.sub.out) comprising a first output (V.sub.out,1) and a second output (V.sub.out,2), the pre-amplifier stage comprising a first cascode pair, comprising a first amplifying transistor (MN2) and a first cascode transistor (MN4) connected at a first cascode node, the first amplifying transistor (MN2) being controlled by the positive input (V.sub.in,p) and the first cascode transistor (MN4) being connected, opposite to the first cascode node, to the first output (V.sub.out,1); a second cascode pair, comprising a second amplifying transistor (MN3) and a second cascode transistor (MN5) connected at a second cascode node, the second amplifying transistor (MN3) being controlled by the negative input (V.sub.in,n) and the second cascode transistor (MN5) being connected, opposite to the second cascode node, to the second output (V.sub.out,2); a first gain-boosting transistor (MN6) connected between the first output (V.sub.out,1) and the first cascode node; and a second gain-boosting transistor (MN7) connected between the second output (V.sub.out,2) and the second cascode node, wherein the first gain-boosting transistor (MN6) and the second gain-boosting transistor (MN7) are cross-coupled, so that the first gain-boosting transistor (MN6) is controlled by the second output (V.sub.out,2) and the second gain-boosting transistor (MN7) is controlled by the first output (V.sub.out,2).

Claims

1. A latched comparator comprising a pre-amplifier stage with: a positive input, a negative input; and a differential output comprising a first output and a second output, said pre-amplifier stage comprising: a first cascode pair, comprising a first amplifying transistor and a first cascode transistor connected at a first cascode node, said first amplifying transistor being controlled by said positive input and said first cascode transistor being connected, opposite to said first cascode node, to said first output; a second cascode pair, comprising a second amplifying transistor and a second cascode transistor connected at a second cascode node, said second amplifying transistor being controlled by said negative input and said second cascode transistor being connected, opposite to said second cascode node, to said second output; a first gain-boosting transistor connected between said first output and said first cascode node; and a second gain-boosting transistor connected between said second output and said second cascode node, wherein said first gain-boosting transistor and said second gain-boosting transistor are cross-coupled, so that said first gain-boosting transistor is controlled by said second output and said second gain-boosting transistor is controlled by said first output.

2. The latched comparator of claim 1, controlled by a clock signal and supplied by a supply voltage.

3. The latched comparator of claim 1 wherein said first cascode transistor and said second cascode transistor each are controlled by a common-mode voltage.

4. The latched comparator of claim 2, wherein said first cascode transistor and said second cascode transistor each are controlled by said supply voltage.

5. The latched comparator of claim 1, wherein said first amplifying transistor, said second amplifying transistor, said first cascode transistor, and said second cascode transistor are NMOS transistors.

6. The latched comparator of claim 2, further comprising a block pulling said first output and said second output towards said supply voltage absent said clock signal, said block preferably comprising a first, preferably PMOS, transistor and a second, preferably PMOS, transistor, each controlled by said clock signal and connected between said supply voltage and, respectively, said first output and said second output.

7. The latched comparator of claim 2, further comprising a block pulling said first amplifying transistor opposite to said first cascode node and said second amplifying transistor opposite to said second cascode node towards ground when said clock signal is present, said block preferably comprising an NMOS transistor connected between ground and said first amplifying transistor and said second amplifying transistor, said NMOS transistor being controlled by said clock signal.

8. The latched comparator of claim 2, further comprising a block pulling said first cascode node and said second cascode node towards said supply voltage absent said clock signal, said block preferably comprising a first, preferably PMOS, transistor and a second, preferably PMOS, transistor, each connected between said supply voltage and, respectively, said first cascode node and said second cascode node and controlled by said clock signal.

9. The latched comparator of claim 1, further comprising a latch stage, configured to receive the differential output from the pre-amplifier stage.

10. An analog-to-digital converter, comprising: the latched comparator of claim 1, wherein the analog-to-digital converter is configured to provide an analog signal to be converted and a reference signal on, respectively, the positive input and the negative input of the latched comparator.

11. The analog-to-digital converter of claim 10, wherein the analog-to-digital converter is a successive approximation register analog-to-digital converter.

12. A biomedical sensor device comprising the analog-to-digital converter of claim 10.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The above, as well as additional objects, features and advantages of the present inventive concept, will be better understood through the following illustrative and non-limiting detailed description, with reference to the appended drawings. In the drawings like reference numerals will be used for like elements unless stated otherwise.

(2) FIG. 1 is a schematic showing a latched comparator according to the present inventive concept, where the cascode transistors are controlled by the supply voltage.

(3) FIG. 2 is a schematic showing a latched comparator not according to the present inventive concept, as a comparison.

(4) FIG. 3 shows simulated transient behavior of the latched comparator of FIG. 2.

(5) FIG. 4 shows simulated transient behavior of the latched comparator of FIG. 1.

DETAILED DESCRIPTION

(6) FIG. 1 shows a schematic of a latched comparator 2 according to the present inventive concept.

(7) The latched comparator comprises a pre-amplifier stage 4. The pre-amplifier stage 4 has a positive input V.sub.in,p and a negative input V.sub.in,n, suitable for, when used in an ADC, respectively, an analog voltage that is to be digitized and a reference voltage to which, as part of the digitization procedure, the analog voltage is to be compared. Further, the pre-amplifier stage 4 has differential output comprising a first output V.sub.out,1 and a second output V.sub.out,2.

(8) The circuitry of the latched comparator 2 may be powered by a supply voltage V.sub.dd and controlled by a clock signal V.sub.clk. The clock signal V.sub.clk then controls the pacing of comparison, having a leading edge of a positive pulse at the start of each comparison and being at ground potential between comparisons.

(9) The latched comparator 4 comprises an amplifying block 14 comprising a first 8 and a second cascode pair 10 and a first gain-boosting transistor MN6 and a second gain-boosting transistor MN7. The first cascode pair 8 comprises a first amplifying transistor MN2 and a first cascode transistor MN4. The second cascode pair 10 comprises a second amplifying transistor MN3 and a second cascode transistor MN5. In the depicted embodiment, MN2, MN3, MN4, MN5, MN6, and MN7 are NMOS transistors.

(10) The gate terminals of the cascode transistors MN4 and MN5 may be connected to the supply voltage V.sub.dd. Alternatively, they may be connected to a common-mode voltage V.sub.cm, which may be generated in a conventional way by buffering a mid-supply. The supply voltage V.sub.dd or the common-mode voltage V.sub.cm thus controls transistors MN4 and MN5.

(11) In either case, during operation of the pre-amplifier stage, the cascode transistors MN4 and MN5 will be in a saturated permanently conducting stage between source and drain. The drain terminals of MN4 and MN5 are connected to, respectively, the first output V.sub.out,1 and the second output V.sub.out,2, while the opposite source terminals are connected to, respectively, a first cascode node 20 and a second cascode node 22.

(12) The gate terminals of the amplifying transistors MN2 and MN3 are connected, respectively, to the positive input V.sub.in,p and the negative input V.sub.in,n, those inputs thereby controlling the respective transistors, while the drain terminals are connected to, respectively the first cascode node 20 and the second cascode node 22. Typically, to provide a high gain, the amplifying transistors MN2 and MN3 work in weak-inversion.

(13) The first gain-boosting transistor MN6 is connected at its drain terminal to the first output V.sub.out,1 and at its source terminal to the first cascode node 20. Thus, it is connected in parallel to the cascode transistor MN4.

(14) Similarly, the second gain-boosting transistor MN7 is connected at its drain terminal to the second output V.sub.out,2 and at its source terminal to the second cascode node 20. Thus, it is connected in parallel to the cascode transistor MN5.

(15) The first gain-boosting transistor MN6 and the second gain-boosting transistor MN7 are cross-coupled in the sense that the first output V.sub.out,1 is connected to the gate terminal of the second gain-boosting transistor MN7, while the second output V.sub.out,2 is connected to the gate terminal of the first gain-boosting transistor V.sub.out,1. Thus, the first output V.sub.out,1 controls the second gain-boosting transistor, while the second output V.sub.out,2 controls the first gain-boosting transistor. This positive feedback structure provides a gain boost for the pre-amplifier stage 4. However, it is not used as a latch. To achieve a high gain of the pre-amplifier stage, the transconductance of transistors MN6 and MN7 needs to be small (see below). Therefore, the positive feedback structure does not have enough loop gain to work as a latch.

(16) Further, the latched comparator 4 may comprise a block 12 comprising PMOS transistors MP1 and MP2, to the respective gate terminals of which the clock signal V.sub.clk is connected, the clock signal V.sub.clk thus controlling transistors MP1 and MP2. Further, to the drain terminals of each of MP1 and MP2, the supply voltage V.sub.dd is connected. The source terminals of MP1 and MP2 are connected, respectively, to the outputs V.sub.out,1 and V.sub.out,2. When the clock signal V.sub.clk is in a low state, i.e., absent, the transistors MP1 and MP2 will become conductive between drain and source in a saturated state, pulling the respective output voltages V.sub.out,1 and V.sub.out,2 towards the supply voltage V.sub.dd, pre-charging them ahead of the next comparison. This pulling will cease as the clock signal V.sub.clk goes to a high state at the start of a comparison, as the transistors MP1 and MP2 will cease to be conductive between drain and source, but ensures that each comparison starts at a well-defined state with respect to V.sub.out,1 and V.sub.out,2, avoiding hysteresis.

(17) Further, the pre-amplifier stage 4 may comprise a block 16 comprising a single NMOS transistor MN1, wherein a source terminal of the transistor MN1 is connected to ground, a drain terminal of the transistor MN1 is connected to each of the drain terminals of cascode transistors MN2 and MN3, and a gate terminal of the transistor MN1 is connected to the clock signal V.sub.clk. When the clock signal goes high at the start of a comparison, MN1 will become conductive between source and drain, thus pulling the drain terminals, i.e., the terminals opposite the cascode nodes 20 and 22, of the cascode transistors MN2 and MN3 towards ground.

(18) Further, the pre-amplifier stage 4 may comprise a block 18 comprising two PMOS transistors MP3 and MP4, to the respective gate terminals of which the clock signal V.sub.clk is connected. Further, the supply voltage V.sub.dd is connected to the drain terminals of each and MP3 and MP4. To the source terminals of MP3 and MP4 are connected, respectively, the cascode nodes 20, 22 of the first cascode pair 8 and the second cascode pair 10. When the clock signal V.sub.clk is absent, i.e., in a low state, the transistors MP3 and MP4 will become conductive between drain and source, pulling the respective cascode node towards the supply voltage V.sub.dd. This pulling will cease as the clock signal V.sub.clk goes to a high state at the start of a comparison, as the transistors MP3 and MP4 will cease to be conductive between drain and source. This further contributes to reducing hysteresis by starting each comparison with the cascode nodes 20 and 22 at well-defined potentials.

(19) Further, the latched comparator 2 may comprise a latch stage 6, forming a complete latched comparator 2. FIG. 1 gives one example of such a latch stage, but other options are equally possible. In the depicted embodiment, the differential outputs V.sub.out,1 and V.sub.out,2 of the pre-amplifier stage 6 are connected, respectively, to the gate terminals of PMOS transistors MP5 and MP6, whose respective source terminals are connected to the supply voltage V.sub.dd. Thus, the latch stage 6 is configured to receive the differential output from the pre-amplifier stage 4. Further, the differential outputs V.sub.out,1 and V.sub.out,2 of the pre-amplifier stage 6 are connected, respectively, to the gate terminals of NMOS transistors MN9 and MN12, the source terminals of which are connected to ground and the drain terminals of which are connected, respectively, to the first and second latch outputs V.sub.q and V.sub.qn. Latching is performed by latch transistors MP7 and MP8 (PMOS) and MN10 and MN11 (NMOS), wherein the first latch output V.sub.q is connected to the gate terminals of transistors MP8 and MN11 and to the drain terminals of transistors MP7 and MN10, while the second latch output V.sub.qn is connected to the gate terminals of transistors MP7 and MN10 and to the drain terminals of transistors MP8 and MN11. The source terminals of transistors MN9, MN10, MN11, and MN12 are connected to ground, while the source terminals of transistors MP7 and MP8 are connected to the drain terminals of, respectively, transistors MP5 and MP6. Further, NMOS transistors MN8 and MN13 are connected at their respective gate terminals to a signal V.sub.clkn which is a logical negation of the clock signal V.sub.clk, at their respective source terminals to ground and at their respective drain terminals to, respectively, the drain terminal of transistor MP5 and the source terminal of transistor MP7, and the drain terminal of transistor MP6 and the source terminal of transistor MP8.

(20) The latched comparator of FIG. 1 may form part of an analog-to-digital converter (ADC), specifically a successive-approximation analog-to-digital converter (SAR ADC) or a delta-sigma modulation analog-to-digital converter (DSM ADC). Typically, the analog voltage to be converted will then be provided on the positive input V.sub.in,p while a reference signal, with which the analog voltage is to be compared, is provided on the negative input V.sub.in,n. For instance, the ADC may be used in a biomedical sensor device having measurement circuitry which may utilize the ADC comprising the latched comparator.

(21) As a comparison, FIG. 2 shows a latched comparator 102 not according to the present inventive concept, comprising a pre-amplifier stage 104 and a latch stage 106. The latched comparator 104 comprises a block 112 comprising PMOS transistors MP1 and MP2 functioning similar to the block 12 as described above in conjunction with FIG. 1. Further, the pre-amplifier stage comprises a block 116 comprising a single NMOS transistor MN1 functioning similar to the block 16 as described above in conjunction with FIG. 1. However, instead of a two cascode pairs and two gain-boosting transistors, in the amplifying block 114 there are only two single amplifying NMOS transistors MN2 and MN3. MN2 is at its gate terminal connected to the positive input V.sub.in,p, at its drain terminal connected to the drain terminal of MP1 and to the first output Vout,1 and at its source terminal connected to the drain terminal of transistor MN1. MN3 is at its gate terminal connected to the negative input V.sub.in,n, at its drain terminal connected to the drain terminal of MP2 and to the second output V.sub.out,2 and at its source terminal connected to the drain terminal of transistor MN1. Further, the latched comparator 102 comprises a latching stage 106 as depicted in FIG. 2.

(22) The gain A of the pre-amplifier stage 104 in FIG. 2 can be constructed, under the assumption that the transconductance of transistor MN2 g.sub.m,MN2 is constant, as:

(23) $V_{\mathrm{out}}=V_{\mathrm{out},2}-V_{\mathrm{out},1}=\frac{-g_{m,\mathrm{MN}2}*R_{\mathrm{out}}}{\frac{\frac{1}{2}*C*R_{\mathrm{out}}}{t}-1}*\left(V_{\mathrm{in},p}-V_{\mathrm{in},n}\right)\frac{-g_{m,\mathrm{MN}2}*t}{\frac{1}{2}*C}*V_{\mathrm{in}}$$A=\frac{V_{\mathrm{out}}}{V_{\mathrm{in}}}=\frac{-g_{m,\mathrm{MN}2}*t}{\frac{1}{2}*C}$

(24) wherein C is the output capacitance and R.sub.out is the output impedance. The (absolute value of) gain A can be seen to be increasing over time. Thus, A is time-varying.

(25) In contrast, the gain A of the latched comparator of FIG. 1 according to the present inventive concept can be constructed as:

(26) $V_{\mathrm{out}}=V_{\mathrm{out},2}-V_{\mathrm{out},1}=\frac{-g_{m,\mathrm{MN}2}*\frac{t}{\frac{1}{2}*C}}{g_{m,\mathrm{MN}6}*\frac{t}{\frac{1}{2}*C}+1}*\left(V_{\mathrm{in},p}-V_{\mathrm{in},n}\right)\frac{-g_{m,\mathrm{MN}2}}{g_{m,\mathrm{MN}6}}*V_{\mathrm{in}}$$A=\frac{V_{\mathrm{out}}}{V_{\mathrm{in}}}=\frac{-g_{m,\mathrm{MN}2}}{g_{m,\mathrm{MN}6}}$
wherein g.sub.m,MN6 is the transconductance of transistor MN6. As can be seen, the time-dependence of the gain A is to a large degree canceled out. Further, it can be seen that for a large gain A, g.sub.m,MN6 should be small.

(27) FIG. 4 shows a simulated time-domain transient behavior of the latched comparator 2 of FIG. 1. The upper graph shows the latch outputs V.sub.q and V.sub.qn, the middle graph shows the pre-amplifier stage 4 outputs V.sub.out,1 and V.sub.out,2, and the lower graph shows the difference of V.sub.out,1 and V.sub.out,2, i.e., the differential output of the pre-amplifier stage 4. The latch decision point is marked by a vertical line. The input voltage difference is 200 V and the output is 9.2 mV, giving a pre-amplifier stage 4 gain of 46 at the decision point. The differential output has a plateau around the decision point, indicating constant gain, giving opportunity for control of the decision point of the latch.

(28) As a comparison, FIG. 3 shows the time-domain transient behavior of the latched comparator 102 of FIG. 2. As in FIG. 4, the upper graph shows the latch outputs V.sub.q and V.sub.qn, the middle graph shows the pre-amplifier stage 104 outputs V.sub.out,1 and V.sub.out,2, and the lower graph shows the difference of V.sub.out,1 and V.sub.out,2, i.e., the differential output of the pre-amplifier stage 104. The latch decision point is marked by a vertical line. The gain is clearly time-varying. The input voltage difference is 200 V and the output is 2.0 mV, giving a pre-amplifier stage 104 gain A of 10 at the decision point.

(29) In the above the inventive concept has mainly been described with reference to a limited number of examples. However, as is readily appreciated by a person skilled in the art, other examples than the ones disclosed above are equally possible within the scope of the inventive concept, as defined by the appended claims.