Frequency DAC for Radar

Abstract

A frequency digital-to-analog converter (FDAC) for generating an analog frequency modulating signal from a digital frequency modulating signal includes a Least Significant Bit (LSB) DAC section and a Most Significant Bit (MSB) DAC section. The LSB DAC section comprises a plurality of LSB DACs and is configured to switch between the LSB DACs for mitigating mismatch. The MSB DAC section comprises a plurality of MSB DAC cells and is configured to switch the MSB DAC cells according to a predefined sequence during a period of the digital frequency modulating signal.

Claims

1. A frequency digital-to-analog converter (FDAC) for generating an analog frequency modulating signal from a digital frequency modulating signal, the FDAC comprising: a Least Significant Bit (LSB) DAC section; and a Most Significant Bit (MSB) DAC section, wherein the LSB DAC section comprises a plurality of LSB DACs and is configured to switch between the LSB DACs for mitigating mismatch; and wherein the MSB DAC section comprises a plurality of MSB DAC cells and is configured to switch the MSB DAC cells according to a predefined sequence during a period of the digital frequency modulating signal.

2. The FDAC according to claim 1, wherein at least one LSB DAC comprises a plurality of binary weighted DAC cells.

3. The FDAC according to claim 2, further comprising circuitry configured to randomly select one of the LSB DACs for mitigating the mismatch.

4. The FDAC according to claim 2, wherein the LSB DAC section is further configured to perform the switching at least once per change of an MSB of the digital frequency modulating signal.

5. The FDAC according to claim 2, wherein the MSB DAC section is further configured to select different sequences for consecutive periods of the frequency modulating signal.

6. The FDAC according to claim 2, wherein the MSB DAC section is further configured to activate or deactivate the MSB DAC cells incrementally according to the predefined sequence when presented with respectively increasing or decreasing MSBs.

7. The FDAC according to claim 2, wherein the digital frequency modulating signal is a sawtooth wave or a triangle wave.

8. The FDAC according to claim 2, wherein the MSBs of the digital frequency modulating signal are thermometer coded.

9. The FDAC according to claim 1, further comprising circuitry configured to randomly select one of the LSB DACs for mitigating the mismatch.

10. The FAC according to claim 1, wherein the LSB DAC section is further configured to perform the switching at least once per change of an MSB of the digital frequency modulating signal.

11. The FDAC according to claim 1, wherein the MSB DAC section is further configured to select different sequences for consecutive periods of the frequency modulating signal.

12. The FDAC according to claim 1, wherein the MSB DAC section is further configured to activate or deactivate the MSB DAC cells incrementally according to the predefined sequence when presented with respectively increasing or decreasing MSBs.

13. The FDAC according to claim 1, wherein the digital frequency modulating signal is a sawtooth wave or a triangle wave.

14. The FDAC according to claim 1, wherein the MSBs of the digital frequency modulating signal are thermometer coded.

15. A continuous-wave radar comprising an FDAC according to claim 1.

16. A signal generator for generating a Frequency-Modulated Continuous-Wave (FMCW) radar signal comprising: an FDAC according to claim 1 for generating an analog frequency modulating signal; and an oscillator controlled by the analog frequency modulating signal configured to generate the Frequency-Modulated Continuous-Wave (FMCW) radar signal.

17. The signal generator according to claim 16 further comprising circuitry for generating the digital frequency modulating signal.

18. A continuous-wave radar comprising an FDAC according to the signal generator of claim 17.

19. A continuous-wave radar comprising an FDAC according to the signal generator of claim 16.

20. A method for generating an analog frequency modulating signal from a digital frequency modulating signal comprising: converting Least Significant Bits (LSBs) of the digital frequency modulating signal by one of a plurality of LSB DACs; switching between the LSB DACs for mitigating mismatch; converting the Most Significant Bits (MSBs) of the digital frequency modulating signal by MSB DAC cells; and switching the MSB DAC cells according to a predefined sequence during a period of the digital frequency modulating signal.

Description

BRIEF DESCRIPTION OF THE FIGURES

[0020] The above, as well as additional, features will be better understood through the following illustrative and non-limiting detailed description of example embodiments, with reference to the appended drawings.

[0021] FIG. 1 illustrates a functional block diagram of a FMCW radar 100, in accordance with an embodiment;

[0022] FIG. 2 shows a plot of the frequency of a transmitted and received radar signal on the vertical axis as a function of time, in accordance with an embodiment;

[0023] FIG. 3 illustrates a signal generator, in accordance with an embodiment;

[0024] FIG. 4 illustrates a frequency analog to digital converter, in accordance with an embodiment;

[0025] FIG. 5 shows a plot of a transmitted analog frequency modulating radar signal derived from a digital signal comprising one MSB and two LSBs by the FDAC of FIG. 4 when there is no LSB mismatch mitigation applied, in accordance with an embodiment;

[0026] FIG. 6 shows a plot of a transmitted analog frequency modulating radar signal derived from a digital signal comprising one MSB and two LSBs by the FDAC of FIG. 4 when there is LSB mismatch mitigation applied, in accordance with an embodiment;

[0027] FIG. 7 shows a plot 700 of the frequency spectrum of an intermediate frequency signal obtained from a simulated model of the radar according to FIG. 1 to FIG. 4 when mismatch mitigation is applied in both the LSB DAC section and the MSB DAC section, in accordance with an embodiment; and

[0028] FIG. 8 shows a plot of the frequency spectrum of an intermediate frequency signal obtained from a simulated model of the radar according to FIG. 1 to FIG. 4 when no mismatch mitigation is applied in both the LSB DAC section and the MSB DAC, in accordance with an embodiment.

[0029] All the figures are schematic, not necessarily to scale, and generally only show parts which are necessary to elucidate example embodiments, wherein other parts may be omitted or merely suggested.

DETAILED DESCRIPTION

[0030] Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings. That which is encompassed by the claims may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided by way of example. Furthermore, like numbers refer to the same or similar elements or components throughout.

[0031] Various example embodiments relate, amongst others, to a Frequency Digital-to-Analogue Converter (FDAC) a signal generator, a Frequency-Modulated Continuous-Wave (FMCW) radar and related methods. FIG. 1 illustrates a functional block diagram of an FMCW radar 100 according to an embodiment. Radar 100 comprises a signal generator 101 for generating a radar signal 102; a power amplifier 111 for amplifying the radar signal 102 and a transmitting antenna 113 for transmission of the amplified radar signal 102. Upon transmission, the radar signal travels through the air as a wireless signal 120 until encountering an object 122 against which the wireless signal 102 reflects and returns as a reflected radar signal 121. Radar 100 further comprises a receiving antenna 114 for receiving the reflected radar signal 121. The received signal is then amplified by a low noise amplifier, LNA, 112. The resulting intermediate frequency signal 104 is then obtained by mixing the transmitted radar signal 102 with the received radar signal 103 thereby obtaining a difference between the transmitted and reflected signal.

[0032] FIG. 2 shows a plot 200 of the frequency of the transmitted and received radar signals 102, 103 on the vertical axis as a function of time, i.e. plot 200 illustrates the frequency modulation of the transmitted and received radar signals or, shortly, the frequency modulating radar signals 102 and 103. The radar signals 102, 103 are not perfectly linear, but exhibit some non-linearity due to non-idealities of the radar components. In FIG. 2, the transmitted frequency modulating signal 102 has a sawtooth wave form, sometimes also referred to as a chirp signal. Also, other waveforms may be used, e.g. a triangular waveform. FIG. 2 shows a single period of the transmitted frequency modulating signal 102. During operation, the signal generator 101 generates a continuously repeated version of this signal 102. As it takes a certain time duration for the radar signal to propagate and reflect through the air, the received signal 103 will be shifted in time with respect to the transmitted signal 102. By the mixing operation 110, the intermediated frequency modulating signal 104 is indicative for the difference between the transmitted and received frequency modulating signals 102 and 103. From the resulting intermediate frequency modulating signal 104, both the distance to and speed of the reflecting object 122 may be obtained.

[0033] FIG. 3 illustrates a signal generator 301 according to an embodiment. An instance of signal generator 301 may be used as signal generator 101 for the radar 100 of FIG. 1. Signal generator 301 comprises an oscillator 319 that generates the radar signal 302 as output. The output frequency of the oscillator is controlled by the analog frequency modulating signal 320. Signal generator 301 also comprises an FMCW generation circuitry 316 that generates a digital version of the frequency modulating signal. This digital signal 321 is fed into FDAC 315 that converts the digital frequency modulating signal into the analog frequency modulating signal 320. The oscillator 319 may be implemented by a phase locked loop (PLL). PLL 319 comprises a phase comparator or detector 310 that determines the phase difference between a reference signal with constant frequency fref and a scaled or divided version 330 of the output signal 302. This difference then controls a voltage controlled oscillator (VCO) 314, through a charge pump 312 and low pass filter 313. A standalone PLL would then lock the frequency of the output signal 302 to that of the reference signal 331. In PLL 319 on the other hand, the oscillator 314 is also controlled by frequency modulating signal 320 such that the output signal 302 will vary in frequency according to the frequency modulating signal 320. Divider 317 of PLL 319 may further be controlled by the digital signal from FMCW generation circuitry 316 to ensure that the PLL stays in a locked condition during the chirping operation.

[0034] FIG. 4 illustrates an FDAC 415 according to an embodiment, e.g. for use in radar 100 and/or signal generator 301. FDAC 415 comprises an LSB section 440 and an MSB section 460. LSB section 440 converts the least significant bits, LSBs 423, of the digital frequency modulating signal 421 to an analog signal portion 459. MSB section 460 converts the most significant bits (MSBs) 422 of the digital frequency modulating signal 421 to an analog signal portion 479. The output analog frequency modulating signal 420 is then based on the sum of both signal portions 459 and 479. FDAC 415 is a current steering DAC, i.e., signal portions 459 and 479 are represented by currents. FDAC 415 may further comprise a resistor 480 for converting the output current of FDAC 415 to an analog frequency modulating output voltage 420.

[0035] LSB section 440 comprises a plurality of LSB DACs 441-443. An LSB DAC is configured to produce the analog output signal portion 459 from the digital input LSBs 423. To this respect, LSB DACs 442-443 may be instances of LSB DAC 441. An LSB DAC 441 comprises a plurality of current sources 451-453, i.e. LSB DAC cells. One or more current source 451-453 can be weighted, and in some instances binary weighted. In such a case, a first current source 451 is configured to generate a current I.sub.LSB, a second current source to generate a current 2I.sub.LSB, a third current source to generate 4I.sub.LSB etc. More generally, when having N LSBs, then there are N weighted current sources 451-453 with a respective current 2.sup.(i-1)I.sub.LSB for i={1 . . . N}. The LSB DAC 441 further comprises switches 454-456 for activating the respective current sources 451-453. When using a binary weighted LSB DAC 441, then the switches may be operated directly by the respective LSBs. LSB section 440 further comprises a selection circuitry 445 for selecting one of the LSB DACs 441-443. The selection may for example be performed at every clock cycle of the FDAC 415 or after any other time period. The selection may be performed at least every time when one of the MSBs 422 changes. Selection circuitry 445 may perform the selection in a random or pseudo-random manner. By performing the selection, mismatches between current sources of an LSB DAC are not fixed for each LSB value but averaged out over the different LSB DACs.

[0036] MSB section 460 comprises an MSB DAC 461 further comprising a plurality of MSB DAC cells each comprising a current source 471-473 and a switch 474-476. The MSB DAC cells are equally dimensioned, i.e., each current source is configured to deliver the same amount of current I.sub.MSB. As the MSB DAC cells are equally weighted, they may not be able to be controlled directly by the MSBs 422. To this respect MSB section 460 further comprises a thermometric encoder 465 that converts the MSB binary coding to a form of thermometer or unary coding 466. The encoder 465 is further configured to perform the encoding according to a predefined sequence during a period of the digital frequency modulating signal 421. Or, in other words, the encoder 465 is configured such that the MSB DAC cells are activated or deactivated incrementally when presented with respectively increasing or decreasing MSBs. As a result, the MSB DAC cells will not toggle during an increasing or decreasing input signal. The encoder 465 may further comprise a lookup table for storing the predefined sequence.

[0037] The encoder 465 comprises a plurality of such lookup tables and, thus, a plurality of the predefined sequences. The MSB section 460 may then select a different sequence during every next period of the frequency modulating input signal 421, for example after each sawtooth or triangle wave cycle. By selecting from a plurality of predefined sequences, mismatches between the different MSB DAC cells are not repeated over each period of the modulating signal but averaged out.

[0038] FIG. 5 shows a plot 500 of a transmitted analog frequency modulating radar signal 510 converted from a digital signal with one MSB and two LSBs by the FDAC 415 but when there is no switching between LSB DACs 441-443 applied, i.e., when there is no LSB mismatch mitigation. In such a case, signal 510 will show a different unwanted offset from the ideal ADC conversion signal 511 at each transition of an LSB. Furthermore, this offset pattern will be repeated at each MSB transition 502, 503. The received radar signal 520 will show the same offset pattern from the ideal signal 521 but shifted in time due to the propagation time 501 between the radar and the detected object. The non-idealities of the FDAC 415 will also result in a repeating offset pattern in the intermediate frequency signal 530 with respect to the ideal intermediate frequency signal 531. Plot 540 of FIG. 5 illustrates the frequency spectrum of this intermediate frequency signal 530 comprising the wanted frequency spike 541 but also unwanted spurious frequency spikes 542-545 caused by the repeating offset pattern. Due to these spikes, the spurious free dynamic range 550 of the radar signal is negatively impacted.

[0039] FIG. 6 illustrates a plot 600 of a transmitted analog frequency modulating radar signal 610 derived from a digital signal with one MSB and two LSBs by the FDAC 415 but now when there is a switching between LSB DACs 441-443 applied, i.e., when there is LSB mismatch mitigation performed. In this case, signal 610 will also show a different unwanted offset from the ideal ADC conversion signal 611 at each transition of an LSB. However, this offset pattern will not be repeated at each MSB transition 602, 603. The received radar signal 620 will show the same offset pattern from the ideal signal 621 but shifted in time by the air delay 601 between the radar and the detected object. The non-idealities of the LSB DAC section of FDAC 415 will now result in a non-repeating offset pattern in the intermediate frequency signal 630 with respect to the ideal intermediate frequency signal 631. Plot 640 of FIG. 6 illustrates the frequency spectrum of this intermediate frequency signal 630 comprising the wanted frequency spike 641. Due to the mismatch mitigation, unwanted spurious frequency spikes 642-645 will be spread out under the noise floor 646 of the radar system. This results in a higher SDFR 650 when compared with the SFDR 550 of FIG. 5.

[0040] FIG. 7 illustrates a plot 700 of the frequency spectrum of a received intermediate frequency signal 104 obtained from a simulated model of the radar according to FIG. 1 to FIG. 4, i.e., when mismatch mitigation is applied in both the LSB DAC section and the MSB DAC section by the respective selection circuitries 445 and 465. Frequency spike 701 is related to the detected object 122. The distance between this spike 701 and the strongest spurious spike 702 is around 37 dB, i.e. the SFDR is around 37 dB.

[0041] As a comparison, FIG. 8 illustrates a plot 800 of the frequency spectrum of a received intermediate frequency signal 104 obtained from a simulated model of the radar according to FIG. 1 to FIG. 4 but when no mismatch mitigation is applied in both the LSB DAC section and the MSB DAC section by the respective selection circuitries 445 and 465. Frequency spike 801 is related to the detected object 122. The distance between this spike 801 and the strongest spurious spike 802 is around 27 dB, i.e. the SFDR is around 27 dB. In other words, the mismatch mitigation by the radar according to FIG. 1 to FIG. 4 results in a 10 dB improvement of the SFDR.

[0042] The FDAC 415 according to the above embodiments is a current DAC, i.e., the digital input signal is converted into currents and, thereupon, converted to a voltage. As an alternative, the same LSB and MSB mismatch mitigation technique may also be applied to a voltage DAC.

[0043] As used in this application, the term circuitry may refer to one or more or all of the following:

[0044] (a) hardware-only circuit implementations such as implementations in only analog and/or digital circuitry and

[0045] (b) combinations of hardware circuits and software, such as (as applicable): [0046] (i) a combination of analog and/or digital hardware circuit(s) with software/firmware and [0047] (ii) any portions of hardware processor(s) with software (including digital signal processor(s)), software, and memory(ies) that work together to cause an apparatus, such as a mobile phone or server, to perform various functions) and

[0048] (c) hardware circuit(s) and/or processor(s), such as microprocessor(s) or a portion of a microprocessor(s), that requires software (e.g. firmware) for operation, but the software may not be present when it is not needed for operation.

[0049] This definition of circuitry applies to all uses of this term in this application, including in any claims. As a further example, as used in this application, the term circuitry also covers an implementation of merely a hardware circuit or processor (or multiple processors) or portion of a hardware circuit or processor and its (or their) accompanying software and/or firmware. The term circuitry also covers, for example and if applicable to the particular claim element, a baseband integrated circuit or processor integrated circuit for a mobile device or a similar integrated circuit in a server, a cellular network device, or other computing or network device.

[0050] Although various examples of embodiments have been described, it will be apparent to those skilled in the art that the claims are not limited to the details of the foregoing embodiments, and that various changes and modifications may be made to the embodiments. Such changed/modified embodiments are understood to fall within the scope of the claims. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, and all changes which come within the scope of the claims are therefore intended to be embraced therein.

[0051] It will furthermore be understood by the reader of this patent application that the words comprising or comprise do not exclude other elements or steps, that the words a or an do not exclude a plurality, and that a single element, such as a computer system, a processor, or another integrated unit may fulfil the functions of several means recited in the claims. Any reference signs in the claims shall not be construed as limiting the respective claims concerned. The terms first, second, third, a, b, c, and the like, when used in the description or in the claims are introduced to distinguish between similar elements or steps and are not necessarily describing a sequential or chronological order. Similarly, the terms top, bottom, over, under, and the like are introduced for descriptive purposes and not necessarily to denote relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments are capable of operating in other sequences, or in orientations different from the one(s) described or illustrated above.

[0052] While some embodiments have been illustrated and described in detail in the appended drawings and the foregoing description, such illustration and description are to be considered illustrative and not restrictive. Other variations to the disclosed embodiments can be understood and effected in practicing the claims, from a study of the drawings, the disclosure, and the appended claims. The mere fact that certain measures or features are recited in mutually different dependent claims does not indicate that a combination of these measures or features cannot be used. Any reference signs in the claims should not be construed as limiting the scope.