METHOD FOR FABRICATING HIGH ELECTRON MOBILITY TRANSISTOR

Abstract

A method for forming a high electron mobility transistor is disclosed. A substrate is provided. A channel layer is formed on the substrate. An electron supply layer is formed on the channel layer. A dielectric passivation layer is formed on the electron supply layer. A gate recess is formed into the dielectric passivation layer and the electron supply layer. A surface modification layer is conformally deposited on an interior surface of the gate recess. The surface modification layer is first subjected to the nitride treatment and is then subjected to the oxidation treatment. A P-type GaN layer is formed in the gate recess and on the surface modification layer.

Claims

1. A method for forming a high electron mobility transistor, comprising: providing a substrate; forming a channel layer on the substrate; forming an electron supply layer on the channel layer; forming a dielectric passivation layer on the electron supply layer; forming a gate recess into the dielectric passivation layer and the electron supply layer; conformally depositing a surface modification layer on an interior surface of the gate recess; subjecting the surface modification layer to an oxidation treatment or a nitridation treatment, wherein the surface modification layer is first subjected to the nitride treatment and is then subjected to the oxidation treatment; and forming a P-type GaN layer in the gate recess and on the surface modification layer.

2. The method according to claim 1, wherein the surface modification layer is an amorphous silicon layer.

3. The method according to claim 2, wherein the amorphous silicon layer has a thickness of equal to or less than 10 angstroms.

4. The method according to claim 1, wherein the gate recess does not penetrate through the electron supply layer.

5. The method according to claim 1, wherein the dielectric passivation layer comprises oxide or aluminum nitride.

6. The method according to claim 1, wherein the dielectric passivation layer is thicker than the surface modification layer.

7. The method according to claim 1, wherein the dielectric passivation layer has a thickness of about 20 nanometers.

8. The method according to claim 1, wherein before forming the channel layer on the substrate, the method further comprises: forming a buffer layer on the substrate.

9. The method according to claim 8, wherein the buffer layer comprises AlN or AlGaN.

10. The method according to claim 1, wherein the substrate is a silicon substrate.

11. The method according to claim 1, wherein the channel layer comprises intrinsic GaN.

12. The method according to claim 11, wherein the electron supply layer comprises AlGaN.

13. The method according to claim 1, wherein after forming the P-type GaN layer in the gate recess, the method further comprises: forming a gate electrode on the P-type GaN layer; and forming a source electrode in a source region and a drain electrode in a drain region.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0020] FIG. 1 to FIG. 6 are schematic cross-sectional views showing the fabrication of a high electron mobility transistor according to an embodiment of the invention.

DETAILED DESCRIPTION

[0021] In the following detailed description of the disclosure, reference is made to the accompanying drawings, which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention.

[0022] Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. Therefore, the following detailed description is not to be considered as limiting, but the embodiments included herein are defined by the scope of the accompanying claims.

[0023] FIG. 1 to FIG. 6 are schematic cross-sectional views showing the fabrication of a high electron mobility transistor according to an embodiment of the invention. As shown in FIG. 1, a substrate 100 is provided. For example, the substrate 100 may be a silicon substrate, but is not limited thereto. A channel layer 102 may be grown on the substrate 100. According to an embodiment, for example, the channel layer 102 may comprise intrinsic GaN. Optionally, before the formation of the channel layer 102, a buffer layer 101 may be formed on the substrate 100. For example, the buffer layer 101 may comprise AlN or AlGaN, but is not limited thereto.

[0024] As shown in FIG. 2, an electron supply layer 104 is then formed on the channel layer 102. According to an embodiment, for example, the electron supply layer 104 may comprise AlGaN, but is not limited thereto. Subsequently, a dielectric passivation layer 106 is formed on the electron supply layer 104. According to an embodiment, for example, the dielectric passivation layer 106 may comprise oxide or aluminum nitride, but is not limited thereto. According to an embodiment, for example, the dielectric passivation layer 106 may have a thickness of about 20 nanometers.

[0025] As shown in FIG. 3, after forming the dielectric passivation layer 106, a lithographic process and an etching process are performed to form a gate recess 200 into the dielectric passivation layer 106 and the electron supply layer 104. According to an embodiment, the gate recess 200 penetrates through the dielectric passivation layer 106, but does not penetrate through the electron supply layer 104.

[0026] As shown in FIG. 4, subsequently, a surface modification layer 110 is conformally deposited on an interior surface of the gate recess 200 and on the top surface of the dielectric passivation layer 106. According to an embodiment, for example, the surface modification layer 110 is an amorphous silicon layer. Preferably, the amorphous silicon layer 110 may have a thickness of equal to or less than 10 angstroms. According to an embodiment, the dielectric passivation layer 106 is thicker than the surface modification layer 110.

[0027] As shown in FIG. 5, the surface modification layer 110 is then subjected to a treatment P such as an oxidation treatment, thereby transforming an entire thickness of the amorphous silicon layer is into a treated surface modification layer 110a such as a silicon oxide layer. In some embodiments, the treatment P may be a nitridation treatment and the entire thickness of the amorphous silicon layer 110 is transformed into a silicon nitride layer. In some embodiments, the surface modification layer 110 may be subjected to the nitride treatment and is then subjected to the oxidation treatment. In some embodiments, the surface modification layer 110 may be subjected to the nitride treatment and is then subjected to the oxidation treatment. According to some embodiments, the treatment P may comprise anneal processes, plasma treatment, ion implantation or wet clean, but is not limited thereto.

[0028] It is advantageous to use the present invention because the surface modification layer 110 after subjected to the treatment P can reduce the surface roughness on the interior surface of the gate recess 200 and the interface defects can be significantly decreased. The surface modification layer 110 also prevents the GaN/AlGaN from oxidation.

[0029] As shown in FIG. 6, after the treatment P is completed, a P-type GaN layer 210 is formed in the gate recess 200 and on the treated surface modification layer 110a. After the formation of the P-type GaN layer 210 in the gate recess 200, a gate electrode GE is formed on the P-type GaN layer 210. Thereafter, a source electrode SE may be formed in a source region S and a drain electrode DE may be formed in a drain region D, thereby forming the high electron mobility transistor 1. According to an embodiment, for example, the gate electrode GE, the source electrode SE, and the drain electrode DE may comprise a metal, but is not limited thereto.

[0030] Structurally, as shown in FIG. 6, the high electron mobility transistor 1 includes a substrate 100, a channel layer 102 on the substrate 100, an electron supply layer 104 on the channel layer 102, a dielectric passivation layer 106 on the electron supply layer 104, a gate recess 200 in the dielectric passivation layer 106 and the electron supply layer 104, a surface modification layer 110a on an interior surface of the gate recess 200, and a P-type GaN layer 210 in the gate recess 200 and on the surface modification layer 110a. According to an embodiment, after subjecting to the treatment P such as oxidation or nitridation, the surface modification layer 110a may have a gradient silicon concentration. That is, the silicon concentration of the surface modification layer 110a is not a constant across the entire thickness of the surface modification layer 110a.

[0031] According to an embodiment, the surface modification layer 110a is a silicon oxide layer or a silicon nitride layer. According to an embodiment, the gate recess 200 does not penetrate through the electron supply layer 104. According to an embodiment, the high electron mobility transistor 1 further comprises a gate electrode GE on the P-type GaN layer 210, a source electrode SE in a source region S and a drain electrode DE in a drain region D.

[0032] Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.