Duty cycle converter

Abstract

A duty cycle conversion circuit portion comprises N inverters, wherein N is an integer greater than two. The duty cycle conversion circuit is arranged to receive N input signals each having a duty cycle between 1/N and 2/N. Each of the N input signals is applied to a respective input terminal of one of the N inverters such that each inverter receives a different input signal. Each of the N input signals is applied to a respective power terminal of one of the N inverters such that each inverter is powered by a different input signal. Each inverter receives different input signal at its respective input terminal to the input signal applied to its respective power terminal.

Claims

1. A duty cycle conversion circuit portion comprising N inverters, wherein N is an integer greater than two, said duty cycle conversion circuit being arranged to receive N input signals each having a duty cycle between 1/N and 2/N, wherein: each of the N input signals is applied to a respective input terminal of one of the N inverters such that each inverter receives a different input signal; and each of the N input signals is applied to a respective power terminal of one of the N inverters such that each inverter is powered by a different input signal; wherein each inverter receives different input signal at its respective input terminal to the input signal applied to its respective power terminal.

2. The duty cycle conversion circuit portion as claimed in claim 1, comprising a plurality of outputs, wherein each output is provided by an output terminal of a different inverter.

3. The duty cycle conversion circuit portion as claimed in claim 1, wherein the input signals are provided by a divider circuit portion.

4. The duty cycle conversion circuit portion as claimed in claim 3, wherein the divider circuit portion comprises a divide-by-N circuit portion.

5. The duty cycle conversion circuit portion as claimed in claim 1, wherein the power terminal of each of the N inverters is a positive power terminal and a negative power terminal of each of the inverters is connected to ground.

6. The duty cycle conversion circuit portion as claimed in claim 1, wherein the output signals are used to drive a respective plurality of amplifier circuit portions sharing a common low noise amplifier.

7. A duty cycle conversion circuit portion comprising N inverters, wherein N is an integer greater than two, said duty cycle conversion circuit being arranged to receive N input signals each having a duty cycle between 1-1/N and 12/N, wherein: each of the N input signals is applied to a respective input terminal of one of the N inverters such that each inverter receives a different input signal; and each of the N input signals is applied to a respective power terminal of one of the N inverters such that each inverter is powered by a different input signal; wherein each inverter receives different input signal at its respective input terminal to the input signal applied to its respective power terminal.

8. The duty cycle conversion circuit portion as claimed in claim 7, comprising a plurality of outputs, wherein each output is provided by an output terminal of a different inverter.

9. The duty cycle conversion circuit portion as claimed in claim 7, wherein the input signals are provided by a divider circuit portion.

10. The duty cycle conversion circuit portion as claimed in claim 9, wherein the divider circuit portion comprises a divide-by-N circuit portion.

11. The duty cycle conversion circuit portion as claimed in any claim 7, wherein the power terminal of each of the N inverters is a negative power terminal and a positive power terminal of each of the inverters is connected to ground.

12. The duty cycle conversion circuit portion as claimed in any claim 7, wherein the output signals are used to drive a respective plurality of amplifier circuit portions sharing a common low noise amplifier.

Description

(1) Certain embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings in which:

(2) FIG. 1 is a circuit diagram of a duty cycle conversion circuit in accordance with an embodiment of the present invention;

(3) FIG. 2 is a timing diagram illustrating signal transitions typical of the duty cycle conversion circuit shown in FIG. 1; and

(4) FIG. 3 is a schematic diagram of a radio receiver arranged to perform quadrature demodulation that uses the duty cycle conversion circuit of FIG. 1.

(5) FIG. 1 is a circuit diagram of a duty cycle conversion circuit 1 in accordance with an embodiment of the present invention. The duty cycle conversion circuit 1 comprises 4 Boolean inverters 2, 4, 6, 8. Each inverter 2, 4, 6, 8 respectively comprises: an input terminal to 2a, 4a, 6a, 8a; an output terminal 2b, 4b, 6b, 8b; a positive power terminal 2c, 4c, 6c, 8c; and a negative power terminal 2d, 4d, 6d, 8d.

(6) Each inverter 2, 4, 6, 8 is arranged to receive a different input signal 10a, 10b, 10c, 10d at its respective input terminal 2a, 4a, 6a, 8a and produce an output signal 12a, 12b, 12c, 12d at its respective output terminal 2b, 4b, 6b, 8b, wherein the output signals 12a-d are the logical negation of the respective input signals 10a-d so long as the corresponding inverter 2, 4, 6, 8 is powered on.

(7) While the negative power terminal 2d, 4d, 6d, 8d of each inverter 2, 4, 6, 8 is connected to ground, the positive power terminal 2c, 4c, 6c, 8c of each inverter 2, 4, 6, 8 is connected to the input signal 10a-d applied to a different inverter 2, 4, 6, 8. In this particular arrangement the positive power terminal 2c of the first inverter 2 is connected to the input signal 10d applied to the input terminal 8a of the fourth inverter 8; the positive power terminal 4c of the second inverter 4 is connected to the input signal 10a applied to the input terminal 2a of the first inverter 2; the positive power terminal 6c of the third inverter 6 is connected to the second input signal 10b applied to the input terminal 4a of the second inverter 4; and the positive power terminal 8c of the fourth inverter 8 is connected to the third input signal 10c applied to the input terminal 6a of the third inverter 6. Thus it will be seen that the inverters 2, 4, 6, 8 are arranged in a loop wherein the input signal 10a-d applied to each inverter 2, 4, 6, 8 is used to power the next inverter 2, 4, 6, 8 in the loop.

(8) FIG. 2 is a timing diagram illustrating signal transitions typical of the duty cycle conversion circuit 1 shown in FIG. 1. The input signals 10a-d have a duty cycle between 25% and 50% as required and may, by way of example only, be derived from a divide-by-four divider driven by a voltage controlled oscillator (not shown). In order to conserve power, these signals have a well-defined rising edge but the falling edge is less well-defined. This means that whilst each has a duty cycle of approximately 50%, this is not accurate. Such signals cannot be used directly where a four-phase clock with 25% duty cycle is requirede.g. in a radio receiver that requires I and Q signals for modulation and/or demodulation as described with reference to FIG. 3 below.

(9) At an initial time t.sub.0 the input signals 10a-c applied to three of the inverters 2, 4, 6 are at logic low while the other input signal 10d applied to the fourth inverter 8 is logic high. As the fourth input signal 10d is used to power the first inverter 2 by virtue of its connection to its respective input terminal 2c, the first inverter 2 is powered on and thus performs a logical negation of the first input signal 10a and thus produces a logic high at the output terminal 2d as shown by the trace of the output signal 12a. The other three inverters 4, 6, 8 are all powered off at this time.

(10) At time t.sub.1 the first input signal 10a undergoes a positive transition to logic high. As the first inverter 2 is still powered on, this changes the first output signal 12a to logic low. However as the first input signal 10a is used to power the second inverter 4 by virtue of its connection to its respective positive power terminal 4c, this powers on the second inverter 4 which performs a logical negation of the second input signal 10b (which is still low) thus driving the second output signal 12b to logic high. Shortly after t.sub.1 (but not at a well-defined time) the fourth input signal 10d may happen to undergo a negative transition to logic low which causes the first converter 2 to be powered off. However, this has no effect on the first output signal 12a since it is already at logic low.

(11) At a later time t.sub.2 the second input signal 10b undergoes its positive transition to logic high which causes the output signal 12b produced by the second inverter 4 to undergo a negative transition to logic low. The connection between the second input signal 10b and the positive power terminal 6c of the third inverter 6 causes the third inverter 6 to become powered on at this time. As a result of the powering on of the third inverter 6, the third output signal 12c produced by this inverter 6 undergoes a positive transition to logic high as the third input signal 10c is still logic low at this time. Some time thereafter (again not well-defined) the first input signal 10a undergoes a negative transition to logic low, disabling the second inverter 4, whose output has already gone low.

(12) Subsequently at time t.sub.3 the third input signal 10c undergoes its positive transition to logic high. As the second input signal 10b is still logic high and accordingly the third inverter 6 is powered on, this causes the output signal 12c produced by the third inverter 6 to undergo a negative transition to logic low at this time. Furthermore since the third input signal 10c is used to power the fourth inverter 8 and the fourth input signal 10d is logic low at this time, the fourth inverter 8 performs a logical negation of the fourth input signal 10d and thus produces a logic high output signal 12d.

(13) At time t.sub.4 the fourth input signal 10d undergoes its next positive transition to logic high which causes the fourth output signal 12d (of the still-powered fourth inverter 8) to undergo a negative transition to logic low and the first output signal 12a to undergo a positive transition to logic high because the first inverter 2 is powered once more. The cycle then repeats with time t.sub.5 being equivalent to t.sub.1,, t.sub.6 being equivalent to t.sub.2 etc.

(14) It can be seen that so long as the rising edges of each of the input signals 10a-d are well defined at the correct intervals and that each input signal 10a-d has a duty cycle between 25% and 50% (i.e. between 1/N and 2/N wherein N=4), each of the output signals 12a-d will have a duty cycle of exactly 25% triggered by only the rising edges of the input signal.

(15) FIG. 3 is a schematic diagram of a radio receiver 14 arranged to perform quadrature demodulation that uses the duty cycle conversion circuit 1 of FIG. 1. As well as the duty cycle conversion circuit 1 described previously, the radio receiver 14 comprises: an antenna 16; a low-noise amplifier (LNA) 18; two differential mixers 20, 22; a bandpass filter 24; a divide-by-two frequency divider 28; and a voltage controlled oscillator (VCO) 30. It will be appreciated that while this radio receiver 14 is an exemplary application of the duty cycle conversion circuit 1 described previously, the duty cycle conversion circuit 1 of FIG. 1 may provide advantages when used in other applications.

(16) Radio signals 34 received at the antenna 16 of the receiver 14 are received at the over-the-air frequency f.sub.RF and are input to the LNA 18 which amplifies the received signals and produces a balanced, amplified output signal 36 which is input to each of the mixers 20, 22.

(17) The VCO 30 produces an oscillator signal 38 at an oscillator frequency f.sub.VCO which can be controlled in a manner known in the art per se. This oscillator signal 38 is input to the divide-by-two frequency divider 28 which produces the four-phase signals 10a-d described previously at a local oscillator frequency f.sub.LO where f.sub.LO is half of f.sub.VCO (as the oscillator signal 38 is already differential, a divide-by-two frequency divider is used instead of a divide-by-four divider as described previously with reference to FIG. 1). However, each of the four-phase signals 10a-d produced by the divide-by-two divider 28 and described previously with reference to FIG. 2 have arbitrary duty cycles within the 1/N to 2/N range.

(18) The duty cycle conversion circuit 1 converts the four-phase signals 10a-d with arbitrary duty cycles (within the 1/N to 2/N range) to output signals 12a-d, each with a duty cycle of exactly 25% (i.e. exactly 1/N) as described above with reference to FIGS. 1 and 2. These signals 12a-d are input to the mixers 20 and 22 which produce an in-phase (I) signal 40 and a quadrature (Q) signal 42 respectively at an intermediate frequency f.sub.IF. These I and Q signals 40, 42 are input to the bandpass filter 24 which produces the quadrature (I and Q) output 32 at the intermediate frequency f.sub.IF, this output 32 comprising a filtered I signal 44 and a filtered Q signal 46 produced by the bandpass filter 24.

(19) Thus it will be seen that the described embodiment of the present invention provides a duty cycle conversion circuit that enables accurate control of a multi-phased system by utilising the power terminals of a number of inverters as control signals so as to allow the definition of the output duty cycle using only one type of input signal edge. This minimises noise and reduces power consumption compared to use of logic gates such as NAND or AND gates to achieve an equivalent effect, without imposing stringent duty cycle requirements in the RF clock generation.

(20) It will be appreciated by those skilled in the art that the embodiments described above are merely exemplary and are not limiting on the scope of the invention.