RANDOM NUMBER GENERATOR FOR DEFENDING AGAINST SUBCHANNEL ATTACK, AND OPERATION METHOD THEREOF

Abstract

A random number generator resistant to side-channel attacks. The random number generator includes an entropy unit generating random pulses, a random frequency clock generator generating random frequencies by receiving random pulses output from the entropy unit, and an MCU externally masking a specific operation or a specific instruction based on a random frequency received from the random frequency clock generator.

Claims

1. A random number generator resistant to side-channel attacks, the random number generator comprising: an entropy unit generating random pulses; a random frequency clock generator generating random frequencies by receiving random pulses output from the entropy unit; and an MCU externally masking a specific operation or a specific instruction based on a random frequency received from the random frequency clock generator.

2. The random number generator of claim 1, further including: a first selector selectively outputting a random frequency output from the random frequency clock generator and a reference clock to the MCU according to a first selection signal.

3. The random number generator of claim 2, further including: a counter outputting a random number based on a random pulse output from the entropy unit.

4. The random number generator of claim 3, further including: a second selector selectively outputting one of a random number output from a random number generating unit and a random number output from the counter according to a second selection signal.

5. A method for operating a random frequency clock generator resistant to side-channel attacks, the method comprising: (a) generating random pulses by an entropy unit; (b) generating random frequencies by receiving random pulses output from the entropy unit; and (c) masking a specific instruction externally by an MCU based on a random frequency received from the random frequency clock generator.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] FIG. 1 illustrates a structure of a random number generator resistant to side-channel attacks according to an embodiment of the present disclosure.

[0011] FIG. 2 illustrates a structure of an entropy unit according to an embodiment of the present disclosure.

[0012] FIG. 3 illustrates a structure of a random frequency clock generator according to an embodiment of the present disclosure.

[0013] FIG. 4 illustrates a simulation result of a random frequency clock generator according to an embodiment of the present disclosure.

[0014] FIGS. 5 to 8 illustrate simulation results for varying pulse widths according to an embodiment of the present disclosure.

DETAILED DESCRIPTION

[0015] Specific structural or functional descriptions of embodiments according to the concept of the present disclosure described herein are illustrated solely for the purpose of describing embodiments according to the concept of the present disclosure, and embodiments according to the concept of the present disclosure may be embodied in various forms and are not limited to the embodiments described herein.

[0016] Since the embodiments based on the concept of the present disclosure may be modified in various ways and may have various other forms, the embodiments will be illustrated in the appended drawings of the present disclosure and described in detail with reference to the drawings. However, it should be understood that the embodiments of the present disclosure are not limited to specific disclosed forms; instead, the embodiments include all of the modifications, equivalents, or substitutes belonging to the technical principles and scope of the present disclosure.

[0017] Terms used in the present disclosure are intended only for describing a specific embodiment and are not intended to limit the technical scope of the present disclosure. A singular expression should be understood to indicate a plural expression unless otherwise explicitly stated. The term “include” or “have” is used to indicate existence of an embodied feature, number, step, operation, element, component, or a combination thereof; and should not be understood to preclude the existence or possibility of adding one or more other features, numbers, steps, operations, elements, components, or a combination thereof.

[0018] In what follows, embodiments of the present disclosure will be described in detail with reference to appended drawings.

[0019] FIG. 1 illustrates a structure of a random number generator resistant to side-channel attacks according to an embodiment of the present disclosure.

[0020] Referring to FIG. 1, a random number generator resistant to side-channel attacks comprises an entropy unit 100, a random frequency clock generator 200, a first selector 300, an MCU 400, a counter 500, a random number generating unit 600, and a second selector 700.

[0021] The entropy unit 100 generates random pulses having a pulse width determined randomly by alpha particles emitted during the natural decay of radioisotopes. The entropy unit 100 may include a radioisotope emitter and detector, and the pulse width of a random pulse may be determined in proportion to the amount of energy generated due to the collision of one or more alpha particles released from the radioisotope emitter with the radioisotope detector. In other words, pulses with a random pulse width may be generated based on different amounts of energy generated when one or more alpha particles having different amounts of energy collide with the detector or one or more alpha particles having the same amount of energy collide with the detector. The pulse width of random pulses generated by the entropy unit 100 may be a value obtained by multiplying the number of random alpha particles colliding with the detector by the amount of energy of each particle.

[0022] The random frequency clock generator 200 receives random pulses output from the entropy unit 100 to generate a random frequency. The random frequency clock generator 200 includes an AMP 210 and a Voltage Controlled Oscillator (VCO) 220. The random frequency clock generator 200 may generate a random frequency based on the pulse signal width of the random pulse and the time difference between the pulse signals. In other words, the random frequency clock generator 200 may generate a frequency as the number of charges accumulated in the capacitor varies according to the width of a random pulse, the initial frequency output to the VCO 220 is changed, and the frequency is decreased in proportion to the number of charges discharged from the capacitor until the next pulse is generated.

[0023] The first selector 300 selectively receives a random frequency output from the random frequency clock generator 200 and the reference clock CLK based on a first selection signal sel0 and outputs the selected signal to the random number generating unit 600.

[0024] The MCU 400 may be configured by firmware to control the first selection signal sel0 of the first selector and a second selection signal sell of the second selector. The MCU 400 may enable the first selection signal of the first selector for external masking when a specific operation or a specific instruction is executed and may receive a random frequency output from the random frequency clock generator 200 to execute a specific operation or a specific instruction. In other words, if the MCU 400 executes a specific instruction when the duty cycle is fixed, a hacker may easily make a side-channel attack; however, when the timing is varied by a random frequency, the hacker may not make the side-channel attack since it is not possible to know whether the MCU executes an instruction.

[0025] The counter 500 receives random pulses output from the entropy unit 100 and outputs a random number seed. The counter 500 may generate a random number by measuring the time between the random pulses. The counter 500 may provide the generated random number to the random number generating unit 500 so that the provided random number is used as a seed for generating random numbers.

[0026] The random number generating unit 600 may be a deterministic random bit generator (DRBG). The present disclosure employs the AES-CTR DRBG approved by NIST. However, the present disclosure is not limited to the specific selection and may employ a different hash function or HMAC-DRBG.

[0027] The second selector 700 outputs at least one of the random number output from the random number generating unit 600 and the random number output from the counter 400 based on the second selection signal sell.

[0028] In other words, the random frequency output from the random frequency clock generator 200 may be used to implement a hiding technique, which is a countermeasure against the side-channel attack, while the random number output from the second selector may be used to implement a masking technique, which is a countermeasure against the side-channel attack.

[0029] FIG. 2 illustrates a structure of an entropy unit according to an embodiment of the present disclosure.

[0030] Referring to FIG. 2, the entropy unit 100 comprises a photodiode for detecting alpha particles, an amplifier, and a comparator. Alpha particles may be detected by a CMOS-type photodiode (PD), where the reverse bias leakage current of the PD is less than 1 nA, and a photocurrent of 1 μA may be typically generated when the alpha particles are absorbed in the depletion region of the PD. The amplifier may be a transimpedance amplifier (TIA), which may amplify and detect a very low-level current due to the absorption of alpha particles and may perform amplification in two steps. The transimpedance gain and unity-gain bandwidth of a first TIA may be 10 MD. and 10 MHz, respectively, and the gain of a second TIA may be set to 10. The comparator may have a reference voltage of 0.3 V and convert the amplified voltage from the transimpedance amplifier (TIA) to the analog pulse signal V.sub.O_COMP, called random pulses.

[00001]$V_{O\_\mathrm{COMP}}=\{\begin{array}{cc}1& \mathrm{if}{V}_{O\_\mathrm{TIA}}\le V_{\mathrm{REF}3}\\ 0& \mathrm{if}{V}_{O\_\mathrm{TIA}}>V_{\mathrm{REF}3}.\end{array}$

[0031] In other words, the entropy unit 100 finally generates a random pulse when alpha particles caused by the radioisotope decay are detected.

[0032] FIG. 3 illustrates a structure of a random frequency clock generator according to an embodiment of the present disclosure.

[0033] Referring to FIG. 3, a structure of a random frequency clock generator is illustrated. V1 represents the analog pulse of the entropy unit and is connected to a low-pass filter consisting of a register R2, a capacitor C1, and a switching diode Dl. During the positive pulse period, the capacitor C1 may be charged with a time constant τ1=R2.Math.C1 and may be discharged with a time constant τ2=(R1+R5).Math.C1 until the next positive pulse is generated. A non-inverting amplifier may be used to amplify the charging voltage of the capacitor C1 by the entropy unit 100.

[0034] FIG. 4 illustrates a simulation result of a random frequency clock generator according to an embodiment of the present disclosure.

[0035] Referring to FIG. 4, the waveform of an analog pulse signal of the entropy unit 100, the voltage of C1, and the clock frequency changed by the amplified voltage and the amplified current are illustrated. The width of a positive pulse and the width of a negative pulse may determine the frequency range of the clock during two successive pulses.

[0036] FIGS. 5 to 8 illustrate simulation results for varying pulse widths according to an embodiment of the present disclosure. FIG. 5 illustrates a 2.4 V charge voltage of a clock generated by the pulses having a pulse width of 200 ns, and FIG. 6 illustrates the FFT result of the clock generated by the pulses having a pulse width of 200 ns. FIG. 7 illustrates a 0.4 V charge voltage of a clock generated by the pulses having a pulse width of 20 ns, and FIG. 8 illustrates the FFT result of the clock generated by the pulses having a pulse width of 20 ns. In other words, the figures show the charge voltages of clocks generated due to two different random pulse widths (200 ns and 20 ns), which determine the frequency range of the generated clocks and FFT results of the clocks, where the base frequency of the generated clock may become smaller as the charged voltage gets smaller.

[0037] The present disclosure has been described with reference to the embodiments illustrated in the appended drawings. However, the descriptions relate only to illustrative examples, and it should be clearly understood by those skilled in the art to which the present disclosure belongs that various modifications of the embodiments and other equivalent embodiments may be implemented from the descriptions. Therefore, the actual scope of technical protection of the present disclosure should be determined by the technical spirit and principles defined by the appended claims.