VOLTAGE RIPPLE REDUCTION IN A POWER MANAGEMENT CIRCUIT

Abstract

Voltage ripple reduction in a power management circuit is disclosed. The power management circuit includes a power amplifier circuit configured to amplify a radio frequency (RF) signal based on a modulated voltage and an envelope tracking integrated circuit (ETIC) configured to provide the modulated voltage to the power amplifier circuit via a conductive path. Notably, an output impedance presenting at an input of the power amplifier circuit can interact with a modulated load current in the power amplifier circuit to create a voltage ripple in the modulated voltage to potentially cause an undesirable error in the RF signal. Herein, the ETIC is configured to modify the modulated voltage based on feedback of the voltage ripple in the modulated voltage. As such, it is possible to reduce the output impedance at the input of the power amplifier circuit to thereby reduce the voltage ripple in the modulated voltage.

Claims

1. A power management circuit comprising: a power amplifier circuit configured to amplify a radio frequency (RF) signal based on a modulated voltage received at a power amplifier input, wherein the modulated voltage received at the power amplifier input comprises a voltage ripple caused by an output impedance presenting at the power amplifier input; and an envelope tracking integrated circuit (ETIC) comprising: a voltage output coupled to the power amplifier input via a conductive path; and a voltage modulation circuit configured to: generate the modulated voltage at the voltage output based on a modulated target voltage; receive power amplifier voltage feedback indicating the voltage ripple in the modulated voltage received at the power amplifier input; and modify the modulated voltage based on the power amplifier voltage feedback to cause a reduction in the output impedance to thereby reduce the voltage ripple in the modulated voltage received at the power amplifier input.

2. The power management circuit of claim 1, wherein the output impedance presenting at the power amplifier input comprises an inductive impedance of the ETIC and an inductive trace impedance associated with the conductive path.

3. The power management circuit of claim 2, wherein the voltage modulation circuit comprises: a voltage amplifier configured to generate an initial modulated voltage at a voltage amplifier output based on the modulated target voltage; and an offset capacitor configured to raise the initial modulated voltage by an offset voltage to generate the modulated voltage at the voltage output.

4. The power management circuit of claim 3, wherein the voltage amplifier comprises an output stage configured to: generate the initial modulated voltage at the voltage amplifier output; receive the power amplifier voltage feedback indicating the voltage ripple in the modulated voltage received at the power amplifier input; and modify the initial modulated voltage based on the power amplifier voltage feedback to cause the reduction in the output impedance to thereby reduce the voltage ripple in the modulated voltage received at the power amplifier input.

5. The power management circuit of claim 4, wherein the voltage amplifier further comprises an input/bias stage configured to: receive the modulated target voltage and modulated voltage feedback indicating the modulated voltage at the voltage output; and generate a pair of bias signals based on the modulated target voltage and the modulated voltage feedback to thereby cause the output stage to generate the initial modulated voltage.

6. The power management circuit of claim 5, wherein the output stage comprises: a first transistor comprising: a first drain electrode configured to receive a supply voltage; a first gate electrode configured to receive a first bias signal among the pair of bias signals; and a first source electrode coupled to the voltage amplifier output; and a second transistor comprising: a second source electrode coupled to the voltage amplifier output; a second gate electrode configured to receive a second bias signal among the pair of bias signals; and a second drain electrode coupled to a ground; wherein a selected one of the first transistor and the second transistor is biased by a selected one of the first bias signal and the second bias signal to output the initial modulated voltage at the voltage amplifier output.

7. The power management circuit of claim 6, wherein the output stage further comprises: a first Miller capacitor coupled between the first gate electrode and the first source electrode and configured to reduce an impedance at the voltage output to thereby reduce the inductive impedance of the ETIC when the first transistor is biased by the first bias signal; and a second Miller capacitor coupled between the second gate electrode and the second source electrode and configured to reduce the impedance at the voltage output to thereby reduce the inductive impedance of the ETIC when the second transistor is biased by the second bias signal.

8. The power management circuit of claim 6, wherein the output stage further comprises: a first resistor-capacitor (RC) circuit coupled between the power amplifier input and the first gate electrode and configured to combine the power amplifier voltage feedback with the first bias signal to thereby reduce the inductive trace impedance at the power amplifier input; and a second RC circuit coupled between the power amplifier input and the second gate electrode and configured to combine the power amplifier voltage feedback with the second bias signal to thereby reduce the inductive trace impedance at the power amplifier input.

9. The power management circuit of claim 8, wherein the first RC circuit and the second RC circuit each comprises a respective adjustable resistor and a respective adjustable capacitor coupled in series between the power amplifier input and a respective one of the first gate electrode and the second gate electrode.

10. The power management circuit of claim 9, wherein the ETIC further comprises a control circuit configured to adjust at least one of the respective adjustable resistor and the respective capacitor in a respective one of the first RC circuit and the second RC circuit to cause the reduction in the output impedance within a modulation bandwidth of the power amplifier circuit.

11. An envelope tracking integrated circuit (ETIC) comprising: a voltage output coupled to a power amplifier circuit via a conductive path, the power amplifier circuit is configured to amplify a radio frequency (RF) signal based on a modulated voltage received at a power amplifier input, wherein the modulated voltage received at the power amplifier input comprises a voltage ripple caused by an output impedance presenting at the power amplifier input; and a voltage modulation circuit configured to: generate the modulated voltage at the voltage output based on a modulated target voltage; receive power amplifier voltage feedback indicating the voltage ripple in the modulated voltage received at the power amplifier input; and modify the modulated voltage based on the power amplifier voltage feedback to cause a reduction in the output impedance to thereby reduce the voltage ripple in the modulated voltage received at the power amplifier input.

12. The ETIC of claim 11, wherein the output impedance presenting at the power amplifier input comprises an inductive impedance of the ETIC and an inductive trace impedance associated with the conductive path.

13. The ETIC of claim 12, wherein the voltage modulation circuit comprises: a voltage amplifier configured to generate an initial modulated voltage at a voltage amplifier output based on the modulated target voltage; and an offset capacitor configured to raise the initial modulated voltage by an offset voltage to generate the modulated voltage at the voltage output.

14. The ETIC of claim 13, wherein the voltage amplifier comprises an output stage configured to: generate the initial modulated voltage at the voltage amplifier output; receive the power amplifier voltage feedback indicating the voltage ripple in the modulated voltage received at the power amplifier input; and modify the initial modulated voltage based on the power amplifier voltage feedback to cause the reduction in the output impedance to thereby reduce the voltage ripple in the modulated voltage received at the power amplifier input.

15. The ETIC of claim 14, wherein the voltage amplifier further comprises an input/bias stage configured to: receive the modulated target voltage and a modulated voltage feedback indicating the modulated voltage at the voltage output; and generate a pair of bias signals based on the modulated target voltage and the modulated voltage feedback to thereby cause the output stage to generate the initial modulated voltage.

16. The ETIC of claim 15, wherein the output stage comprises: a first transistor comprising: a first drain electrode configured to receive a supply voltage; a first gate electrode configured to receive a first bias signal among the pair of bias signals; and a first source electrode coupled to the voltage amplifier output; and a second transistor comprising: a second source electrode coupled to the voltage amplifier output; a second gate electrode configured to receive a second bias signal among the pair of bias signals; and a second drain electrode coupled to a ground; wherein a selected one of the first transistor and the second transistor is biased by a selected one of the first bias signal and the second bias signal to output the initial modulated voltage at the voltage amplifier output.

17. The ETIC of claim 16, wherein the output stage further comprises: a first Miller capacitor coupled between the first gate electrode and the first source electrode and configured to reduce an impedance at the voltage output to thereby reduce the inductive impedance of the ETIC when the first transistor is biased by the first bias signal; and a second Miller capacitor coupled between the second gate electrode and the second source electrode and configured to reduce the impedance at the voltage output to thereby reduce the inductive impedance of the ETIC when the second transistor is biased by the second bias signal.

18. The ETIC of claim 16, wherein the output stage further comprises: a first resistor-capacitor (RC) circuit coupled between the power amplifier input and the first gate electrode and configured to combine the power amplifier voltage feedback with the first bias signal to thereby reduce the inductive trace impedance at the power amplifier input; and a second RC circuit coupled between the power amplifier input and the second gate electrode and configured to combine the power amplifier voltage feedback with the second bias signal to thereby reduce the inductive trace impedance at the power amplifier input.

19. The ETIC of claim 18, wherein the first RC circuit and the second RC circuit each comprises a respective adjustable resistor and a respective adjustable capacitor coupled in series between the power amplifier input and a respective one of the first gate electrode and the second gate electrode.

20. The ETIC of claim 19, wherein the ETIC further comprises a control circuit configured to adjust at least one of the respective adjustable resistor and the respective capacitor in a respective one of the first RC circuit and the second RC circuit to cause the reduction in the output impedance within a modulation bandwidth of the power amplifier circuit.

Description

BRIEF DESCRIPTION OF THE DRAWING FIGURES

[0011] The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

[0012] FIG. 1A is a schematic diagram of an exemplary existing transmission circuit wherein a power management circuit is configured to reduce a voltage ripple in a modulated voltage based on a conventional approach;

[0013] FIG. 1B is a schematic diagram of an exemplary electrical model of the power management circuit in FIG. 1A;

[0014] FIG. 1C is a graphic diagram providing an exemplary illustration of magnitude impedance as a function of modulation frequency;

[0015] FIG. 2 is a schematic diagram of an exemplary power management circuit configured according to an embodiment of the present disclosure to reduce a voltage ripple in a modulated voltage by reducing an output impedance presenting at a power amplifier input of a power amplifier circuit; and

[0016] FIG. 3 is a schematic diagram providing an exemplary illustration of an inner structure of a voltage amplifier in the power management circuit of FIG. 2.

DETAILED DESCRIPTION

[0017] The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

[0018] It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

[0019] It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.

[0020] Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

[0021] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

[0022] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0023] Embodiments of the disclosure relate to voltage ripple reduction in a power management circuit. The power management circuit includes a power amplifier circuit configured to amplify a radio frequency (RF) signal based on a modulated voltage and an envelope tracking integrated circuit (ETIC) configured to provide the modulated voltage to the power amplifier circuit via a conductive path. Notably, an output impedance (e.g., an inductive impedance associated with the ETIC and the conductive path) presenting at an input of the power amplifier circuit can interact with a modulated load current in the power amplifier circuit to create a voltage ripple in the modulated voltage to potentially cause an undesirable error in the RF signal. In embodiments disclosed herein, the ETIC is configured to modify the modulated voltage based on feedback that indicates the voltage ripple in the modulated voltage as received at the power amplifier input. By modifying the modulated voltage based on knowledge of the voltage ripple, it is possible to reduce the output impedance at the input of the power amplifier circuit to thereby reduce the voltage ripple in the modulated voltage.

[0024] Before discussing the specific voltage ripple reduction embodiment of the present disclosure, starting at FIG. 2, a brief overview of an existing transmission circuit is first discussed with reference to FIGS. 1A-1C to help understand some issues related to reducing voltage ripple based conventional approaches.

[0025] FIG. 1A is a schematic diagram of an exemplary existing transmission circuit 10 wherein a power management circuit 12 is configured to reduce a voltage ripple V.sub.CC-RP in a modulated voltage V.sub.CC based on a conventional approach. The power management circuit 12 includes an ETIC 14 and a power amplifier circuit 16. The ETIC 14 is configured to generate the modulated voltage V.sub.CC based on a modulated target voltage V.sub.TGT and provide the modulated voltage V.sub.CC to the power amplifier circuit 16 via a conductive path 18 (e.g., a conductive trace), which is coupled between a voltage output 20 of the ETIC 14 and a power amplifier input 22 of the power amplifier circuit 16. The power amplifier circuit 16 is configured to amplify an RF signal 24 based on the modulated voltage V.sub.CC.

[0026] Notably, there may be an internal routing distance from the power amplifier input 22 to an actual voltage input 26 (e.g., a collector node) of the power amplifier circuit. Given that the internal routing distance is far shorter than the conductive path 18, the internal routing distance is thus neglected hereinafter. Accordingly, the power amplifier input 22 as illustrated herein can be equated with the actual voltage input 26 of the power amplifier circuit 16.

[0027] The power management circuit 12 may be coupled to a transceiver circuit 28. Herein, the transceiver circuit 28 is configured to generate the RF signal 24 and the modulated target voltage V.sub.TGT.

[0028] The voltage ripple V.sub.CC-RP can be quantitively analyzed based on an equivalent electrical model of the power management circuit 12. In this regard, FIG. 1B is a schematic diagram of an exemplary equivalent electrical model 30 of the power management circuit 12 in FIG. 1A. Common elements between FIGS. 1A and 1B are shown therein with common element numbers and will not be re-described herein.

[0029] The ETIC 14 inherently has an inductive impedance Z.sub.ETIC that can be modeled by an ETIC inductance L.sub.ETIC. The conductive path 18 can also be associated with an inductive trace impedance Z.sub.TRACE that can be modeled by a trace inductance L.sub.TRACE. As a result, looking from the power amplifier input 22 toward the ETIC 14, the power amplifier circuit 16 will see an output impedance Z.sub.OUT that includes both the inductive impedance Z.sub.ETIC and the inductive trace impedance Z.sub.TRACE.

[0030] The power amplifier circuit 16 can be modeled as a current source. In this regard, the power amplifier circuit 16 will modulate a load current I.sub.LOAD based on the modulated voltage V.sub.CC. The load current I.sub.LOAD can interact with the output impedance Z.sub.OUT to create the voltage ripple V.sub.CC-RP in the modulated voltage V.sub.CC received at the power amplifier input 22. In this regard, the voltage ripple V.sub.CC-RP is a function of the modulated load current I.sub.LOAD and the output impedance Z.sub.OUT, as expressed in equation (Eq. 1) below.

V.sub.CC-RP=I.sub.LOAD*Z.sub.OUT  (Eq. 1)

[0031] Notably from the equation (Eq. 1), it may be possible to reduce the voltage ripple V.sub.CC-RP by lowering the output impedance Z.sub.OUT seen at the power amplifier input 22. In this regard, the conventional approach for reducing the voltage ripple V.sub.CC-RP in the power management circuit 12 of FIG. 1A is to add a decoupling capacitor C.sub.PA inside the power amplifier circuit 16 and be as close to the power amplifier input 22 as possible. By adding the decoupling capacitor C.sub.PA, the output impedance Z.sub.OUT can be simply expressed as in equation (Eq. 2).

Z.sub.OUT=Z.sub.CPA∥(Z.sub.ETIC+Z.sub.TRACE)  (Eq. 2)

[0032] In the equation (Eq. 2), Z.sub.CPA represents a capacitive impedance of the decoupling capacitor C.sub.PA. The capacitive impedance Z.sub.CPA and the inductive impedance Z.sub.ETIC and Z.sub.TRACE can each be determined according to equations (Eq. 3.1-3.3) below.

|Z.sub.CPA|=½πf*C.sub.PA  (Eq. 3.1)

|Z.sub.ETIC|=2πf*L.sub.ETIC  (Eq. 3.2)

|Z.sub.TRACE|=2πf*L.sub.TRACE  (Eq. 3.3)

[0033] In the equations (Eq. 3.1-3.3), f represents the modulation frequency of the load current I.sub.LOAD. In this regard, the capacitive impedance Z.sub.CPA, the inductive impedance Z.sub.ETIC, and the inductive trace impedance Z.sub.TRACE are each a function of the modulation frequency f. FIG. 1C is a graphic diagram providing an exemplary illustration of magnitude impedance vs. the modulation frequency f.

[0034] When the modulation frequency f is lower than 10 MHz, the output impedance Z.sub.OUT is dominated by a real part of the inductive impedance Z.sub.ETIC and a real part of the inductive trace impedance Z.sub.TRACE. Between 10 MHz and 100 MHz, the output impedance Z.sub.OUT is dominated by the inductive impedance Z.sub.ETIC and the inductive trace impedance Z.sub.TRACE. Above 1000 MHz, the output impedance Z.sub.OUT will be dominated by the capacitive impedance Z.sub.CPA.

[0035] Herein, a modulation bandwidth BW.sub.MOD of the RF signal 24 may fall between 100 MHz and 1000 MHz (e.g., 100-500 MHz). In this frequency range, the output impedance Z.sub.OUT will be determined by the output impedance Z.sub.OUT as expressed in equation (Eq. 2).

[0036] Notably from equations (Eq. 2 and 3.1), the capacitive impedance Z.sub.CPA, and therefore the output impedance Z.sub.OUT, will decrease as the capacitance C.sub.PA increases. In this regard, the conventional approach for reducing the ripple voltage V.sub.CC-RP relies largely on adding the decoupling capacitor C.sub.PA with a larger capacitance (e.g., 1 to 2 μF). However, doing so can cause some obvious issues.

[0037] Understandably, a rate of change of the modulated voltage V.sub.CC (ΔV.sub.CC or dV/dt) can be inversely affected by the capacitance of the decoupling capacitor C.sub.PA, as shown in equation (Eq. 4) below.

ΔV.sub.CC=I.sub.CC/C.sub.PA  (Eq. 4)

[0038] In the equation (Eq. 4), I.sub.CC represents a low-frequency current (a.k.a. in-rush current) provided by the ETIC 14 when the decoupling capacitor C.sub.PA is charged or discharged. In this regard, the larger capacitance the decoupling capacitor C.sub.PA has, the larger amount of the low-frequency current I.sub.CC would be needed to change the modulated voltage V.sub.CC at a required rate of change (ΔV.sub.CC). As a result, the existing transmission circuit 10 may cause a negative impact on battery life.

[0039] If the low-frequency current I.sub.CC is kept at a low level to prolong battery life, the existing transmission circuit 10 may have difficulty meeting the required rate of change (ΔV.sub.CC), particularly when the RF signal 24 is modulated based on orthogonal frequency division multiplexing (OFDM) for transmission in a millimeter wave (mmWave) spectrum. Consequently, the existing transmission circuit 10 may not be able to change the modulated voltage V.sub.CC in between OFDM symbols.

[0040] On the other hand, if the capacitance of the decoupling capacitor C.sub.PA is reduced to help improve the rate of change (ΔV.sub.CC) of the modulated voltage V.sub.CC and reduce the in-rush current I.sub.CC, doing so may lead to insufficient reduction of the output impedance Z.sub.OUT and, thus, the voltage ripple V.sub.CC-RP. Hence, it is desirable to sufficiently reduce the ripple voltage V.sub.CC-RP within the modulation bandwidth BW.sub.MOD concurrent to improving the rate of change (ΔV.sub.CC) of the modulated voltage V.sub.CC and reducing the in-rush current I.sub.CC.

[0041] FIG. 2 is a schematic diagram of an exemplary power management circuit 32 configured according to an embodiment of the present disclosure to reduce a voltage ripple V.sub.CC-RP in a modulated voltage V.sub.CC by reducing an output impedance Z.sub.OUT presenting at a power amplifier input 34 of a power amplifier circuit 36. Herein, the power amplifier circuit 36 is configured to receive the modulated voltage V.sub.CC via a conductive path 38 (e.g., a conductive trace) and amplify an RF signal 40 based on the modulated voltage V.sub.CC. The power amplifier circuit 36 includes a decoupling capacitor C.sub.PA. Similar to the decoupling capacitor C.sub.PA in the power amplifier circuit 16 in FIG. 1A, the decoupling capacitor C.sub.PA is also provided as close to the power amplifier input 34 as possible.

[0042] The power management circuit 32 includes an ETIC 42. The ETIC 42 includes a voltage modulation circuit 44. The voltage modulation circuit 44 is configured to generate the modulated voltage V.sub.CC at a voltage output 46 based on a modulated target voltage V.sub.TGT. Herein, the voltage output 46 is coupled to the power amplifier input 34 via the conductive path 38.

[0043] Like the power management circuit 12 in FIG. 1A, the decoupling capacitor C.sub.PA has a capacitive impedance Z.sub.CPA, the ETIC 42 inherently has an inductive impedance Z.sub.ETIC, and the conductive path 38 is inherently associated with an inductive trace impedance Z.sub.TRACE, which can be expressed as in the equations (Eq. 3.1-3.3). Accordingly, the power amplifier circuit 36 will see an output impedance Z.sub.OUT, as determined in the equation (Eq. 2), within a modulation bandwidth (e.g., 100-500 MHz) of the RF signal 40. Herein, the power amplifier circuit 36 also operates as a current source, which can induce a modulated load current I.sub.LOAD based on the modulated voltage V.sub.CC. Similar to the power management circuit 12 in FIG. 1A, the modulated load current I.sub.LOAD can interact with the output impedance Z.sub.OUT to create a voltage ripple V.sub.CC-RP in the modulated voltage V.sub.CC received at the power amplifier input 34.

[0044] In embodiments disclosed herein, the decoupling capacitor C.sub.PA has a smaller capacitance (e.g., 100 pF) compared to the decoupling capacitor C.sub.PA in the power amplifier circuit 16 in FIG. 1A. By employing the smaller decoupling capacitor C.sub.PA, it is possible to improve the rate of change (ΔV.sub.CC) of the modulated voltage V.sub.CC to satisfy the stringing voltage switching time requirement (e.g., per OFDM symbol or sub-symbol) in such advanced wireless systems as fifth generation (5G) and 5G new-radio (5G-NR), while concurrently reducing the in-rush current I.sub.CC to prolong battery life.

[0045] Further, the power management circuit 32 is configured to reduce the voltage ripple V.sub.CC-RP in the modulated voltage V.sub.CC by reducing the output impedance POUT presenting at the power amplifier input 34 and/or creating a notch filter at the power amplifier input 34. As a result, the power management circuit 32 can achieve a defined performance threshold, such as RMS EVM and/or peak EVM within the modulation bandwidth of the RF signal 40.

[0046] In an embodiment, the voltage modulation circuit 44 includes a voltage amplifier 48 (denoted as “VA”), which can be an operational amplifier (OpAmp), as an example. The voltage amplifier 48 is configured to generate an initial modulated voltage V.sub.AMP at a voltage amplifier output 50 based on the modulated target voltage V.sub.TGT and a supply voltage V.sub.SUP. The voltage modulation circuit 44 also includes an offset capacitor C.sub.OFF that is coupled in between the voltage amplifier output 50 and the voltage output 46. The offset capacitor C.sub.OFF is configured to raise the initial modulated voltage V.sub.AMP by an offset voltage V.sub.OFF to thereby generate the modulated voltage V.sub.CC at the voltage output 46 (V.sub.CC=V.sub.AMP+V.sub.OFF).

[0047] The voltage amplifier 48 is also configured to receive a modulated voltage feedback V.sub.CC-FB that indicates the modulated voltage V.sub.CC at the voltage output 46, thus making the voltage modulation circuit 44 a closed-loop circuit. Accordingly, the voltage amplifier 48 can adjust the initial modulated voltage V.sub.AMP and, thus the modulated voltage V.sub.CC, based on the modulated feedback V.sub.CC-FB to better track the modulated target voltage V.sub.TGT.

[0048] The voltage amplifier 48 includes an input/bias stage 52 and an output stage 54. The output stage 54 is coupled in series to the voltage amplifier output 50. According to an embodiment of the present disclosure, the output stage 54 is configured to receive a power amplifier voltage feedback V.sub.CC-PA-FB that indicates the modulated voltage V.sub.CC as received at the power amplifier input 34. The output stage 54 may receive the power amplifier voltage feedback V.sub.CC-PA-FB via a feedback path 56. Like the conductive path 38, the feedback path 56 is associated with an inductive feedback trace impedance Z.sub.TRACE-FB that can be modeled by a feedback inductance L.sub.TRACE-FB.

[0049] Understandably, since the power amplifier voltage feedback V.sub.CC-PA-FB is provided from the power amplifier input 34, the power amplifier voltage feedback V.sub.CC-PA-FB will include the voltage ripple V.sub.CC-RP in the modulated voltage V.sub.CC as received at the power amplifier input 34. Accordingly, the voltage amplifier 48 may modify the initial modulated voltage V.sub.AMP based on the power amplifier voltage feedback V.sub.CC-PA-FB to cause the output impedance Z.sub.OUT to be reduced at the power amplifier input 34, thus helping to reduce the voltage ripple V.sub.CC-RP in the modulated voltage V.sub.CC that is received at the power amplifier input 34.

[0050] The ETIC 42 may include a control circuit 58, which can be a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC), as an example. In an embodiment, the control circuit 58 may control the voltage amplifier 48, for example, via a control signal 60, to modify the initial modulated voltage V.sub.AMP based on the power amplifier voltage feedback V.sub.CC-PA-FB to thereby reduce the output impedance Z.sub.OUT at the power amplifier input 34.

[0051] FIG. 3 is a schematic diagram providing an exemplary illustration of an inner structure of the voltage amplifier 48 in FIG. 2. Common elements between FIGS. 2 and 3 are shown therein with common element numbers and will not be re-described herein.

[0052] In an embodiment, the input/bias stage 52 is configured to receive the modulated voltage V.sub.TGT and the modulated voltage feedback V.sub.CC-FB. Accordingly, the input/bias stage 52 generates a pair of bias signals 62P (a.k.a. first bias signal), 62N (a.k.a. second bias signal) to control the output stage 54.

[0053] In an embodiment, the output stage 54 is configured to generate the initial modulated voltage V.sub.AMP at the voltage amplifier output 50 based on a selected one of the bias signals 62P, 62N. The output stage 54 is also configured to receive the power amplifier voltage feedback V.sub.CC-FB. Accordingly, the output stage 54 can modify the initial modulated voltage V.sub.AMP based on the power amplifier voltage feedback V.sub.CC-FB to reduce the output impedance Z.sub.OUT and thereby the voltage ripple V.sub.CC-RP at the power amplifier input 34.

[0054] In an embodiment, the output stage 54 includes a first transistor 64P and a second transistor 64N. In a non-limiting example, the first transistor 64P is a p-type field-effect transistor (pFET) and the second transistor 64N is an n-type FET (nFET). In this example, the first transistor 64P includes a first source electrode C.sub.1, a first drain electrode D.sub.1, and a first gate electrode G.sub.1, and the second transistor 64N includes a second source electrode C.sub.2, a second drain electrode D.sub.2, and a second gate electrode G.sub.2. Specifically, the first drain electrode D.sub.1 is configured to receive the supply voltage V.sub.SUP, the second drain electrode D.sub.2 is coupled to a ground (GND), and the first source electrode C.sub.1 and the second source electrode C.sub.2 are both coupled to the voltage amplifier output 50.

[0055] The first gate electrode G.sub.1 is coupled to the input/bias stage 52 to receive the bias signal 62P and the second gate electrode G.sub.2 is coupled to the input/bias stage 52 to receive the bias signal 62N. Herein, the input/bias stage 52 is configured to generate the bias signal 62P in response to an increase of the modulated voltage V.sub.CC or generate the bias signal 62N in response to a decrease of the modulated voltage V.sub.CC. Specifically, the first transistor 64P will be turned on to output the initial modulated voltage V.sub.AMP and source a high-frequency current IAC (e.g., an alternating current) from the supply voltage V.sub.SUP in response to receiving the bias signal 62P, and the second transistor 64N will be turned on to output the initial modulated voltage V.sub.AMP from the supply voltage V.sub.SUP and sink the high-frequency current IAC to the GND in response to receiving the bias signal 62N.

[0056] In this embodiment, the output stage 54 also includes a first Miller capacitor C.sub.Miller1 and a second Miller capacitor C.sub.Miller2. Specifically, the first Miller capacitor C.sub.Miller1 is coupled between the voltage amplifier output 50 and the first gate electrode G.sub.1, and the second Miller capacitor C.sub.Miller2 is coupled between the voltage amplifier output 50 and the second gate electrode G.sub.2. In this regard, the output stage 54 can be regarded as a typical class AB rail-rail OpAmp output stage. The first Miller capacitor C.sub.Miller1 and the second Miller capacitor C.sub.Miller2 not only can stabilize controls of the first transistor 64P and the second transistor 64N (e.g., mitigating so-called Miller effect), but may also reduce the closed-loop output impedance of the voltage amplifier 48.

[0057] Notably, since the first Miller capacitor C.sub.Miller1 and the second Miller capacitor C.sub.Miller2 are each coupled to the voltage amplifier output 50, the first Miller capacitor C.sub.Miller1 and the second Miller capacitor C.sub.Miller2 can only reduce the inductive impedance Z.sub.ETIC, which is part of the output impedance Z.sub.OUT seen at the power amplifier input 34. As such, to further reduce the output impedance Z.sub.OUT, it is also necessary to reduce the inductive trace impedance Z.sub.TRACE.

[0058] In this regard, the output stage 54 further includes a first resistor-capacitor (RC) circuit 66P and a second RC circuit 66N. The first RC circuit 66P and the second RC circuit 66N are both coupled to the power amplifier input 34 via the feedback path 56 to thereby receive the power amplifier voltage feedback V.sub.CC-FB. Specifically, the first RC circuit 66P is coupled between the power amplifier input 34 and the first gate electrode G.sub.1, and the second RC circuit 66N is coupled between the power amplifier input 34 and the second gate electrode G.sub.2. As such, the first RC circuit 66P can cause the power amplifier voltage feedback V.sub.CC-FB to be combined with the bias signal 62P to thereby modify the bias signal 62P. Similarly, the second RC circuit 66N can cause the power amplifier voltage feedback V.sub.CC-FB to be combined with the bias signal 62N to thereby modify the bias signal 62N.

[0059] In an embodiment, the first RC circuit 66P includes a first adjustable resistor R.sub.FB1 and a first adjustable capacitor C.sub.FB1, and the second RC circuit 66N includes a second adjustable resistor R.sub.FB2 and a second adjustable capacitor C.sub.FB2. Recall that the feedback path 56 is associated with the inductive feedback trace impedance Z.sub.TRACE-FB that can be modeled by the feedback inductance L.sub.TRACE-FB. As such, the first adjustable resistor R.sub.FB1, the first adjustable capacitor C.sub.FB1, and the feedback inductance L.sub.TRACE-FB can be equated with a first resistor-inductor-capacitor (RLC) circuit, which has a first resonance frequency f.sub.1 as expressed in equation (Eq. 5) below.

f.sub.1=½π√{square root over (L.sub.TRACE-FB*C.sub.FB1)}  (Eq. 5)

[0060] Likewise, the second adjustable resistor R.sub.FB2, the second adjustable capacitor C.sub.FB2, and the feedback inductance L.sub.TRACE-FB can be equated with a second RLC circuit, which has a second resonance frequency f.sub.2 as expressed in equation (Eq. 6) below.

f.sub.2=½π√{square root over (L.sub.TRACE-FB*C.sub.FB2)}  (Eq. 6)

[0061] From equations (Eq. 5 and 6), the first adjustable capacitor C.sub.FB1 and the second adjustable capacitor C.sub.FB2 can each be adjusted to resonate with the feedback inductance L.sub.TRACE-FB to create a low-impedance feedback path at a respective one of the first resonance frequency f.sub.1 and the second resonance frequency f.sub.2. The first adjustable resistor R.sub.FB1 will de-Q the first resonance frequency f.sub.1 across the modulation bandwidth BW.sub.MOD to prevent the first adjustable capacitor C.sub.FB1 and the feedback inductance L.sub.TRACE-FB from entering oscillation at the first resonance frequency f.sub.1. Likewise, the second adjustable resistor R.sub.FB2 will de-Q the second resonance frequency f.sub.2 across the modulation bandwidth BW.sub.MOD to prevent the second adjustable capacitor C.sub.FB2 and the feedback inductance L.sub.TRACE-FB from entering oscillation at the second resonance frequency f.sub.2.

[0062] When the voltage ripple V.sub.CC-RP seen at the power amplifier input 34 is fed back to the first gate electrode G.sub.1 or the second gate electrode G.sub.2, the first transistor 64P and the second transistor 64N may act like a common source amplifier, which amplifies and inverts the initial modulated voltage V.sub.AMP at the voltage amplifier output 50 and, therefore, the voltage output 46 of the ETIC 42. The inverted initial modulated voltage V.sub.AMP will cause more of the load current I.sub.LOAD to flow to the GND through the conductive path 38 (a.k.a. the trace inductor L.sub.TRACE) than flowing through the power amplifier circuit 36, thus lowering the inductive trace impedance Z.sub.TRACE and, accordingly the output impedance Z.sub.OUT at the power amplifier input 34.

[0063] Thus, by adjusting the first adjustable capacitor C.sub.FB1, the first adjustable resistor R.sub.FB1, the second adjustable capacitor C.sub.FB2, and/or the second adjustable resistor R.sub.FB2, it is possible to reduce the output impedance Z.sub.OUT to across the modulation bandwidth BW.sub.MOD. In an embodiment, the first adjustable capacitor C.sub.FB1, the first adjustable resistor R.sub.FB1, the second adjustable capacitor C.sub.FB2, and/or the second adjustable resistor R.sub.FB2 may be adjusted by the control circuit 58 via the control signal 60.

[0064] By employing the first Miller capacitor C.sub.Miller1 and the second Miller capacitor C.sub.Miller2 to help reduce the inductive impedance Z.sub.ETIC, and further employing the first RC circuit 66P and the second RC circuit 66N to help reduce the inductive trace impedance Z.sub.TRACE, it is possible to reduce the output impedance Z.sub.OUT to thereby reduce the voltage ripple V.sub.CC-RP in the modulated voltage V.sub.CC. A simulation shows that, at 200 MHz load current modulation frequency, the power management circuit 32 can reduce an RMS value of the voltage ripple V.sub.CC-RP from 231 mV, as in the power management circuit 12 in FIG. 1A, to 134 mV, which amounts to a 42% improvement.

[0065] With reference to FIG. 2, the ETIC 42 further includes a switcher circuit 68. In an embodiment, the switcher circuit 68 includes a multi-level charge pump (MCP) 70 that is coupled to the voltage output 46 via a power inductor LP. The MCP 70, which can be a buck-boost voltage converter, as an example, is configured to generate a low-frequency voltage VDC based on a battery voltage V.sub.BAT. Specifically, the MCP 70 may operate in a buck mode to generate the low-frequency voltage VDC at 0×V.sub.BAT or 1×V.sub.BAT, or in a boost mode to generate the low-frequency voltage VDC at 2×V.sub.BAT. Thus, by configuring the MCP 70 to toggle between 0×V.sub.BAT, 1×V.sub.BAT, and/or 2×V.sub.BAT based on an appropriate duty cycle, the MCP 70 can generate the low-frequency voltage VDC at multiple voltage levels.

[0066] The power inductor LP is configured to induce a low-frequency current I.sub.CC (a.k.a. in-rush current) based on the low-frequency voltage VDC. As previously described in FIG. 1A, the low-frequency current I.sub.CC is provided to the power amplifier input 34 to charge the decoupling capacitor C.sub.PA.

[0067] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.