Switch for Connecting Field Apparatuses and Device for Galvanically Isolating at Least One Apparatus which is Connectable to a 2-wire Ethernet Bus System

Abstract

Switch for connecting field apparatuses and device for galvanically isolating at least one apparatus which is connectable to a 2-wire Ethernet bus system includes an uplink and a downlink PHY interface device that each have a transmitting unit and a receiving unit that has two output terminals for providing a received ternary-coded signal as differential signal, includes an uplink and a downlink signal split device that are each connected to the output terminals of an assigned receiving unit and are configured to split a ternary-coded signal provided as differential signal into two binary coded signals, and includes an uplink and a downlink optocoupler device that are each connected to an assigned signal split device and are configured to transfer two received binary-coded signals to a transmitting unit of an assigned PHY interface device.

Claims

1. A device for galvanically isolating at least one apparatus which is connectable to a 2-wire Ethernet bus system, comprising: an uplink and a downlink physical layer (PHY) interface device, each PHY interface device comprising a transmitting unit and a receiving unit, and the receiving units each having two output terminals for providing a received ternary-coded signal as a differential signal; an uplink and a downlink signal split device, each connected to output terminals of an assigned receiving unit and configured to split a ternary-coded signal provided as differential signal into two binary-coded signals; and an uplink and a downlink optocoupler device, each connected to an assigned signal split device and configured to transfer two received binary-coded signals to a transmitting unit of an assigned PHY interface device.

2. The device as claimed in claim 1, wherein the uplink signal split device is connected to the output terminals of the receiving unit of the uplink PHY interface device; and wherein the downlink signal split device is connected to the output terminals of the receiving unit of the downlink PHY interface device.

3. The device as claimed in claim 1, wherein the uplink and downlink signal split devices are each formed by comparators, switching transistors or logic gates.

4. The device as claimed in claim 2, wherein the uplink and downlink signal split devices are each formed by comparators, switching transistors or logic gates.

5. The device as claimed in claim 3, wherein the uplink and downlink signal split devices are each formed by two comparators for a respective differential signal component and are configured to compare a respective differential signal component with a reference signal level.

6. The device as claimed in claim 3, wherein the ternary-coded signal is an MLT-3 signal comprising a negative signal level, a zero signal level and a positive signal level; and wherein the two binary-coded signals each comprise a zero signal level and a one signal level.

7. The device as claimed in claim 5, wherein the ternary-coded signal is an MLT-3 signal comprising a negative signal level, a zero signal level and a positive signal level; and wherein the two binary-coded signals each comprise a zero signal level and a one signal level.

8. The device as claimed in claim 6, wherein the uplink and downlink signal split devices are each configured to convert the negative signal level of the MLT-3 signal to the zero signal level of a first binary-coded signal and to the one signal level of a second binary-coded signal, the zero signal level of the MLT-3 signal to the same signal level of the first and second binary-coded signals and the positive signal level of the MLT-3 signal to the one signal level of the first binary-coded signal and to the zero signal level of the second binary-coded signal.

9. The device as claimed in claim 6, wherein the uplink and downlink signal split devices are each configured to convert the negative signal level of the MLT-3 signal to the one signal level of a first binary-coded signal and to the zero signal level of a second binary-coded signal, the zero signal level of the MLT-3 signal to the same signal level of the first and second binary-coded signals and the positive signal level of the MLT-3 signal to the zero signal level of the first binary-coded signal and to the one signal level of the second binary-coded signal.

10. The device as claimed in claim 8, wherein the uplink and downlink signal split devices are each configured to convert the zero signal level of the MLT-3 signal to the zero signal level of the first binary-coded signal and to the zero signal level of the second binary-coded signal or the zero signal level of the MLT-3 signal to the one signal level of the first binary-coded signal and to the one signal level of the second binary-coded signal.

11. The device as claimed in claim 9, wherein the uplink and downlink signal split devices are each configured to convert the zero signal level of the MLT-3 signal to the zero signal level of the first binary-coded signal and to the zero signal level of the second binary-coded signal or the zero signal level of the MLT-3 signal to the one signal level of the first binary-coded signal and to the one signal level of the second binary-coded signal.

12. The device as claimed in claim 1, wherein the uplink optocoupler device is connected to the uplink signal split device; wherein the downlink optocoupler device is connected to the downlink signal split device; and wherein the optocoupler devices each comprise two digital optocouplers for transferring one binary-coded signal of the two binary-coded signals.

13. The device as claimed in claim 1, wherein the device is configured for use in an intrinsically safe circuit and, in accordance with International Electrotechnical Commission (IEC) standard 60079-11, includes a safe link to line elements to be protected.

14. The device as claimed in claim 1, wherein the optocoupler devices each comprise two digital optocouplers, each having an input-side anode terminal, an input-side cathode terminal, a supply voltage terminal, an output signal terminal and an output-side ground terminal; and wherein the cathode terminals, the supply voltage terminals and the output signal terminals are each interconnected with limiting resistors for limiting at least one of voltage, current and power.

15. The device as claimed in claim 1, wherein the device is configured for connection to multiplexed supply lines of the 2-wire Ethernet bus system which are provided for simultaneous power and data transmission.

16. The device as claimed in claim 1, wherein the apparatus which is connectable to the 2-wire Ethernet bus system is configured in accordance with Ethernet Advanced Physical Layer.

17. A switch for connecting field apparatuses to a 2-wire Ethernet bus system, comprising a device for galvanic isolation comprising an uplink and a downlink physical layer (PHY) interface device, an uplink and a downlink signal split device and an uplink and a downlink optocoupler device; a primary switch connected to the uplink PHY interface device; a secondary switch connected to the downlink PHY interface device; wherein the uplink and downlink PHY interface devices each comprise a transmitting unit and a receiving unit, the receiving units each including two output terminals for providing a received ternary-coded signal as a differential signal; wherein the uplink and downlink signal split devices are each connected to output terminals of an assigned receiving unit and are configured to split a ternary-coded signal provided as the differential signal into two binary coded signals; and wherein the uplink and downlink optocoupler devices are each connected to an assigned signal split device and are configured to transfer two received binary-coded signals to a transmitting unit of an assigned PHY interface device.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The present invention is explained in greater detail below on the basis of an exemplary embodiment with reference to the drawings, in which:

[0023] FIG. 1 shows a device for the galvanic isolation of at least one apparatus which is connectable to a 2-wire Ethernet bus system in accordance with the invention;

[0024] FIG. 2 shows an arrangement composed of a comparator and a digital optocoupler with limiting resistors, where the arrangement is comprised by the device of FIG. 1; and

[0025] FIG. 3 shows a switch comprising the device of FIG. 1.

DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS

[0026] The device for the galvanic isolation of at least one apparatus which is connectable to a 2-wire Ethernet bus system, as illustrated in FIG. 1, is preferably configured for use in an intrinsically safe circuit and advantageously, in accordance with IEC60079-11, has a safe link to line elements to be protected. Here, the at least one apparatus that is connectable to the 2-wire Ethernet bus system is configured, for example, in accordance with Ethernet Advanced Physical Layer. In accordance with one particularly preferred embodiment, the device is configured for connection to multiplexed supply lines of the 2-wire Ethernet bus system that are provided for simultaneous power and data transmission.

[0027] As shown in FIG. 1, the device has an uplink and a downlink PHY interface device 101, 102, each comprising a transmitting unit Tx and a receiving unit Rx. The receiving units Rx each have two output terminals 111-112, 123-124 for providing a received ternary-coded signal as differential signal MLT-3. Moreover, the device has an uplink and a downlink signal split device 131-132, 133-134, each connected to the output terminals 111-112, 123-124 of an assigned receiving unit Rx and configured for splitting a ternary-coded signal MLT-3 provided as differential signal into two binary coded signals BIN-1, BIN-2.

[0028] In the present exemplary embodiment, the uplink and downlink signal split devices are each formed by two comparators 131-132, 133-134 for a respective differential signal component, which is present at one of the output terminals 111-112, 123-124, and configured to compare the respective differential signal component with a reference signal level VREF. As an alternative to this configuration, the uplink and downlink signal split devices can, in principle, also each be formed by switching transistors or logic gates.

[0029] The uplink signal split device 131-132 is connected to the output terminals 111-112 of the receiving unit Rx of the uplink PHY interface device 101, while the downlink signal split device 133-134 is connected to the output terminals 123-124 of the receiving unit Rx of the downlink PHY interface device 102. Moreover, an uplink and a downlink optocoupler device 141-142, 143-144 are provided, each connected to an assigned signal split device 131-132 and configured to transfer two received binary-coded signals BIN-1, BIN-2 to a transmitting unit TX of an assigned PHY interface device 101, 102. Here, the uplink optocoupler device 141-142 is connected to the uplink signal split device 131-132, while the downlink optocoupler device 143-144 is connected to the downlink signal split device 133-134. The optocoupler devices each comprise 2 digital optocouplers 141-142, 143-144 for transferring, in each case, one of the two binary-coded signals BIN-1, BIN-2.

[0030] On the downlink and uplink sides, the optocouplers 141-142, 143-144, via their output terminals, each once again provide a ternary-coded signal as a differential signal MLT-3, which is fed in each case to two input terminals 121-122, 113-114 of the transmitting units Tx of the PHY interface devices 102, 101. In the present exemplary embodiment, the ternary-coded signal is an MLT-3 signal comprising a negative signal level, a zero signal level and a positive signal level. By contrast, the two binary-coded signals BIN-1, BIN-2 each comprise a zero signal level and a one signal level.

[0031] The signal split devices formed by the comparators 131-132, 133-134 are each configured to convert (i) the negative signal level of the MLT-3 signal to the zero signal level of a first binary-coded signal BIN-1 and to the one signal level of a second binary-coded signal BIN-2, (ii) the zero signal level of the MLT-3 signal to the same signal level of the first and second binary-coded signals BIN-1, BIN-2 and (iii) the positive signal level of the MLT-3 signal to the one signal level of the first binary-coded signal BIN-1 and to the zero signal level of the second binary-coded signal BIN-2. Here, the zero signal level of the MLT-3 signal can be converted (i) to the zero signal level of the first binary-coded signal BIN-1 and to the zero signal level of the second binary-coded signal BIN-2 or alternatively (ii) to the one signal level of the first binary-coded signal BIN-1 and to the one signal level of the second binary-coded signal BIN-2.

[0032] The table below illustrates the above-described conversion between the MLT-3 signal and the two binary-coded signals BIN-1, BIN-2 for the case where the zero signal level of the MLT-3 signal is converted in each case to the zero signal level of the binary-coded signals BIN-1, BIN-2.

TABLE-US-00001 MLT-3 BIN-1 BIN-2 Negative (−1) 0 1 Zero (0) 0 0 Positive (1) 1 0

[0033] In accordance with an alternative embodiment, it would be possible to convert (i) the negative signal level of the MLT-3 signal to the one signal level of a first binary-coded signal BIN-1 and to the zero signal level of a second binary-coded signal BIN-2, (ii) the zero signal level of the MLT-3 signal to the same signal level of the first and second binary-coded signals BIN-1, BIN-2, and (iii) the positive signal level of the MLT-3 signal to the zero signal level of the first binary-coded signal BIN-1 and to the one signal level of the second binary-coded signal BIN-2.

[0034] For the case where the zero signal level of the MLT-3 signal is converted in each case to the zero signal level of the binary-coded signals BIN-1, BIN-2, this would correspond to an interchange of the contents of the columns in the above table for the binary-coded signals BIN-1, BIN-2.

[0035] FIG. 2 is an illustration of an arrangement composed of a comparator and a digital optocoupler, the arrangement being comprised by the device in accordance with FIG. 1, where the digital optocoupler is interconnected with limiting resistors for the purpose of voltage, current and/or power limiting. The comparator 131 and the digital optocoupler 141 are considered by way of example in FIG. 2. The reference signal level VREF at the comparator 131 is “tapped off” from a first voltage source V1 via a voltage divider having 2 resistors 204, 205 and is compared with the differential signal component present at the output terminal 111. In the present exemplary embodiment, a difference between the differential signal component and the reference signal level VREF is amplified. A correspondingly amplified differential signal is supplied to an input-side anode terminal 211 of the digital optocoupler 141.

[0036] Besides the anode terminal 211, the digital optocoupler 141 comprises an input-side cathode terminal 212, a supply voltage terminal 213, an output signal terminal 214 and an output-side ground terminal 215. The cathode terminal 212, the supply voltage terminal 213 and the output signal terminal 215 are each interconnected with a limiting resistor 201, 202, 203. Here, a first limiting resistor 201 is connected between the cathode terminal 212 and ground. A second limiting resistor 202 is connected between the supply voltage terminal 213 and a second voltage source V2, while a third limiting resistor 203 is connected between the output signal terminal 215 and the input terminal 121 of the transmitting unit Tx of the downlink PHY interface device 102. These limiting resistors 201, 202, 203 enable components to be protected against an overload in the case of a fault, without a signal integrity being impermissibly influenced.

[0037] Based on the device for galvanic isolation illustrated in FIG. 1, it is possible to realize a switch 300 for connecting field apparatuses to a 2-wire Ethernet bus system. Here, besides an uplink-side primary switch 301 and a downlink-side secondary switch 302, the switch comprises the PHY interface devices 101, 102 and also a unit 303 for galvanic isolation. In this case, the unit 303 for galvanic isolation comprises the comparators 131, 132, 133, 134 and also the digital optocouplers 141, 142, 143, 144 and is connected both to the uplink PHY interface device 101 on one side and to the downlink PHY interface device 102 on the other side. The uplink PHY interface device 101 is in turn connected to the primary switch 301, while the downlink PHY interface device 102 is connected to the secondary switch 302.

[0038] Thus, while there have been shown, described and pointed out fundamental novel features of the invention as applied to a preferred embodiment thereof, it will be understood that various omissions and substitutions and changes in the form and details of the devices illustrated, and in their operation, may be made by those skilled in the art without departing from the spirit of the invention. For example, it is expressly intended that all combinations of those elements which perform substantially the same function in substantially the same way to achieve the same results are within the scope of the invention. Moreover, it should be recognized that structures and/or elements shown and/or described in connection with any disclosed form or embodiment of the invention may be incorporated in any other disclosed or described or suggested form or embodiment as a general matter of design choice. It is the intention, therefore, to be limited only as indicated by the scope of the claims appended hereto.