SELF-BIASED ACTIVE VOLTAGE DOUBLER FOR ENERGY HARVESTING SYSTEMS

Abstract

An active voltage doubler utilizing a single supply op-amp for energy harvesting system is presented. The active voltage doubler is used for rectification of low power alternating energy sources to achieve both acceptably high power conversion efficiency (PCE) and large rectified DC voltage. The op-amp is self-biased, meaning that no external supply is needed but rather it uses part of the harvested energy for its biasing. Further, the rectified DC voltage is almost twice that of the conventional passive doubler. Power conversion efficiency versus load resistance is plotted and demonstrates that the self-biased active voltage doubler is at least twice as efficient as a conventional passive voltage doubler within the range of 20 to 50 K. The self-biased active voltage doubler achieves maximum power conversion efficiency (PCE) of 61.7% for a 200 Hz sinusoidal input of 0.8V for a 20 K load resistor.

Claims

1. A self-biased active voltage doubler comprising: a clamp capacitor (C.sub.c) having a first connection point and a second connection point; a first NMOS transistor (MN.sub.1) having a drain connected to second connection point of the clamp capacitor and a source connected to ground; a load capacitor having a first end and a second end, wherein the second end is connected to ground; a load resistor (R.sub.L) connected in parallel with the load capacitor; a second NMOS transistor (MN.sub.2) having a source connected to the second connection point of the clamp capacitor (C.sub.C), the source further connected to a gate and a drain connected to the first end of the load capacitor (C.sub.L); and an operational amplifier having an inverting input connected to the second connection point of the clamp capacitor (C.sub.C), a non-inverting input connected to ground, a positive bias point (V.sub.bias) connected to the first end of the load capacitor (C.sub.L), a negative bias point connected to ground and an output (V.sub.o) connected to the gate of the first NMOS transistor (MN.sub.1).

2. The self-biased active voltage doubler of claim 1, wherein the first connection point of the clamp capacitor is connected to a low power source of alternating current.

3. The self-biased active voltage doubler of claim 2, wherein the low power source of alternating current is received from a piezoelectric sensor.

4. The self-biased active voltage doubler of claim 2, wherein the low power source of alternating current is received from a low power antenna.

5. The self-biased active voltage doubler of claim 1, wherein the operational amplifier comprises a first PMOS transistor (M.sub.1) and a second PMOS transistor (M.sub.2), each having a gate connected to ground and a source connected to the first end of the load capacitor C.sub.L; a third NMOS transistor (M.sub.3) having a gate connected to a drain, wherein the drain is connected to the drain of the first PMOS transistor, and a source that provides the inverting input of the operational amplifier; a fourth NMOS transistor (M.sub.4) having a drain connected to the drain of the second PMOS transistor and a source connected to ground; wherein the output (V.sub.o) of the operational amplifier is connected to the drains of the fourth NMOS transistor and the second PMOS transistor.

6. The self-biased active voltage doubler of claim 1, wherein the load resistor (R.sub.L) is a variable resistance.

7. An active rectifier, comprising a first NMOS transistor (MN.sub.1) having a gate, a source and a drain; an operational amplifier having an inverting input, a non-inverting input, a positive bias input, a negative bias input and an output; a clamp capacitor having a first connection point and a second connection point, wherein the second connection point is connected to the drain of the first NMOS transistor and the inverting input; wherein the gate of the first NMOS transistor is connected to the output of the operational amplifier (V.sub.o); wherein the source of the first NMOS transistor and the non-inverting input are connected to ground.

8. The active rectifier of claim 7, wherein the operational amplifier comprises a first PMOS transistor (M.sub.1) and a second PMOS transistor (M.sub.2) having their gates connected to ground and their sources providing the positive bias input point; a second NMOS transistor (M.sub.3) having a gate connected to a drain, wherein the drain is connected to the drain of the first PMOS transistor, and wherein the source provides the inverting input of the operational amplifier; a third NMOS transistor (M.sub.4) having a drain connected to the drain of the second PMOS transistor and a source connected to ground; wherein the output (V.sub.o) of the operational amplifier is connected to the drains of the fourth NMOS transistor and the second PMOS transistor.

9. The active rectifier of claim 7, wherein the first connection point of the clamp capacitor is connected to a low power source of alternating current.

10. The active rectifier of claim 9, wherein the low power source of alternating current is received from a piezoelectric sensor.

11. The active rectifier of claim 9, wherein the low power source of alternating current is received from a low power antenna.

12. A method for harvesting energy with a self-biased active voltage doubler, comprising: charging a clamp capacitor of a self-biased active voltage doubler by a source of low power alternating electrical current to an input voltage, V.sub.in; rectifying the current through a first diode connected NMOS transistor whose gate is connected to the output of an op-amp; charging a load capacitor during a first half cycle of the alternating current to a first negative voltage; charging the load capacitor and rectifying the current during a second half cycle of the alternating current to a second negative voltage through a second diode connected NMOS transistor; self-biasing the op-amp at the positive bias point by the voltage of the load capacitor; wherein the voltage of the load capacitor provides the output of the self-biased active voltage doubler; and wherein the output voltage V.sub.out is double the input voltage V.sub.in across the clamp capacitor.

13. The method for harvesting energy of claim 12, further comprising receiving a low power source of alternating current at the first connection point of the clamp capacitor.

14. The method for harvesting energy of claim 13, further comprising receiving the low power source of alternating current from a piezoelectric sensor.

15. The method for harvesting energy of claim 13, further comprising receiving the low power source of alternating current from a low power antenna.

16. The method for harvesting energy of claim 12, further comprising tuning the amplitude of the output voltage V.sub.out by adjusting a variable resistance connected in parallel with the load capacitor.

17. The method for harvesting energy of claim 12, further comprising tuning the output resistance by adjusting a variable resistance connected in parallel with the load capacitor.

18. A method of voltage doubling with the self-biased active voltage doubler of claim 1, comprising: connecting an alternating current power source to the first connection point of the clamp capacitor, thus charging the clamp capacitor; controlling the gate of a first diode connected transistor with the output voltage V.sub.o of an operational amplifier; charging the load capacitor by the first diode connected transistor during a first half cycle of the alternating current; charging the load capacitor by the second diode connected transistor during a second half cycle of the alternating current; wherein charging the load capacitor rectifies the alternating current to provide a rectified voltage output, V.sub.out.

19. The method of voltage doubling of claim 18, further comprising tuning the output voltage V.sub.out by adjusting a variable resistance connected in parallel with the load capacitor.

20. The method of voltage doubling of claim 18, further comprising tuning the output resistance by adjusting a variable resistance connected in parallel with the load capacitor.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0014] A more complete appreciation of this disclosure and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein:

[0015] FIG. 1 illustrates a traditional passive voltage doubler;

[0016] FIG. 2 illustrates a voltage waveform across a first ideal diode;

[0017] FIG. 3 illustrates a simple diode-connected voltage doubler;

[0018] FIG. 4 illustrates a self-biased active voltage doubler of the present disclosure;

[0019] FIG. 5 is a graph illustrating simulated voltage waveforms when V.sub.in=0.8 V:

[0020] FIG. 6 illustrates a single supply op-amp;

[0021] FIG. 7 is a graph illustrating a simulated frequency response of the differential amplifier;

[0022] FIG. 8 is a graph illustrating the simulated output voltage with respect to the input voltage;

[0023] FIG. 9 is a graph illustrating power conversion efficiency (PCE) as a function of load resistance (R.sub.L).

DETAILED DESCRIPTION

[0024] In the drawings, like reference numerals designate identical or corresponding parts throughout the several views. Further, as used herein, the words a, an and the like generally carry a meaning of one or more, unless stated otherwise. The drawings are generally drawn to scale unless specified otherwise or illustrating schematic structures or flowcharts.

[0025] Furthermore, the terms approximately, approximate, about, and similar terms generally refer to ranges that include the identified value within a margin of 20%, 10%, or preferably 5%, and any values therebetween.

[0026] Aspects of this disclosure are directed to a self-biased active voltage doubler, an active rectifier for use in a self-biased voltage doubler and a for using a self-biased active voltage doubler to harvest energy.

[0027] Power originating from vibration energy sources may be unregulated, alternating, and may be small. Therefore, in such situations it is necessary to increase the power conversion efficiency of the rectifier of a voltage doubler. As the output of a precision rectifier can be an the input of a next stage or used to power another active element, larger power conversion efficiency is required so that next stage receives higher DC output voltage at a feasible efficiency. If the power conversion efficiency of the first stage is low, then second stage may not be able to be utilized for further operation.

[0028] Maximization of the power conversion efficiency relies on the performance of the rectifier circuit. Enhancement in the power conversion efficiency of the rectifier may be considered as a powerful tool in increase the efficiency of an entire system, as the performance of a front-end is often limited by regional regulation. For example, the maximum power transmission allowed in the Japan and United Stales is 4 W.

[0029] The power conversion efficiency (PCE) of a rectifier circuit is defined as the ratio of the output power to the input power. The input power equals the loss in the rectifier plus the output power. Thus, power conversion efficiency can be expressed as

[00001]$\begin{array}{cc}\mathrm{PCE}=\frac{P_{\mathrm{OUT}}}{P_{\mathrm{IN}}}=\frac{P_{\mathrm{OUT}}}{\left(P_{\mathrm{OUT}}+P_{\mathrm{LOSS}}\right)}.& \left(1\right)\end{array}$

[0030] Further elaborating on the definition, P.sub.LOSS is defined as

P.sub.LOSS=N.Math.P.sub.DIODE. (2)

[0031] P.sub.DIODE is the loss in the diode and N is the total number of diode stages. When current flows through the diode, the resistive loss generates a diode loss and is expressed as

P.sub.DIODE=P.sub.FWD+P.sub.REV. (3)

[0032] P.sub.FWD is the diode forward drop and P.sub.REF is the diode reverse drop, which are found from the diode voltage turn-on and the diode leakage reverse current. Therefore, less forward voltage drop and less reverse leakage current are needed to realize a large power conversion efficiency of the harvesting system.

[0033] A conventional passive voltage doubler circuit is shown in FIG. 1. (See Adel S. S. and Kenneth C. S., Microelectronic Circuits, Oxford University Press. 6th edition, 2009, incorporated herein by reference in its entirety).

[0034] The circuit is a combination of two cascaded parts the clamp circuit formed by C.sub.1 and D.sub.1, and the peak rectifier circuit formed by C.sub.2 and D.sub.2. Diode D.sub.1 102 conducts during the positive half cycle, storing input voltage in C.sub.1. Assuming ideal diodes, the clamped output voltage V.sub.D1 is shown in FIG. 2 when a sinusoidal input is applied.

[0035] Diode D.sub.2 104 conducts during the negative half cycle which results in a negative peak of 2V.sub.in while the positive peak is clamped to 0V. The output of the peak detector at C.sub.2 yields DC voltage of 2V.sub.in. The circuit is known as a voltage doubler since the output voltage, in the ideal case, has twice the amplitude as the input voltage. In practice, the DC output voltage is 2V.sub.in plus two forward biased diode voltage drops. For large AC input signals, the diode drops may be neglected. However, the forward biased diode voltage drops represent major loss factors in the output voltage and the efficiency of the circuit.

[0036] A diode-connected transistor is a method of creating a two-terminal rectifying device (a diode) out of a three-terminal transistor. A characteristic of diode-connected transistors is that they are always in the saturation region for metal-oxide-semiconductor field-effect transistors (MOSFETs). A diode-connected transistor is made by connecting the gate and drain of a MOSFET.

[0037] In FIG. 3, the diodes (102, 104) are replaced by diode-connected MOS transistors (302, 304), i.e., their sources (S) are connected to their gates (G). The diode-connected NMOS transistors are attached in series and an intermediate node is linked to the input terminal via coupling capacitor C.sub.C.

[0038] The effective turn-on voltage of the diode-connected MOS transistor is practically equivalent to V.sub.th of the MOS transistor, which is smaller than a pn-junction diode, however for the most part larger than a Schottky diode. Thus, a rectifier using this straightforward diode-connected MOS setup achieves neither large voltage nor large power conversion efficiency.

[0039] Different energy sources have different types of transducers. An RF transducer is equivalent to an antenna whose power is very small. It may be fed to an impedance matching circuit and a PCB balun to obtain the appropriate AC voltage. (See S. Scorcioni. L. Larcher, and A. Bertacchini, A reconfigurable differential CMOS RF energy scavenger with 60% peak efficiency and 21 dBm sensitivity, IEEE Microwave and Wireless Components Letters, vol. 23, no. 3, pp. 155-157, 2013, incorporated herein by reference in its entirety). This voltage signal is then applied to the input of a rectifier. The matching network circuit is not shown, as it is incidental to the self-biased active voltage doubler of the present disclosure.

[0040] The piezoelectric transducer (not shown) which generates the alternating voltage commonly includes a cantilever capacitance and is used at a low operating frequency. The type of PE is often called a bimorph. The bimorph is a cantilever used for actuation or sensing which consists of two active layers. It can also have a passive layer between the two active layers. In a non-limiting example, the piezoelectric transducer may be of the type manufactured by Steminc, Steiner & Martins, Inc. and referred to as Piezo Bimorph Disc Actuator SMBA21T20KP https://www.steminc.com/PZT/en/piezo-bimorph-disc-actuator-2120mm. The PE may be an array of piezoelectric transducers. The self-biased active voltage double of the present disclosure is not limited by the source of the electrical signals generated.

[0041] FIG. 4 shows the proposed self-biased active voltage doubler circuit. NMOS transistor MN.sub.1 402 is connected as a diode (the gate and source are connected) and the circuit has the configuration of an inverting super diode with only one op-amp 406 that is used for the active rectification purpose to achieve large power conversion efficiency. The other NMOS transistor MN.sub.2 404 is connected to the load capacitance C.sub.L and a load resistor R.sub.L, thus forming an active voltage doubler. The load resistor R.sub.L may be configured as a variable resistance.

[0042] There is no additional DC power supply needed to bias the op-amp; instead the bias voltage is obtained from a portion of the harvested energy. Therefore, the op-amp must be biased from a single positive supply with the negative bias connected to ground. The output DC voltage V.sub.out is connected to V.sub.dd of the op-amp, therefore the active voltage doubler circuit is self-biasing due to this incorporated active op-amp.

[0043] The active op-amp will not work during start-up as the input voltage is not large enough to supply biasing to the op-amp. The energy stored in the capacitor is small and the op-amp requires a threshold value of DC voltage to operate. Thus, during the startup, the operation of the voltage doubler is governed by the body source voltage of diode MN.sub.1 402. The active doubler circuit can be modelled as two parallel rectifier stages: a passive rectifier which only works during startup and a high efficiency active rectifier which dominates when the op-amp starts working.

[0044] The operation of the self-biased active doubler circuit is explained as follows and is illustrated in FIG. 5. In each input cycle, one of the NMOS diode connected transistors is ON and other is OFF. During startup, when the voltage input cycle is positive, MN.sub.2 is ON, storing energy in C.sub.L, while MN.sub.1 is OFF. Note that the source of MN.sub.2 is connected to the negative contact of the capacitor C.sub.C. In the negative half cycle, MN.sub.1 conducts due to the body source voltage while MN.sub.2 turns OFF. The energy stored in capacitance C.sub.L is fed back to bias the op-amp. The op-amp requires a certain threshold of DC voltage to function properly. The op-amp signal predominates the rectification when the op-amp receives enough voltage to provide its bias. The output V.sub.o of the op-amp is connected to the gate of NMOS switch MN.sub.1. When the AC input is positive, the output of the op-amp becomes zero as the configuration is inverting (as the voltage seen by the op-amp at the inverting input is negative), therefore diode connected transistor MN.sub.1 is cut off as its gate voltage is zero. The output of op-amp 406 does not go into the negative saturation level. The op-amp output V.sub.o is zero during this half cycle as the op-amp has a single bias supply voltage (due to the grounding of the negative bias point) which reduces the reverse leakage loss. The AC input voltage passes through diode connected transistor MN.sub.2 to charge output storage capacitance C.sub.L with some loss due to the ON resistance of the diode connected transistor. When the AC input is negative, the output V.sub.o of the op-amp increases, turning MN.sub.1 ON, the voltage drop at MN.sub.1 is reduced and diode connected transistor MN.sub.2 is cut off. The output V.sub.out decreases slowly and rises again when the next input positive cycle comes.

[0045] Simple diode-connected NMOS transistor MN.sub.2 is not configured as a super diode. The principle of the doubler circuit is that only one of the diode connected transistors should be conducting during specific half cycle. If MN.sub.2 is setup as active diode connected transistor as is MN.sub.1, the two diode connected transistors MN.sub.1 and MN.sub.2 would both be either ON or OFF simultaneously during any specific cycle. During a positive half cycle, both transistors would be OFF and both would ON during negative cycle, since both the active diode connected transistors have same type of configuration and are the same type of transistors. Similarly, the same problem occurs even if MN.sub.1 is used as a passive diode connected transistor and MN.sub.2 as an active diode connected transistor and the reason is the same that both active diode connected transistors are simultaneously ON.

[0046] Some of the harvested energy is used to operate the op-amp, so its energy consumption should be as small as possible. The main hurdle in op-amp based active rectifiers is that the op-amp itself requires a DC power supply. There are two drawbacks if a DC power supply is used for op-amp. First, an additional element and an additional price are added every time the circuit is utilized for certain application. Second, the addition of an external DC supply means that the system is not truly harvesting energy.

[0047] The above-mentioned drawbacks can be eliminated if the DC supply of the op-amp based rectifier is provided by the harvested energy. The stored energy in the capacitor C.sub.L supplies the necessary positive DC voltage to bias the op-amp. Hence, the bias voltage of the op-amp must be configured as a single ended supply as only positive DC rectified voltage is fed back from the output of the active doubler. The power consumption of the op-amp must be less that of the rest of the circuit. In this situation, the power conversion efficiency is high.

[0048] Although the dual supply op-amp is advantageous in some implementations, there are many applications where single supply op-amp is required. For example, in marine and automotive equipment, battery power provides a single supply. One of the main advantages of a single supply op-amp is low power consumption, hence it is useful for low power applications such as biomedical implants and wireless sensor nodes. However, a single supply op-amp needs appropriate signal biasing; otherwise the op-amp becomes unstable or does not provide the desired output. A single supply differential pair MOS configuration is op-amp is used as shown in FIG. 6. (See E. Dallago, D. Miatton, G. Venchi et al., Active self supplied AC-DC converter for piezoelectric energy scavenging systems with supply independent bias, in Proceedings of the 2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008, pp. 1448-1451, USA, May 2008, incorporated herein by reference in its entirety).

[0049] The op amp 606 as shown in FIG. 6 is ground compatible because the input voltage V.sub.dd is fed from storage capacitance as shown in FIG. 4, and the op amp and capacitor are both referenced to ground. The op amp of the present disclosure is designed to work with the lowest possible value of voltage bias. Therefore, the self-biased active voltage doubler performs at a much higher efficiency level than does the prior art passive voltage doubler of FIG. 1 once a low level of charge has been stored in capacitance C.sub.L. Matched NMOS input differentials (M.sub.3 and M.sub.4) are used and the non-inverting and inverting inputs are fed into sources of these transistors. The active loads are the PMOS transistors (M.sub.1 and M.sub.2). The sources of these PMOS transistors are connected together and are connected to the DC power supply V.sub.dd coming from the storage capacitance C.sub.L. All the transistors are in pinch-off condition and the op-amp has been carefully adjusted for best performance.

[0050] The first embodiment is illustrated with respect to FIG. 4 and FIG. 6. The first embodiment describes a self-biased active voltage doubler comprising a clamp capacitor (C.sub.C) having a first connection point (+) and a second connection point (); a first NMOS transistor 402 (MN.sub.1) having a drain connected to second connection point of the clamp capacitor and a source connected to ground. A load capacitor (C.sub.L) is shown having a first end and a second end, wherein the second end is connected to ground. A load resistor (R.sub.L) is connected in parallel with the load capacitor.

[0051] A second NMOS transistor (MN.sub.2) has a source connected to the second connection point of the clamp capacitor (C.sub.C), a source further connected to a gate and a drain connected to the first end of the load capacitor (C.sub.L).

[0052] An operational amplifier is connected at an inverting input (see minus sign of 406) to the second connection point of the clamp capacitor (C.sub.C), a non-inverting input (see plus sign of 406) connected to ground, a positive bias point (V.sub.bias) connected to the first end of the load capacitor (C.sub.L), a negative bias point connected to ground and a output (V.sub.o) connected to the gate of the first NMOS transistor (MN.sub.1).

[0053] The first connection point of the clamp capacitor is connected to a low power source of alternating current, which may be received from a piezoelectric sensor or from a low power antenna.

[0054] The operational amplifier comprises a first PMOS transistor (M.sub.1) and a second PMOS transistor (M.sub.2) having their gates connected to ground (note that their gates are tied together in mirror fashion in FIG. 6) and their sources tied together and connected to the first end of the load capacitor C.sub.L.

[0055] A third NMOS transistor (M.sub.3) has a gate connected to a drain. A drain is connected to the drain of the first PMOS transistor, and a source provides the inverting input of the operational amplifier. A fourth NMOS transistor (M.sub.4) has a drain connected to the drain of the second PMOS transistor and a source connected to ground.

[0056] The output (V.sub.o) of the operational amplifier is connected to the drains of the fourth NMOS transistor and the second PMOS transistor.

[0057] The load resistor (R.sub.L) may be a variable resistance.

[0058] The second embodiment is illustrated with respect to FIG. 4 and FIG. 6. The second embodiment describes an active rectifier, comprising a first NMOS transistor (MN.sub.1) having a gale, a source and a drain, an operational amplifier having an inverting input, a non-inverting input, a positive bias input, a negative bias input and an output, a clamp capacitor having a first connection point and a second connection point, wherein the second connection point is connected to the drain of the first NMOS transistor and the inverting input. The gate of the first NMOS transistor is connected to the output of the operational amplifier (V.sub.o) and the source of the first NMOS transistor and the non-inverting input are connected to ground.

[0059] The operational amplifier comprises a first PMOS transistor (M.sub.1) and a second PMOS transistor (M.sub.2) having their gates connected to ground and their sources providing the positive bias input point, a second NMOS transistor (M.sub.3) having a gate connected to a drain, wherein a drain is connected to the drain of the first PMOS transistor, and wherein a source provides the inverting input of the operational amplifier. A third NMOS transistor (M.sub.4) has a drain connected to the drain of the second PMOS transistor and a source connected to ground. The output (V.sub.o) of the operational amplifier is connected to the drains of the fourth NMOS transistor and the second PMOS transistor.

[0060] The first connection point of the clamp capacitor is connected to a low power source of alternating current, which may be received from a piezoelectric sensor or from a low power antenna.

[0061] The third embodiment is illustrated with respect to FIG. 4 to FIG. 6. The first embodiment describes a method for harvesting energy with a self-biased active voltage doubler, and comprises providing a source of low power alternating electrical current to charge a clamp capacitor of the a self-biased active voltage doubler to an input voltage, V.sub.in, rectifying the current through a first diode connected NMOS transistor 402 whose gate is connected to the output of an op-amp 406, charging a load capacitor C.sub.L during a first half cycle of the alternating current to a first negative voltage, charging the load capacitor and rectifying the current during a second half cycle of the alternating current to a second negative voltage through a second diode connected NMOS transistor, self-biasing the op-amp at the positive bias point by the voltage of the load capacitor, wherein the voltage of the load capacitor provides the output of the self-biased active voltage doubler and wherein the output voltage V.sub.out is double the input voltage V.sub.in across the clamp capacitor.

[0062] The method continues by receiving a low power source of alternating current at the first connection point of the clamp capacitor, from either a piezoelectric sensor or a low power antenna.

[0063] The method continues by tuning the amplitude of the output voltage V.sub.out by adjusting a variable resistance connected in parallel with the load capacitor and/or tuning the output resistance by adjusting a variable resistance connected in parallel with the load capacitor.

[0064] A more general method of voltage doubling with the self-biased active voltage doubler described above comprises connecting an alternating current power source to the first connection point of the clamp capacitor, thus charging the clamp capacitor, controlling the gate of a first diode connected transistor with the output voltage V.sub.o of an operational amplifier, charging the load capacitor by the first diode connected transistor during a first half cycle of the alternating current, charging the load capacitor by the second diode connected transistor during a second half cycle of the alternating current, wherein charging the load capacitor rectifies the alternating current to provide a rectified voltage output, V.sub.out.

[0065] The method of using the self-biased active voltage doubler described above continues by tuning the amplitude of the output voltage V.sub.out by adjusting a variable resistance connected in parallel with the load capacitor and/or tuning the output resistance by adjusting a variable resistance connected in parallel with the load capacitor.

[0066] In a non-limiting example of a simulated frequency response analysis, the op-amp is powered with a 0.6V DC supply and transistor widths and lengths are all set to 1 m except for PMOS active load transistors M.sub.1 and M.sub.2 whose length is set to 0.3 m. Note that M.sub.1 and M.sub.2 are transistors within the op-amp as shown in FIG. 6 and are not the same as MN.sub.1 and MN.sub.2 of FIG. 4. The gain and phase response of the op-amp 606 are simulated as shown in FIG. 7.

[0067] The gain of the op-amp is 41 dB and the unity gain frequency is 110 MHz. The current consumption of the op-amp is 200 nA at 0.6V supply and the current increases with the supply voltage. The DC supply V.sub.DD is used for the simulation only. In the design of the present disclosure, the op-amp is self-biased as explained with respect to FIG. 4 and FIG. 6.

[0068] The simulation results of the op-amp of FIG. 4 are compared with simulation of the passive voltage doubler circuit of FIG. 1. A piezoelectric (PE) transducer is employed as the input as it provides high output efficiency. PE transducers are able to harvest energy from a button press action and produce high inputs at low frequency. (See X.-D. Do, H.-H. Nguyen, S.-K. Han, and S.-G. Lee, A rectifier for piezoelectric energy harvesting system with series Synchronized Switch Harvesting Inductor, in Proceedings of the 2013 9th IEEE Asian Solid-State Circuits Conference, A-SSCC2013, pp. 269-272. Singapore, November 2013, incorporated herein by reference in its entirety). The transducer is simulated by an AC voltage source since the transducer output is an alternating electrical signal. The simulation results demonstrated in this section are carried out using Cadence Virtuoso Simulator with LF 0.15 m CMOS process technology. The op-amp transistor widths and lengths are all set to 1 m except for PMOS length which is set at 0.3 m. The active voltage doubler circuit operates at 200 Hz with a 0.8V input supply. The storage capacitor C.sub.L is set to 1 F and R.sub.L=20 K. The NMOS transistor ratios are set to 18/0.15. The threshold voltages NMOS and PMOS are 0.5V and 0.56V in a standard LF 0.15 m CMOS process technology.

[0069] FIG. 5 shows the voltage waveforms of the simulated self-biased active voltage doubler at steady state. The output voltage is 0.98V with V.sub.in=0.8V.

[0070] The self-biased active voltage doubler achieves a power conversion efficiency (PCE) of 61.7% at R.sub.L=20 K. This efficiency is double that of the passive voltage doubler. A conventional passive voltage doubler yields a PCE of 30% at R.sub.L=20 K, with a rectified output voltage of 0.48V, as shown in FIG. 8.

[0071] The output voltage graph with respect to the input voltage is simulated and shown in FIG. 8. Below 0.5 V input voltage, the output voltages are negligible, that is, less than 0.1V, and also have less PCE. The output voltage increases sharply beyond 0.5V resulting in higher power conversion efficiency, as the active rectifier begins operating. At 0.6V input voltage, the output voltage is 0.66V with PCE of 57% and then increases linearly with a slope of two for each 0.1V input voltage. At 0.8V the output voltage is 0.98V and continues to increase linearly for higher inputs. The output voltage is compared with that of the passive voltage doubler circuit and gives output voltage of 0.2V with PCE of 17% at 0.6 V input voltage. The output voltages of the self-biased active voltage doubler circuit of the present disclosure are greater than those of the traditional passive voltage doubler for all input range.

[0072] The power conversion efficiency of the self-biased active voltage doubler depends upon the output loading condition (different output loads) and its simulation is demonstrated in FIG. 9. The input amplitude is 0.8V. The active doubler achieves maximum PCE of 61.7% at R.sub.L=20 k and it extracts power of 39.36 W. This relates to input power of about 64 W (11.94 dBm). The PCE decreases with the load resistance due to maximum power transfer from impedance matching. When the rectifier input impedance equals the output impedance, maximum power is transferred to the load which leads to the high efficiency of the rectifier at that particular point. When there is variation between the input and output impedances, the PCE varies. The resistance R.sub.L is variable, allowing tuning of the output impedance to match the input impedance of a device connected to the active voltage doubler. The variable resistance serves two purposes: it acts to provide output amplitude adjustment as well as output impedance tuning. The power conversion efficiency of the conventional active doubler employing diode-connected MOS transistors (FIG. 3) is 30% at 20 k and it extracts 10.4 W of power from the piezoelectric vibrations. Further, the self-biased active doubler performs better than the conventional passive voltage doubler for all loads.

[0073] Comparison of the self-biased active voltage doubler with previous works can be seen in Table 1. (See Y. Sun, N. H. Hieu, C.-J. Jeong, and S.-G. Lee. An integrated high-performance active rectifier for piezoelectric vibration energy harvesting systems. IEEE Transactions on Power Electronics, vol. 27. no. 2, pp. 623-627, 2012; Do et al. A self-powered high-efficiency rectifier with automatic resetting of transducer capacitance in piezoelectric energy harvesting systems, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, no. 3. pp. 444-453, 2015); and X.-D. Do. H.-H. Nguyen, S.-K. Han. and S.-G. Lee, A rectifier for piezoelectric energy harvesting system with series Synchronized Switch Harvesting Inductor, in Proceedings of the 2013 9th IEEE Asian Solid-State Circuits Conference. A-SSCC2013, pp. 269-272, Singapore, November 2013, each incorporated herein by reference in its entirety).

TABLE-US-00001 TABLE 1 COMPARISON WITH PREVIOUS RECTIFIERS Present Reference (Sun) FIG. 3 (Do) 2015 (Do) 2013 Disclosure Year 2012 2015 2013 2017 Technology 0.18 m 0.18 m 0.35 m 0.15 m Topology Op-amp based Self-Powered Series SSHI Self-Biased active rectifier Rectifier Doubler Input 2.8 V 3 V 3.7 V 0.8 V voltage Operating 200 Hz 200 Hz 200 Hz 200 Hz frequency Output 2.78 V 2.9 V 3.63 V 0.98 V voltage Area 0.24 mm.sup.2 0.016 mm.sup.2 0.016 mm.sup.2 0.001 mm.sup.2 PCE 90% 91.2% 90% 61.7% Inductor No No Yes No Load R.sub.L = 95 k R.sub.L = 100 k R.sub.L = 160 k R.sub.L = 20 K C.sub.L = 1 F C.sub.L = 1 F

[0074] There are previously known voltage rectifiers which give high efficiency around 90%, however these designs are built for high input voltages (around 3V) and provide lower DC outputs than the input signal amplitudes, thus are not suitable for energy harvesting. The self-biased active voltage doubler of the present disclosure yields 61.7% power efficiency with small input voltages of about 0.8V and yields a rectified output voltage of 0.98V. Therefore, the self-biased active voltage doubler of the present disclosure may be used with low input voltage sources, such as piezoelectric signals from mechanical vibrations, and provides doubled output voltage.

[0075] The self-biased active voltage doubler of the present disclosure is suited for low power energy harvesting system applications. The active doubler starts to operate 0.5V input and achieves larger PCE at high inputs. The voltage doubler of the present disclosure achieves power conversion efficiency (PCE) of 61.7% under the condition of 200 Hz operating frequency, 0.8V input signal with a 20 k load resistor. The power conversion efficiency is double that of the passive voltage doubler. The self-biased active voltage doubler circuit has application in biomedical devices and wireless sensor nodes for direct powering or to charge a rechargeable battery. The self-biased active voltage doubler can be scaled to a multistage rectifier circuit design that provides larger DC output voltages to power remote devices while maintaining acceptable power conversion efficiency.

[0076] Obviously, numerous modifications and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims, the invention may be practiced otherwise than as specifically described herein.