System and method for regulating transfer characteristics of integral analog-to-digital converter

Abstract

A system and method for regulating transfer characteristics of an integral analog-to-digital converter are provided. The system comprises a cascade N-stage integrator structure having N integrators, the input end of the first integrator is connected to a voltage, the output end of each integrator is connected to the input end of the adjacent integrator, and the output end of the Nth integrator is connected to an output node (VRAMP). Wherein, the N is positive integer greater than or equal to 2. In the cascade multistage integrator structure, the voltage of the output node (VRAMP) is in direct proportion relation with the time to the power of N. By adopting a cascade multistage integrator according to the present disclosure, it is simple to regulate transfer characteristics of the ADC, and the cascade digital signal processing is convenient, which can reduce the ADC conversion time and improve the ADC conversion rate. Compared with the existing polyline mode, the present disclosure has better linearity; and it can be easily extended to cascade multistage integrators.

Claims

1. A system for regulating transfer characteristics of an integral analog-to-digital converter, comprising: a cascade N-stage integrator structure having N integrators, the input end of the first integrator is connected to a voltage, the output end of each integrator is connected to the input end of the adjacent integrator, and the output end of the Nth integrator is connected to an output node (VRAMP), wherein the N is a positive integer and larger than or equal to 2; in the cascade N-stage integrator structure, the voltage of the output node (VRAMP) is in direct proportion relation with the time to the power of N.

2. The system of claim 1, wherein, each integrator comprises a resistor, a capacitor, an operational transconductance amplifier and a switch; wherein, for each integrator, the positive input end of the operational transconductance amplifier is connected to the common mode voltage (VCM); one end of the resistor is connected to the reverse input end of the operational transconductance amplifier at a node, the two ends of the capacitor are connected to the node and the output end of the operational transconductance amplifier respectively; the two ends of the switch is connected to the two ends of the capacitor in parallel, and the other end of the resistor is connected to the input end of the integrator; the output end of the operational transconductance amplifier is connected to the input end of the adjacent integrator.

3. The system of claim 2, wherein the number of the integrators is three.

4. The system of claim 1, wherein the number of the integrators is three.

5. A method for regulating transfer characteristics of an integral analog-to-digital converter by using adjusting system of claim 1, comprising: forming the cascade N-stage integrator structure using N integrators; connecting the input end of the first integrator with a voltage; connecting the output end of the Nth integrator to an output node (VRAMP), and connecting the output end of each integrator with the input end of the adjacent integrator, so that the voltage changes of the output of the Nth integrator, namely the output node VRAMP, is in direct proportion with time to the power of N.

6. The method of claim 5, wherein, each integrator comprises a resistor, a capacitor, an operational transconductance amplifier and a switch; wherein for each integrator, the positive input end of the operational transconductance amplifier is connected to a voltage source (VCM), and one end of the resistor is connected to the reverse input end of the operational transconductance amplifier at a node, and the two ends of the capacitor are connected to the node and the output end of the operational transconductance amplifier respectively; and the switch is connected to the two ends of the capacitor in parallel, and the other end of the resistor is connected to the input end of the integrator; the output end of the operational transconductance amplifier is connected to the input end of the adjacent integrator.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) In order to better understand the purpose, characteristics and advantages of the present disclosure, the following is a detailed description of preferred embodiments of the present disclosure in combination with the attached drawings, wherein:

(2) FIG. 1 is a schematic structural diagram of a traditional single integral ADC

(3) FIG. 2 is a working principle diagram of a traditional single integral ADC

(4) FIG. 3 is a schematic diagram of a traditional generation mode of the reference voltage VRAMP of the integral ADC

(5) FIG. 4 is a working principle diagram of an existing method for regulating transfer characteristics of an integral analog-to-digital converter

(6) FIG. 5 is a working principle diagram of a method for regulating transfer characteristics of an integral analog-to-digital converter according to a preferred embodiment of the present disclosure

(7) FIG. 6 is a schematic diagram of a system for regulating transfer characteristics of an integral analog-to-digital converter according to a preferred embodiment of the present disclosure

(8) FIG. 7 is a specific circuit structure diagram of a reference voltage VRAMP generating mode in a method for regulating transfer characteristics of an integral analog-to-digital converter according to a preferred embodiment of the present disclosure

(9) FIG. 8 is a schematic diagram of a reference voltage VRAMP generated by three-times extended iterative according to an embodiment of the present disclosure

(10) FIG. 9 is a specific circuit structure diagram of a reference voltage VRAMP generated by three-times extended iterative according to an embodiment of the present disclosure

(11) FIG. 10 is a schematic diagram of a reference voltage VRAMP generated by N-time extended iterative according to an embodiment of the present disclosure

DETAILED DESCRIPTION

(12) In order to make the content of the invention clearer and easier to understand, the following is a further explanation of the content of the invention combined with the attached drawings of the manual. Of course, the invention is not limited to the specific embodiment, and the general replacement familiar to the person having ordinary skill in the art is also covered by the protection scope of the invention.

(13) In the invention, a system for regulating transfer characteristics of an integral analog-to-digital converter has a cascade N-stage integrator structure formed by N integrators, the input end of the first integrator is connected to a reference voltage, the output end of each integrator is connected to the input end of an adjacent integrator, and the output end of the Nth integrator is connected to an output node (VRAMP). Wherein N is a positive integer and larger than or equal to 2. In the cascade N-stage integrator, the voltage change of the output node (VRAMP) is in direct proportion relation with the time to the power of N.

(14) In one embodiment, each integrator includes a resistor, a capacitor, an operational transconductance amplifier, and a switch. Wherein, for each integrator, the positive input end of the operational transconductance amplifier is connected to a the common mode voltage (VCM), one end of the resistor is connected to the reverse input end of the operational transconductance amplifier at a node, the two ends of the capacitor are connected to the node and the output end of the operational transconductance amplifier respectively; the switch is connected to the two ends of the capacitor in parallel, and the other end of the resistor is connected to the input end of the integrator; the output end of the operational transconductance amplifier is connected to the input end of the adjacent integrator.

(15) The present disclosure is described in further detail below with reference to FIGS. 5-10 and specific embodiments. It should be noted that the FIGs are in a very simplified form, and the non-precise proportion is used, and are only used for conveniently and clearly achieving the purpose of assisting in describing the embodiment of the present disclosure.

(16) In this embodiment, the integral analog-to-digital converter having two integrators is used as an example for description. Please refer to FIG. 6 and FIG. 7, FIG. 6 is a schematic diagram of a system for regulating transfer characteristics of an integral analog-to-digital converter according to a preferred embodiment of the present disclosure, FIG. 7 is a specific circuit structure diagram of a reference voltage VRAMP generating mode in a method for regulating transfer characteristics of an integral analog-to-digital converter according to a preferred embodiment of the present disclosure. The cascaded two-stage integrator structure has two integrators (an integrator 1 and an integrator 2). The integrator 1 includes an operational transconductance amplifier OTA1, a resistor R1, a capacitor C1 and a switch S1. The reverse input end of the operational transconductance amplifier OTA1 is connected to the node V1, the positive input end of the operational transconductance amplifier OTA1 is connected to a voltage source VCM, and the output end of the operational transconductance amplifier OTA1 is connected to the output node (VRAMP), the two ends of the capacitor C1 are connected to the node V1 and the node VRAMP respectively, the two ends of the switch S1 are connected to connect the node V1 and the node VRAMP respectively, and the two ends of the resistor R1 are connected to the node V1 and the node Vref1 respectively. Wherein the node Vref1 is the input voltage of the integrator 1 and is also the output end voltage of an integrator 2. The integrator 2 is composed of an operational amplifier OTA2, a resistor R2, a capacitor C2 and a switch S2. The reverse input end of the OTA2 is connected to a node V3, and the positive input end of the OTA2 is connected to a voltage source VCM, the output end of the operational amplifier OTA2 is connected to the node Vref1, and the two ends of the capacitor C2 are connected to the node V3 and the node Vref1 respectively, the two ends of the switch S2 are connected to the node V3 and the node Vref1 respectively, and the two ends of the resistor R2 are connected to the node V3 and the node Vref respectively, wherein the node Vref is input reference voltage.

(17) Refer to FIG. 5 combined with FIG. 6 and FIG. 7, in the cascaded two-stage integrator structure composed of the two integrators, the integrator 2 is used for achieving the final voltage of the output node (VRAMP) is in direct proportion relation with the time to the power of 2. According to the properties of the integrator, when the VRAMP voltage starts to change with time, the output voltage is expressed as follows:

(18) $\begin{array}{cc}\mathrm{Vref}1=\mathrm{VCM}+\frac{\left(\mathrm{Vref}-V3\right)}{R2}*C2*t,& \\ \mathrm{VRAMP}=\mathrm{VCM}+\frac{\left(\mathrm{Vref}1-V1\right)}{R1}*C1*t,& \end{array}$

(19) Wherein the common mode voltage VCM is taken as the initial voltage of the VRAMP, that is, when the t=0, the VRAMP=VCM.

(20) In addition, according to the virtual short characteristic of the input end of the operational transconductance amplifier, the V1=VCM, the formula {circle around (6)} and the formula {circle around (7)}, the formula {circle around (8)} can be obtained as follows:

(21) $\begin{array}{cc}\mathrm{VRAMP}=\mathrm{VCM}+\frac{\left(\mathrm{Vref}-\mathrm{VCM}\right)}{R1*R2}*C1*C2*t^2,& \end{array}$

(22) As shown in the formula {circle around (8)}, the follow-up of the voltage VRAMP is the quadratic term of time t, which can be used as the reference voltage of the integral ADC to realize the function of regulating transfer characteristics of the integral ADC.

(23) According to the working principle of the ADC, the follow-up of the voltage VRAMP in the above formula {circle around (8)}, namely the time t.sup.2, can be used as the reference voltage of the integral ADC. The VCM is just the initial voltage of the VRAMP. When the input of the ADC is VIN, the effective counting time t of the counter in the ADC is:

(24) $\mathrm{VIN}=\frac{\left(\mathrm{Vref}-\mathrm{VCM}\right)}{R1*R2}*C1*C2*t^2$

(25) then:

(26) $t=\sqrt{\frac{\mathrm{VIN}}{\left(\mathrm{Vref}-\mathrm{VCM}\right)*C1*C2/\left(R1*R2\right)}}$

(27) According to the working principle of the ADC, the value counted by the counter in the t time is the digital code DN, which is converted by the ADC finally when the VIN is inputted:
DN=t*CLK

(28) Therefore, the expression for the digital code DN as following when the input of the ADC is VIN and using the VRAMP shown in the formula {circle around (8)} as a reference voltage:

(29) $\begin{array}{cc}\mathrm{DN}=\sqrt{\frac{\mathrm{VIN}}{\left(\mathrm{Vref}-\mathrm{VCM}\right)*C1*C2/\left(R1*R2\right)}}*\mathrm{CLK}& \end{array}$

(30) Wherein, the CLK is the clock frequency of the counter in the ADC; and now, the transfer characteristic of the ADC can be expressed as the following formula:
VIN=k*DN.sup.210

(31) Wherein, the k is a coefficient, which is related to a parameter selection of the integrator and the counter clock CLK of the ADC, that is:

(32) $k=\frac{\left(\mathrm{Vref}-\mathrm{VCM}\right)*C1*C2/\left(R1*R2\right)}{{\mathrm{CLK}}^2}$

(33) Refer to FIG. 8 and FIG. 9, FIG. 8 is a schematic diagram of a reference voltage VRAMP generated by three-time extended iterative according to an embodiment of the present disclosure, FIG. 9 is a specific circuit structure diagram of a reference voltage VRAMP generated by three-time extended iterative according to an embodiment of the present disclosure. According to the cascaded three-stage integrator in FIG. 8, the voltage change outputted by the output node VRAMP in the integration period is in direct proportion relation with the time to the power of 3, so that the input signal in the transfer characteristic of the ADC is in direct proportion relation with the output digital code to the power of 3.

(34) Referring to FIG. 10, FIG. 10 is a schematic diagram of a reference voltage VRAMP generated by N-time extended iterative according to an embodiment of the present disclosure. The voltage change outputted by the output node VRAMP through the cascade N-stage integrator in the integration period is in direct proportion with time to the power of N, so that the input signal in the transfer characteristic of the ADC is in direct proportion with the output digital code to the power of N.

(35) Moreover, in the embodiment, the invention further provides a method adopting the system for regulating transfer characteristics of an integral analog-to-digital converter, the method for regulating transfer characteristics of an integral analog-to-digital converter comprises the following steps: forming the cascade N-stage integrator structure using N integrators; connecting the input end of the first integrator with a reference voltage; connecting the output end of the Nth integrator to an output node (VRAMP), connecting the output end of each integrator with the input end of the adjacent integrator, so that the voltage change of the output of the Nth integrator to the output node (VRAMP) is in direct proportion with time to the power of N.

(36) Specifically, each integrator in the embodiment comprises a resistor, a capacitor, an operational transconductance amplifier and a switch. For each integrator, the positive input end of the operational transconductance amplifier is connected to a voltage source (VCM), and one end of the resistor is connected to the reverse input end of the operational transconductance amplifier at a node, the two ends of the capacitor are connected to the node and the output end of the operational transconductance amplifier respectively; the switch is connected to the two ends of the capacitor in parallel, and the other end of the resistor is connected to the input end of the integrator; the output end of the operational transconductance amplifier is connected to the input end of the other integrator which is adjacent to the operational transconductance amplifier.

(37) While this invention has been particularly shown and described with references to preferred embodiments thereof, if will be understood by those skilled in the art that various changes in form and details may be made herein without departing from the spirit and scope of the invention as defined by the appended claims.