Operational amplifier

Abstract

An operational amplifier includes an output node; an output stage, comprising a plurality of output current paths and a plurality of control nodes, wherein the plurality of control nodes are respectively coupled to the plurality of output current paths, and the plurality of output current paths are coupled to the output node and respectively coupled to a plurality of power supply sources providing different voltages; and a selecting unit, configured to couple an internal output node of the operational amplifier to one of the plurality of control nodes of the output stage.

Claims

1. An operational amplifier, comprising: an output node; an output stage, comprising a plurality of output current paths and a plurality of control nodes, wherein the plurality of control nodes are respectively coupled to the plurality of output current paths, and the plurality of output current paths are coupled to the output node and respectively coupled to a plurality of power supply sources providing different voltages; and a selecting unit, configured to selectively couple an internal output node of the operational amplifier to one of the plurality of control nodes of the output stage; wherein the operational amplifier is an output buffer of a display driving circuit.

2. The operational amplifier of claim 1, wherein one of the plurality of output current paths is selected to provide a supply current to a load.

3. The operational amplifier of claim 1, wherein one of the plurality of output current paths is selected to provide a sink current drained from a load.

4. The operational amplifier of claim 1, wherein when one of the plurality of output current paths is selected to provide an output current, other output current paths not selected are configured to not conducted.

5. The operational amplifier of claim 1, wherein at least one of the plurality of power supply source provides a voltage determined according to a plurality of digital display data.

6. The operational amplifier of claim 1, wherein the selecting unit is controlled by a selecting signal generated according to a digital display data which is converted into an input voltage to be outputted to the operational amplifier.

7. The operational amplifier of claim 6, wherein the selecting signal is generated according to the most significant bit of the digital display data.

8. The operational amplifier of claim 6, wherein the selecting signal is generated according to a determination result that is generated by determining a voltage range where the input voltage is.

9. The operational amplifier of claim 1, wherein the plurality of output current paths respectively comprise transistors of the same channel type, and each of the plurality of control nodes is coupled to a gate of a transistor in each output current path.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a schematic diagram of an operational amplifier according to an embodiment of the present invention.

(2) FIG. 2 is a schematic diagram of an operational amplifier according to an embodiment of the present invention.

(3) FIG. 3 is a schematic diagram of an operational amplifier according to an embodiment of the present invention.

(4) FIG. 4 is a table illustrating the input voltage, the composition of the output stage and corresponding bias of the output stage of the operational amplifier of FIG. 3.

(5) FIG. 5 is a timing diagram of an output voltage of an operational amplifier according an embodiment of the present invention.

(6) FIG. 6 is a schematic diagram of an output buffer pair according to an embodiment of the present invention.

(7) FIG. 7 is a schematic diagram of an output buffer pair according to an embodiment of the present invention.

DETAILED DESCRIPTION

(8) Please refer to FIG. 1, which is a schematic diagram of an operational amplifier 10 according to an embodiment of the present invention. The operational amplifier 10 is a voltage follower and may be utilized as an output buffer in a display driving circuit of a display panel. The operational amplifier 10 may generate an output current I.sub.OUT outputted through an output node N.sub.OUT, wherein the output current I.sub.OUT is generated according to a differential input voltage that is the difference between an input voltage V.sub.IN inputted to the operational amplifier 10 from a digital-to-analog converter (DAC) in the display driving circuit and the voltage level at the output node N.sub.OUT, called the output voltage V.sub.OUT hereinafter. The output current I.sub.OUT is a supply current (or called charging current) or a sink current (or called discharging current) with respect to a load (e.g., a pixel unit in a display panel, not shown in FIG. 1) coupled to the output node N.sub.OUT, such that the output voltage V.sub.OUT may follow the input voltage V.sub.IN. The input voltage V.sub.IN is corresponding to a gray level to be displayed in the pixel unit.

(9) The operational amplifier 10 includes an input stage 100, a gain stage 102, a selecting unit 104, and an output stage 106. The input stage 100 receives the input voltage V.sub.IN and a feedback voltage which is the output voltage V.sub.OUT. The input stage 100 may generate differential output signals according to the differential input voltage (V.sub.INV.sub.OUT).

(10) The gain stage 102 is coupled to the input stage 100 and internal output nodes N.sub.T1 and N.sub.T2 of the operational amplifier 10. The gain stage 102 is utilized for generating a first control voltage V.sub.T1 and a second control voltage V.sub.T2 according to the differential output signals generated by the input stage 100. The first control voltage V.sub.T1 and the second control voltage V.sub.T2 are respectively outputted through the internal output nodes N.sub.T1 and N.sub.T2.

(11) The selecting unit 104 is coupled to the internal output node N.sub.T1 and is utilized for selectively coupling the internal output node N.sub.T1 to one of two first control nodes N.sub.1A and N.sub.1B of the output stage 106 according to a selecting signal SEL. By using the selecting unit 104, the first control voltage V.sub.T1 may be transmitted to the output stage 106. The first control voltage V.sub.T1 and the second control voltage V.sub.T2 control the output stage 106 to output the output current I.sub.OUT.

(12) The selecting signal SEL may be generated according to a digital display data converted into the input voltage V.sub.IN to be outputted to the operational amplifier 10. In an example, the selecting signal SEL may be generated according to the most significant bit of the digital display data. In this example, the first control voltage V.sub.T1 is transmitted via the selecting unit 104 to the first control node N.sub.1A if the selecting signal SEL indicates the most significant bit of the digital display data is 1; otherwise, the first control voltage V.sub.T1 is transmitted via the selecting unit 104 to the first control node N.sub.1B if the selecting signal SEL indicates the most significant bit of the digital display data is 0. Based on the example using the most significant bit of the digital display data to generate the selecting signal SEL, an exemplary circuit for generating the selecting signal SEL may include a level shifter to convert the most significant bit of the digital display data to a higher voltage level proper to be applied in the operational amplifier 10. Another example of generating the selecting signal SEL may be given in the later description.

(13) The output stage 106 may be a class AB output stage. The output stage 106 includes the first control nodes N.sub.1A and N.sub.1B coupled to the selecting unit 104, and includes a second control node N.sub.2 coupled to the internal output node N.sub.T2. The output stage 106 includes two output current paths, denoted as path (1) and path (2) in FIG. 1. The output current path (1) is coupled between a power supply source supplying a voltage VDD and the output node N.sub.OUT and coupled to the first control node N.sub.1A. The output current path (2) is coupled between a power supply source supplying a voltage VSP1 and the output node N.sub.OUT and coupled to the first control node N.sub.1B. The output stage 106 also includes a current path (3) coupled between the output node N.sub.OUT and a power supply source supplying a voltage VEE and coupled to the second control node N.sub.2. The voltage VSP1 is lower than the voltage VDD, and the voltage VSP1 may be a constant voltage such as ()*VDD or ()*VDD, or a variable voltage. The voltage VEE may be lower than the voltages VDD and VSP1.

(14) One of the first control nodes N.sub.1A and N.sub.1B which is selected according to the selecting signal SEL receives the first control voltage V.sub.T1, and the first control voltage V.sub.T1 controls the selected one of the output current paths (1) and (2). The second control node N.sub.2 receives the second control voltage V.sub.T2 from the gain stage 102 to control the current path (3).

(15) One of the output current paths (1) and (2) may be selected according to the selecting signal SEL to provide the output current I.sub.OUT to the load, in a condition that a current input voltage V.sub.IN,t corresponding to a current digital display data D[t] is higher than the output voltage V.sub.OUT which follows an input voltage V.sub.IN,t1 corresponding to a previous digital display data D[t1], wherein t indicates a timing order. In this condition (V.sub.IN,t>V.sub.IN,t1), the voltage level at the output node N.sub.OUT may be increased to reach the current input voltage V.sub.IN,t. There is still a current flowing though the current path (3) to the power supply source supplying VEE when the output current path (1) or (2) outputs the supply current.

(16) Therefore, the operational amplifier 10 has a selected output current path, selected from multiple output current paths each capable of providing a supply current. It is noted that the output current path(s) not selected is configured to not conducted, i.e., not to provide a supply current, when the selected output current path provides the supply current.

(17) The current path (3) may provide the output current I.sub.OUT drained from the load, in a condition that the current input voltage V.sub.IN,t corresponding to the current digital display data D [t] is lower than the output voltage V.sub.OUT which follows the input voltage V.sub.IN,t1 corresponding to the previous digital display data D[t1]. In this condition (V.sub.IN,t<V.sub.IN,t1), the voltage level at the output node N.sub.OUT may be decreased to reach the current input voltage V.sub.IN,t.

(18) Each of the output current paths (1) and (2) may include one or more transistors. In the output stage 106 shown in FIG. 1, the output current paths (1) and (2) respectively include PMOS transistors M1A and M1B. The first control node N.sub.1A is coupled to the gate of the PMOS transistor M1A and the first control node N.sub.1B is coupled to the gate of the PMOS transistor M1B. The current path (3) includes a NMOS transistor M2, and the second control node N.sub.2 is coupled to the gate of the NMOS transistor M2.

(19) In another example, the selecting signal SEL may be generated according to a determination result that is generated by determining a voltage range where the current input voltage V.sub.IN,t corresponding to the current digital display data D [t] is. For example, the current input voltage V.sub.IN,t is compared with the voltage VSP1. It is noted that the determination result indicating V.sub.IN,tVSP1 or V.sub.IN,t<VSP1 may be generated by comparing analog voltages, i.e., comparing the current input voltage V.sub.IN,t and the voltage VSP1, or, may be generated by comparing the current digital display data corresponding to the current input voltage V.sub.IN,t and a digital value corresponding to the voltage VSP1.

(20) When V.sub.IN,tVSP1, the selecting unit 104 selectively couples the internal output node N.sub.T1 to the first control node N.sub.1A (e.g., the gate of the PMOS transistor M1A) according to the selecting signal SEL which indicates V.sub.IN,tVSP1. The first control voltage V.sub.T1 and the second control voltage V.sub.T2 respectively control the PMOS transistor M1A and the NMOS transistor M2 to be in the active state (and whatever M1A and M2 is in triode region or saturation region is not limited), so that a current output current I.sub.OUT,t is generated. Whether the current output current I.sub.OUT,t is a supply current or a sink current is determined according to the voltage difference between the current input voltage V.sub.IN,t and the previous input voltage V.sub.IN,t1. When the PMOS transistor M1A is in the active state, the selecting unit 104 or other circuit may control the first control node N.sub.1B to be pulled high to make the PMOS transistor M1B be in the cutoff state.

(21) When V.sub.IN,t<VSP1, the selecting unit 104 selectively couples the internal output node N.sub.T1 to the first control node N.sub.1B (e.g., the gate of the PMOS transistor M1B) according to the selecting signal SEL which indicates V.sub.IN,t<VSP1. The first control voltage V.sub.T1 and the second control voltage V.sub.T2 respectively control the PMOS transistor M1B and the NMOS transistor M2 to be in the active state, so that the current output current I.sub.OUT,t is generated. When the PMOS transistor M1B is in the active state, the selecting unit 104 or other circuit may control the first control node N.sub.1A to be pulled high to make the PMOS transistor M1A be in the cutoff state.

(22) When V.sub.IN,tVSP1 and the current output current I.sub.OUT,t is a supply current to the load by the output current path (1), the power consumption of charging to the load, denoted as P1, is expressed by the following equation:
P1=C.sub.LV.sub.D1V.sub.DIFF(E1)
wherein V.sub.D1 is the voltage VDD, C.sub.L is the equivalent capacitance of the load (i.e., pixel unit), and V.sub.DIFF is the voltage difference between the current input voltage V.sub.IN,t and the previous input voltage V.sub.IN,t1.

(23) When V.sub.IN,t<VSP1 and the output current is a supply current to the load by the output current path (2), the power consumption of charging to the load, denoted as P2, is expressed by the following equation:
P2=C.sub.LV.sub.D2V.sub.DIFF(E2)

(24) wherein V.sub.D2 is the voltage VSP1, which is lower than the voltage VDD. From the above, the power consumption P2 may be less than the power consumption P1 in a condition that the voltage difference V.sub.DIFF in the equation E1 equals that in the equation E2.

(25) Therefore, by using the operational amplifier 10, the power consumption of charging to the load may be reduced adaptively according to the input voltage of the operational amplifier 10. In other words, the power consumption of charging to the load may be reduced adaptively according to the digital display data. The conventional pre-charge techniques may be not suitable for a display panel of higher resolution and short charging period. By using the operational amplifier 10 in the display driving circuit, a charging period does not need to be divided into two sub-periods (i.e., a pre-charge period and a regular charging period) so the conventional pre-charge circuit may be not necessary.

(26) Please refer to FIG. 2, which is an operational amplifier 20 according to an embodiment of the present invention. The operational amplifier 20 includes an input stage 200, a gain stage 202, a selecting unit 204, and an output stage 206. The operational amplifier 20 further includes internal output nodes N.sub.T1 and N.sub.T2. The input stage 200 and the gain stage 202 may be similar to the input stage 100 and the gain stage 102 of FIG. 1, and related description is not repeated herein.

(27) The selecting unit 204 is coupled to the internal output node N.sub.T2 and is utilized for selectively coupling the internal output node N.sub.T2 to one of two second control nodes N.sub.2A and N.sub.2B of the output stage 206 according to a selecting signal SEL2. By using the selecting unit 204, the second control voltage V.sub.T2 may be transmitted to the output stage 206. The first control voltage V.sub.T1 and the second control voltage V.sub.T2 control the output stage 206 to output the output current I.sub.OUT.

(28) The selecting signal SEL2 may be generated according to a digital display data converted into the input voltage V.sub.IN to be outputted to the operational amplifier 20. In an example, the selecting signal SEL2 may be generated according to the most significant bit of the digital display data. In this example, the second control voltage V.sub.T2 is transmitted via the selecting unit 204 to the second control node N.sub.2A when the selecting signal SEL2 indicates the most significant bit of the digital display data is 1; otherwise, the second control voltage V.sub.T2 is transmitted via the selecting unit 204 to the second control node N.sub.2B when the selecting signal SEL2 indicates the most significant bit of the digital display data is 0. Another example of generating the selecting signal SEL2 may be given in the later description.

(29) The output stage 206 may be a class AB output stage. The output stage 206 includes the second control nodes N.sub.2A and N.sub.2B coupled to the selecting unit 204, and includes a first control node N.sub.1 coupled to the internal output node N.sub.T1. The output stage 206 includes two output current paths, denoted as path (4) and path (5) in FIG. 2. The output current path (4) is coupled between the output node N.sub.OUT and a power supply source supplying a voltage VEE and coupled to the second control node N.sub.2A. The output current path (5) is coupled between the output node N.sub.OUT and a power supply source supplying a voltage VSN1 and coupled to the second control node N.sub.2B. The output stage 206 also includes a current path (6) coupled between a power supply source supplying a voltage VDD and the output node N.sub.OUT and coupled to the first control node N.sub.1. The voltage VEE may be lower than the voltage VDD. The voltage VSN1 is higher than the voltage VEE and is lower than the voltage VDD, and the voltage VSN1 may be a constant voltage or a variable voltage.

(30) One of the second control nodes N.sub.2A and N.sub.2B which is selected according to the selecting signal SEL2 receives the second control voltage V.sub.T2, and the second control voltage V.sub.T2 controls the selected one of the output current paths (4) and (5). The first control node N.sub.1 receives the first control voltage V.sub.T1 from the gain stage 202 to control the current path (6).

(31) One of the output current paths (4) and (5) may be selected according to the selecting signal SEL2 to provide the output current LOUT which is drained from the load, in a condition that a current input voltage V.sub.IN,t corresponding to a current digital display data D [t] is lower than the output voltage V.sub.OUT which follows an input voltage V.sub.IN,t1 corresponding to a previous digital display data D[t1]. In this condition (V.sub.IN,t<V.sub.IN,t1), the voltage level at the output node N.sub.OUT may be decreased to reach the current input voltage V.sub.IN,t. There is still a current flowing though the current path (6) from the power supply source supplying VDD when the output current path (4) or (5) outputs the sink current.

(32) Therefore, the operational amplifier 20 has a selected output current path, selected from multiple output current paths each capable of providing a sink current. It is noted that the output current path (s) not selected is configured to not conducted, i.e., not to provide a sink current, when the selected output current path provides the sink current.

(33) The current path (6) may provide the output current I.sub.OUT supplied to the load, in a condition that a current input voltage V.sub.IN,t corresponding to a current digital display data D[t] is higher than the output voltage V.sub.OUT which follows the input voltage V.sub.IN,t1 corresponding to a previous digital display data D[t1]. In this condition (V.sub.IN,t>V.sub.IN,t1), the voltage level at the output node N.sub.OUT may be increased to reach the current input voltage V.sub.IN,t.

(34) Each of the output current paths (4) and (5) may include one or more transistors. In the output stage 206, the output current paths (4) and (5) respectively include NMOS transistors M2A and M2B. The second control node N.sub.2A is coupled to the gate of the NMOS transistor M2A and the second control node N.sub.2B is coupled to the gate of the NMOS transistor M2B. The current path (6) includes a PMOS transistor M1, and the first control node N.sub.1 is coupled to the gate of the PMOS transistor M1.

(35) In another example, the selecting signal SEL2 may be generated according to a determination result that is generated by determining a voltage range where the current input voltage V.sub.IN,t corresponding to the current digital display data D [t] is. For example, the current input voltage V.sub.IN,t is compared with the voltage VSN1. It is noted that the determination result indicating V.sub.IN,t>VSN1 or V.sub.IN,tVSN1 may be generated by comparing analog voltages or comparing digital values.

(36) When V.sub.IN,t>VSN1, the selecting unit 204 selectively couples the internal output node N.sub.T2 to the second control node N.sub.2B (e.g., the gate of the NMOS transistor M2B) according to the selecting signal SEL2 which indicates V.sub.IN,t>VSN1. The first control voltage V.sub.T1 and the second control voltage V.sub.T2 respectively control the PMOS transistor M1 and the NMOS transistor M2B to be in the active state (and whatever M1 and M2B is in triode region or saturation region is not limited), so that a current output current I.sub.OUT,t is generated. Whether the current output current I.sub.OUT,t is a supply current or a sink current is determined according to the voltage difference between the current input voltage V.sub.IN,t and the previous input voltage V.sub.IN,t1 When the NMOS transistor M2B is in the active state, the selecting unit 204 or other circuit may control the second control node N.sub.2A to be pulled low to make the NMOS transistor M2A be in the cutoff state.

(37) When V.sub.IN,tVSN1, the selecting unit 204 selectively couples the internal output node N.sub.T2 to the second control node N.sub.2A (e.g., the gate of the NMOS transistor M2A) according to the selecting signal SEL2 which indicates V.sub.IN,tVSN1. The first control voltage V.sub.T1 and the second control voltage V.sub.T2 respectively control the PMOS transistor M1 and the NMOS transistor M2A to be in the active state, so that a current output current I.sub.OUT,t is generated. When the NMOS transistor M2A is in the active state, the selecting unit 204 or other circuit may control the second control node N.sub.2B to be pulled low to make the NMOS transistor M2B be in the cutoff state.

(38) To compare the power consumption of discharging from the load to the power supply source supplying the voltage VEE and the power consumption of discharging from the load to the power supply source supplying the voltage VSN1, equations may be derived in a similar way as the equations E1 and E2. By using the operational amplifier 20, the power consumption of discharging from the load may be reduced adaptively according to the input voltage the operational amplifier 20. In other words, the power consumption of discharging from the load may be reduced adaptively according to the display data.

(39) Please refer to FIG. 3, which is an operational amplifier 30 according to an embodiment of the present invention. The operational amplifier 30 includes an input stage 300, a gain stage 302, a selecting unit 304, and an output stage 306. The operational amplifier 30 further includes internal output nodes N.sub.T1 and N.sub.T2. The input stage 300 and the gain stage 302 may be similar to the input stage 100 and the gain stage 102 of FIG. 1.

(40) The output stage 306 includes four output current paths which are similar to the output current paths (1) and (2) (for supply current) in FIG. 1 and the output current paths (4) and (5) (for sink current) in FIG. 2. The power supply sources respectively coupled to the four output current paths are also similar to the illustrated in FIG. 1 and FIG. 2 and related description is not repeated herein. The output current paths for outputting a supply current respectively include PMOS transistors M1A and M1B, and the output current paths for outputting a sink current respectively include NMOS transistors M2A and M2B. The output stage 306 includes two first control nodes N.sub.1A and N.sub.1B and two second control nodes N.sub.2A and N.sub.2B.

(41) The selecting unit 304 is coupled to the internal output nodes N.sub.T1 and N.sub.T2 and is utilized for selectively coupling the internal output node N.sub.T1 to one of the first control nodes N.sub.1A and N.sub.1B according to a selecting signal SEL. The first control voltage V.sub.T1 outputted from the gain stage 302 is used as the gate bias of the PMOS transistor M1A or M1B. The selecting unit 304 is also utilized for selectively coupling the internal output node N.sub.T2 to one of the second control nodes N.sub.2A and N.sub.2B according to a selecting signal SEL2. The second control voltage V.sub.T2 outputted from the gain stage 302 is used as the gate bias of the NMOS transistor M2A or M2B.

(42) Please refer to FIG. 4, which is a table of the voltage range that the input voltage V.sub.IN of the operational amplifier 30 falls in, the composition of the output stage 306, and corresponding gate bias of the transistors M1A, M1B, M2A and M2B. The selecting signals SEL and SEL2 may be generated according to a determination result that is generated by determining a voltage range where the current input voltage V.sub.IN,t is. The current input voltage V.sub.IN,t is remarked as V.sub.IN in the table.

(43) When VDD>V.sub.INVSP1, the selecting unit 304 couples the internal output node N.sub.T1 to the first control node N.sub.1A and the first control voltage V.sub.T1 controls the PMOS transistor M1A (coupled to VDD) to be in the active state; and in this condition, it is workable whatever the selecting unit 304 couples the internal output node N.sub.T2 to the second control node N.sub.2A or the second control node N.sub.2B, which means either the NMOS transistor M2A or the NMOS transistor M2B is in the active state. The PMOS transistor and the NMOS transistor those are in the unselected paths are in the cutoff state.

(44) When VSP1>V.sub.IN>VSN1, it is workable whatever the selecting unit 304 couples the internal output node N.sub.T1 to the first control node N.sub.1A or the first control node N.sub.1B, which means either the PMOS transistor M1A (coupled to VDD) or the PMOS transistor M1B (coupled to VSP1) is in the active state; and it is workable whatever the selecting unit 304 couples the internal output node N.sub.T2 to the second control node N.sub.2A or the second control node N.sub.2B, which means either the NMOS transistor M2A (coupled to VEE) or the NMOS transistor M2B (coupled to VSN1) is in the active state.

(45) When VSN1V.sub.IN>VEE, the selecting unit 304 couples the internal output node N.sub.T2 to the second control node N.sub.2A and the second control voltage V.sub.T2 controls the NMOS transistor M2A (coupled to VEE) to be in the active state; and in this condition, it is workable whatever the selecting unit 304 couples the internal output node N.sub.T1 to the first control node N.sub.1A or the first control node N.sub.1B, which means either the PMOS transistor M1A or the PMOS transistor M1B is in the active state. The PMOS transistor and the NMOS transistor those are in the unselected paths are in the cutoff state.

(46) By using the operational amplifier 30, the power consumption of charging to the load and the power consumption of discharging from the load may be reduced adaptively according to the digital display data which are converted to the input voltage to the operational amplifier 30. Similar to the operational amplifier 10, the operational amplifier 20 and the operational amplifier 30 also have the benefit of being suitable for the display panel of higher resolution and short charging period.

(47) Please refer to FIG. 5, which is an exemplary timing diagram of the output voltage V.sub.OUT of the operational amplifier 10 of FIG. 1. The input voltage V.sub.IN may have a similar timing diagram since the output voltage V.sub.OUT follows the input voltage V.sub.IN. FIG. 5 illustrates that the operational amplifier 10 is configured to output only positive output voltages in a frame, which may be one of exemplary application scenarios of the operational amplifier 10. A frame period includes a plurality of charging periods, and for each current charging period (i.e., the period of updating a horizontal display line) the output voltage V.sub.OUT may vary or maintain at the same level as in a previous charging period. Take a frame including 1080 horizontal display lines as an example, 1080 digital display data are converted into 1080 input voltages to the operational amplifier 10, and 1080 output voltages are sequentially outputted to the display panel in a frame period. For a frame N, the voltage VSP1 may be determined according to the 1080 digital display data converted into the input voltages to the operational amplifier 10. More specifically, the voltage VSP1 may be determined according to an average of these 1080 digital display data (gray level values) or an average of 1080 luminance values corresponding to these 1080 digital display data. The voltage VSP1 may be a variable voltage and configured frame by frame, as shown in FIG. 5, since the digital display data is variable.

(48) The above method to determine the voltage VSP1 is one of various examples. In another example, the number of digital display data for determining the voltage DSP1 may be all or a part of digital display data for a frame. The voltage VSN1 in the operational amplifier 20 of FIG. 2 may be determined in a similar way.

(49) It is noted that FIG. 1 to FIG. 3 illustrate individual blocks of the input stage, the gain stage, the output stage and the selecting unit for an illustrative purpose only. An operational amplifier according to one of embodiments of the present invention may be illustrated as a two-stages structure including an input stage and an output stage, wherein the output stage or the output stage may provide a current gain. Hence, a selecting unit may be in combination with the output stage, and internal output nodes N.sub.T1 and N.sub.T2 may be in the output stage. According to the embodiments of the present invention, the internal output nodes N.sub.T1 and N.sub.T2 may be at any proper positions in the operational amplifier as long as voltage signals (or current signals) on those positions are capable of directly or indirectly controlling the gate bias of the PMOS transistor which provides the supply current and the gate bias of the NMOS transistor which provides the sink current.

(50) Please refer to FIG. 6, which is a schematic diagram of an output buffer pair 60 according to an embodiment of the present invention. The output buffer pair 60 may be used in a display driving circuit. The output buffer pair 60 includes operational amplifiers 600 and 602. The operational amplifier 600 has a structure similar to the operational amplifier 10 of FIG. 1 and includes two output current paths among which a supply current path is selected; and the operational amplifier 602 has a structure similar to the operational amplifier 20 and includes two output current paths among which a sink current path is selected. The operational amplifier 600 may receive an input voltage V.sub.IN,n and output an output voltage V.sub.OUT,n via an output node N.sub.OUT,n, wherein n denotes an even number or an odd number and the output node N.sub.OUT,n may be coupled to an even-numbered output pad or an odd-numbered output pad of the display driving circuit (not shown in FIG. 6). The operational amplifier 602 may receive an input voltage V.sub.IN,n+1 and output an output voltage V.sub.OUT,n+1 via an output node N.sub.OUT,n+1, wherein the output node N.sub.OUT,n+1 may be coupled to an output pad adjacent to the output pad corresponding to the output node N.sub.OUT,n. The output voltages V.sub.OUT,n and V.sub.OUT,n+1 are outputted to drive two adjacent pixel units (i.e., subpixels) of a display panel.

(51) In the output buffer pair 60, the voltages VDD and VSP.sub.n are positive voltages and the voltages VEE and VSN.sub.n+1 are negative voltages. The voltage VCOM may be set to a middle voltage between VDD and VEE. The voltage VSP.sub.n is lower than the voltage VDD and is higher than the voltage VCOM. The voltage VSN.sub.n+1 is lower than the voltage VCOM and is higher than the voltage VEE. For example, VDD may be +9V, VEE may be 9V, VCOM may be 0V, VSP.sub.n and VSN.sub.n+1 may be constant voltages, or variable voltages determined based on digital display data.

(52) The selecting unit of the operational amplifier 600 and the selecting unit of the operational amplifier 602 are controlled by respective selecting signals SEL.sub.n and SEL.sub.n+1. According to the selecting signal SEL.sub.n which is determined based on the input voltage V.sub.IN,n (or corresponding digital display data), the operational amplifier 600 may be capable of selectively providing a supply current from the power supply source supplying VDD or from the power supply source supplying VSP.sub.n, to a load coupled to the output node N.sub.OUT,n. According to the selecting signal SEL.sub.n+1 determined based on the input voltage V.sub.IN,n+1 (or corresponding digital display data), the operational amplifier 602 may be capable of selectively providing a sink current, from a load coupled to the output node N.sub.OUT,n+1 to the power supply source supplying VEE or to the power supply source supplying VSN.sub.n+1. By using the output buffer pair 60 in the display driving circuit, power consumption of charging to the load coupled to the output node N.sub.OUT,n and power consumption of discharging from the load coupled to the output node N.sub.OUT,n+1 may be reduced.

(53) Please refer to FIG. 7, which is a schematic diagram of an output buffer pair 70 according to an embodiment of the present invention. The output buffer pair 70 may be used in a display driving circuit. The output buffer pair 70 includes operational amplifiers 700 and 702. The operational amplifiers 700 and 702 have a structure similar to the operational amplifier 10 of FIG. 1, and respectively include two output current paths among which a supply current path is selected. The operational amplifier 700 may receive an input voltage V.sub.IN,n and output an output voltage V.sub.OUT,n via an output node N.sub.OUT,n. The operational amplifier 702 may receive an input voltage V.sub.IN,n+1 and output an output voltage V.sub.OUT,n+1 via an output node N.sub.OUT,n+1.

(54) In the output buffer pair 70, the voltages VDD, VSP.sub.n, VCOM and VSP.sub.n+1 are positive voltages. The voltages GND is a ground voltage. The voltage VCOM may be set to a middle voltage between VDD and GND. The voltage VSP.sub.n is lower than the voltage VDD and is higher than the voltage VCOM. The voltage VSP.sub.n+1 is lower than the voltage VCOM and is higher than the voltage GND. For example, VDD may be +18V, GND may be 0V, VCOM may be +9V, and VSP.sub.n and VSN.sub.n+1 may be constant voltages, or variable voltages determined based on digital display data.

(55) According to the selecting signals SEL.sub.n determined based on the input voltage V.sub.IN,n (or corresponding digital display data), the operational amplifier 700 may be capable of selectively providing a supply current from the power supply source supplying VDD or from the power supply source supplying VSP.sub.n, to a load coupled to the output node N.sub.OUT,n. According to the selecting signals SEL.sub.n+1 determined based on the input voltage V.sub.IN,n+1 (or corresponding digital display data), the operational amplifier 702 may be capable of selectively providing a supply current from the power supply source supplying VCOM or from the power supply source supplying VSP.sub.n+1, to a load coupled to the output node N.sub.OUT,n+1. By using the output buffer pair 70 in the display driving circuit, power consumption of charging to the load coupled the output node N.sub.OUT,n and power consumption of charging to the load coupled the output node N.sub.OUT,n+1 may be reduced.

(56) It is noted that FIG. 1 to FIG. 3 which illustrate the operational amplifier having two output current paths for supply current and/or two output current paths for sink current are some of embodiments. Based on the use of selective multiple output current paths, the number of output current paths is not limited to two paths, and may be three or more paths if required. The selecting signal may have multiple values (e.g., 2-bits value) capable of indicating more than two output current paths respectively coupled to power supply source supplying different voltages, and the value of the selecting signal may be determined according to the voltage range which the input voltage is in.

(57) By using the operational amplifier according to the embodiments of the present invention, the power consumption of charging to the load and/or the power consumption of discharging from the load may be reduced adaptively according to the digital display data. In addition, by using the operational amplifier according to the embodiments of the present invention in the display driving circuit, the charging period does not need to be divided into two sub-periods and the pre-charge circuit may be not necessary in the display driving circuit.

(58) Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.