Device and method for analog-to-digital conversion with charge redistribution, converter and associated image acquisition chain

Abstract

An N-bit type charge redistribution analog-to-digital conversion device includes an input terminal configured to receive an input signal and coupled via a line to an output terminal. The output terminal is configured to be coupled to a comparator. The device further includes three reference potential sources of different values and a network of capacitors, where a first terminal of each capacitor is coupled to the line, and where a second terminal of each capacitor is coupled to switching circuit configured for coupling the second terminal of each capacitor to one of the reference potentials.

Claims

1. An N-bit type charge redistribution analog-to-digital conversion device, comprising: an input terminal configured to receive an input signal; an output terminal coupled to the input terminal via a line, wherein the output terminal is configured to be coupled to a comparator; a plurality of reference potential terminals configured to be respectively coupled to a plurality of reference potential sources of different values; a plurality of switching circuits; and a network of capacitors comprising a plurality of capacitors, wherein a first terminal of each capacitor of the network of capacitors is coupled to the line, wherein a second terminal of a respective capacitor of the network of capacitors is coupled to a respective switching circuit of the plurality of switching circuits, the respective switching circuit is configured to couple the second terminal of the respective capacitor to one of the plurality of reference potential sources or to leave the second terminal of the respective capacitor floating, wherein the network of capacitors comprises a reference capacitor having a capacitance equal to a reference capacitance value and N groups of capacitors, wherein an overall capacitance n of each group of the N groups of capacitors follows a geometric progression series of ratio $\frac{2^N}{2^n},$ wherein N is a positive integer greater or equal to 1, and wherein n is a positive integer greater or equal to 1 and smaller or equal to N.

2. The device according to claim 1, wherein an initial value of the geometric progression series is equal to the reference capacitance value.

3. The device according to claim 1, wherein capacitors of each group of the N groups of capacitors have a capacitance being a multiple of the reference capacitance value, and wherein an overall capacitance of the network of capacitors is equal to 2N times the reference capacitance value.

4. The device according to claim 1, wherein N is equal to 4, wherein a first group of capacitors of the N groups of capacitors comprises four capacitors having a capacitance equal to twice the reference capacitance value, wherein a second group of capacitors of the N groups of capacitors comprises two capacitors having a capacitance equal to twice the reference capacitance value, wherein a third group of capacitors of the N groups of capacitors comprises one capacitor having a capacitance equal to twice the reference capacitance value, and wherein a fourth group of capacitors of the N groups of capacitors comprises one capacitor having a capacitance equal to the reference capacitance value.

5. The device according to claim 1, wherein the plurality of reference potential sources comprises a first reference potential source and a second reference potential source having a same magnitude and an opposite sign.

6. The device according to claim 5, wherein the plurality of reference potential sources further comprises a third reference potential source coupled to a ground potential.

7. An analog-to-digital converter, comprising: a conversion device, comprising: an input terminal configured to receive an input signal; an output terminal coupled to the input terminal via a line; a plurality of reference potential terminals configured to be respectively coupled to a plurality of reference potential sources of different values; a plurality of switching circuits; and a network of capacitors comprising a plurality of capacitors, wherein a first terminal of each capacitor of the network of capacitors is coupled to the line, wherein a second terminal of a respective capacitor of the network of capacitors is coupled to a respective switching circuit of the plurality of switching circuits, the respective switching circuit is configured to couple the second terminal of the respective capacitor to one of the plurality of reference potential sources or to couple the second terminal of the respective capacitor to a floating terminal; a comparator coupled to the output terminal of the conversion device; and a state machine configured to successively connect the second terminal of the plurality of capacitors to the floating terminal.

8. The analog-to-digital converter according to claim 7, wherein the output terminal of the conversion device is coupled to a non-inverting input of the comparator, and wherein an inverting input of the comparator is coupled to a variable potential different from the plurality of reference potential sources, and wherein an output of the comparator is coupled to an input of the state machine.

9. The analog-to-digital converter according to claim 7, wherein the state machine comprises a plurality of outputs for delivering a digital word, and wherein respective inputs of the plurality of switching circuits are coupled to respective outputs of the plurality of outputs of the state machine.

10. The analog-to-digital converter according to claim 7, wherein the output terminal is directly connected to the input terminal via the line.

11. The analog-to-digital converter according to claim 7, wherein the network of capacitors comprises a reference capacitor having a capacitance equal to a reference capacitance value and N groups of capacitors, wherein an overall capacitance n of each group of the N groups of capacitors follows a geometric progression series of ratio $\frac{2^N}{2^n},$ wherein N is a positive integer greater or equal to 1, and wherein n is a positive integer greater or equal to 1 and smaller or equal to N.

12. An image acquisition chain, comprising: a pixel; and a conversion device comprising an input terminal coupled to an output of the pixel, the conversion device comprising: an output terminal coupled to the input terminal via a line; a plurality of reference potential terminals configured to be respectively coupled to a plurality of reference potential sources of different values; a plurality of switching circuits; and a network of capacitors comprising a plurality of capacitors, wherein a first terminal of each capacitor of the network of capacitors is coupled to the line, wherein a second terminal of a respective capacitor of the network of capacitors is coupled to a respective switching circuit of the plurality of switching circuits, the respective switching circuit is configured to couple the second terminal of the respective capacitor to one of the plurality of reference potential sources or to couple the second terminal of the respective capacitor to a floating terminal, wherein the network of capacitors comprises a reference capacitor having a capacitance equal to a reference capacitance value and N groups of capacitors, wherein an overall capacitance n of each group of the N groups of capacitors follows a geometric progression series of ratio $\frac{2^N}{2^n},$ wherein N is a positive integer greater or equal to 1, and wherein n is a positive integer greater or equal to 1 and smaller or equal to N.

13. The image acquisition chain according to claim 12, wherein an initial value of the geometric progression series is equal to the reference capacitance value.

14. The image acquisition chain according to claim 12, wherein capacitors of each group of the N groups of capacitors have a capacitance being a multiple of the reference capacitance value, and wherein an overall capacitance of the network of capacitors is equal to 2N times the reference capacitance value.

15. The image acquisition chain according to claim 12, wherein N is equal to 4, wherein a first group of capacitors of the N groups of capacitors comprises four capacitors having a capacitance equal to twice the reference capacitance value, wherein a second group of capacitors of the N groups of capacitors comprises two capacitors having a capacitance equal to twice the reference capacitance value, wherein a third group of capacitors of the N groups of capacitors comprises one capacitor having a capacitance equal to twice the reference capacitance value, and wherein a fourth group of capacitors of the N groups of capacitors comprises one capacitor having a capacitance equal to the reference capacitance value.

16. An image acquisition chain, comprising: a pixel; and a conversion device comprising an input terminal coupled to an output of the pixel, the conversion device comprising: an output terminal coupled to the input terminal via a line; a plurality of reference potential terminals configured to be respectively coupled to a plurality of reference potential sources of different values; a plurality of switching circuits; a network of capacitors comprising a plurality of capacitors, wherein a first terminal of each capacitor of the network of capacitors is coupled to the line, wherein a second terminal of a respective capacitor of the network of capacitors is coupled to a respective switching circuit of the plurality of switching circuits, the respective switching circuit is configured to couple the second terminal of the respective capacitor to one of the plurality of reference potential sources or to couple the second terminal of the respective capacitor to a floating terminal; and a state machine configured to successively connect the second terminal of the plurality of capacitors to the floating terminal.

17. A method, comprising: receiving an input signal at an input terminal of an N-bit type charge redistribution analog-to-digital conversion device; asserting an output signal at an output terminal of the N-bit type charge redistribution analog-to-digital conversion device, wherein the output terminal is coupled to the input terminal via a line and to a comparator; providing a plurality of reference potentials of different values to a plurality of reference potential terminals of the N-bit type charge redistribution analog-to-digital conversion device; switching a network of capacitors, comprising a plurality of capacitors, using a plurality of switching circuits, wherein a first terminal of each capacitor of the network of capacitors is coupled to the line, wherein a second terminal of a respective capacitor of the network of capacitors is coupled to a same reference potential of the plurality of reference potentials, wherein switching the network of capacitors comprises: disconnecting the second terminal of the respective capacitor from a ground potential to leave the second terminal of the respective capacitor floating when the network of capacitors is charged by the input signal; and repeating disconnection of the second terminal of successive capacitors of the network of capacitors after a predetermined duration until the second terminal of each capacitor of the network of capacitors is floating.

18. The method according to claim 17, wherein the second terminal of each capacitor of the network of capacitors is disconnected from the ground potential after the predetermined duration so that an overall switched capacitance is constant.

19. The method according to claim 17, wherein the plurality of reference potentials comprises a first reference potential source and a second reference potential source having a same magnitude and an opposite sign.

20. The method according to claim 19, wherein the same reference potential of the plurality of reference potentials is coupled to the ground potential.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Other advantages and features of the invention will appear on examination of the detailed description of embodiments, in no way restrictive, and the appended drawings in which:

(2) FIGS. 1 to 4, previously described, illustrate an image acquisition chain including a charge redistribution analog-to-digital conversion device according to the prior art; and

(3) FIGS. 5 to 9 schematically illustrate embodiments and implementations of the invention.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

(4) Reference is made to FIG. 5 which represents an embodiment of an image acquisition chain CH1 of a pixel 99.

(5) The chain CH1 includes the pixel 99 and a four-bit type charge redistribution analog-to-digital converter 6.

(6) An output S100 of the pixel 99 is connected to an input E6 of the converter 6.

(7) The pixel 99 includes a photodiode and switching transistors and generates at its output S100 two successive signals, the difference of which is proportional to the captured light intensity.

(8) The two signals are successively converted by the device 6 into two distinct digital words.

(9) In what follows, only the processing of a first analog signal s6 emitted by the pixel 99 is described in detail. The processing of a second signal emitted by the pixel 99 by the device 6 is identical to the processing of the first signal.

(10) The analog signal s100 is converted by the device 6 into a digital word s6.

(11) Reference is made to FIG. 6 which represents an example of a charge redistribution analog-to-digital converter of the 4-bit type 6.

(12) The converter 6 includes the sampler 4, the clock CLK and the comparator COMP previously defined. It further includes a four-bit type charge redistribution analog-to-digital conversion device 7, and a state machine 8.

(13) The state machine 8 is, for example, implemented from logic gates, of a microprocessor or a microcontroller.

(14) The input E4 of the sampler 4 is connected to the input E6, the output S4 is connected to an input E7 of the device 7 and the control input Ec4 is connected to an output S8 of the state machine 8.

(15) The device 7 includes three connection terminals connected to three reference potential sources of different values Vref10, Vref20 and Vref30 connected to the connection terminals E7.sub.REF10, E7.sub.REF20 and E7.sub.REF30 respectively, and an output S7 connected to a non-inverting input E.sub.COMP1 of the comparator COMP.

(16) The potential Vref10 is less than the potential Vref20 and the potential Vref30 is connected to the earth.

(17) The value of the potentials Vref10, Vref20 is selected so that the amplitude of the signal s1 varying, for example, between 1 volts and +1 volts i.e. included in the interval [Vref10; Vref20].

(18) For example, a first reference potential source Vref10 is equal to 1 volts, a second reference potential source Vref20 of the same value as the first source Vref10 and of opposite sign i.e. +1 Volts and a third potential source Vref30 coupled to an earth.

(19) The device 7 further includes here nine control inputs E71, E72, E73, E74, E75, E76, E77, E78 and E79, connected to nine outputs S81, S82, S83, S84, S85, S86, S87, S88 and S89 respectively of the state machine 8.

(20) The inverting input E.sub.COMP2 connected to a potential source Vref4o and the output S is connected to an input E8 of the state machine 8.

(21) The potential Vref40 is connected here to the earth/ground potential.

(22) The state machine 8 includes an input E8.sub.CLK connected to the clock CLK and four outputs S8a, S8b, S8c and S8d connected to the output interface S6 which here includes four outputs a6, b6, c6 and d6 respectively.

(23) The state machine 8 further includes a programmable processing unit UT8 as represented here.

(24) The processing unit UT8 may also be located outside the state machine 8.

(25) Reference is now made to FIG. 7 which represents an embodiment of a four-bit type charge redistribution analog-to-digital conversion device 7.

(26) The converter 7 includes a line L7 connecting the input E7 to the output S7 and a network of capacitors R comprising five groups of capacitors 80, 40, 20, 10 and 100.

(27) The groups 80, 40, 20, 10 and 100 of capacitors include four capacitors C81, C82, C83 and C84, two capacitors C41 and C42, one capacitor C20, one capacitor C10 and one capacitor C100 respectively, whereof a first terminal B.sub.811, B.sub.821, B.sub.831, B.sub.841, B.sub.411, B.sub.421, B.sub.201, B.sub.101 and B.sub.1001 respectively is connected to the line L7 and a second terminal B.sub.812, B.sub.822, B.sub.832, B.sub.842, B.sub.412, B.sub.422, B.sub.202, B.sub.102 and B.sub.1002 respectively is connected to an output S.sub.M81, S.sub.M82, S.sub.M83, S.sub.M84, S.sub.M41, S.sub.M42, S.sub.M20, S.sub.M10, S.sub.M100 respectively of the switching circuit M81, M82, M83, M84, M41, M42, M20, M10 and M100 respectively.

(28) Each switching circuit M81, M82, M83, M84, M41, M42, M20, M10 and M100 includes a control input E.sub.c81, E.sub.c82, E.sub.c83, E.sub.c84, E.sub.c41, E.sub.c42, E.sub.c20, E.sub.c10 and E.sub.c100 respectively connected to the input E71, E72, E73, E74, E75, E76, E77, E78 and E79 respectively.

(29) Each switching circuit M81, M82, M83, M84, M41, M42, M20, M10 further includes a first input E.sub.M813, E.sub.M823, E.sub.M833, E.sub.M843, E.sub.M413, E.sub.M423, E.sub.M203, E.sub.M103 respectively connected to the input E7.sub.REF30, a second input E.sub.M812, E.sub.M822, E.sub.M832, E.sub.M842, E.sub.M412, E.sub.M422, E.sub.M202, E.sub.M102 respectively connected to the input E7.sub.REF20, a third input E.sub.M811, E.sub.M821, E.sub.M831, E.sub.M841, E.sub.M411, E.sub.M421, E.sub.M201, E.sub.M101 respectively connected to the input E7.sub.REF10.

(30) The switching circuit M100 further includes an input E.sub.M1003 connected to the input E7.sub.REF30.

(31) Each switching circuit M81, M82, M83, M84, M41, M42, M20, M10 and M100 also includes a floating terminal B.sub.M810, B.sub.M820, B.sub.M830, B.sub.M840, B.sub.M410, B.sub.M420, B.sub.M200, B.sub.M100, B.sub.M1000 respectively which is floating.

(32) Each switching circuit is configured for connecting its output to one of its first, second or third inputs or to its floating terminal according to the control signal received at its control input.

(33) Each floating terminal of a switching circuit is not connected to any physical element of the converter 6 so as to conserve the accumulated charge in the associated capacitor when the second terminal of the capacitor is coupled to the floating terminal.

(34) The network of capacitors R includes a reference capacitor which here is the capacitor C100 of capacitance CAP, e.g. 200 fF.

(35) The capacitance of the capacitor C10 is equal to CAP, the capacitance of the capacitors C20, C41, C42, C81, C82, C83 and C84 here is equal to twice the capacitance CAP.

(36) As the charge redistribution analog-to-digital conversion device 7 is of the four-bit type, the total capacitance of the network of capacitors R here is equal to 24 times CAP i.e. sixteen times CAP.

(37) In other words, the network R of capacitors includes a reference capacitor C100 of a capacitance equal to a reference capacitance CAP and N groups of capacitors, here four groups 80, 40, 20 and 10, the overall capacitance of each group following a geometric progression series of ratio

(38) $\frac{2^N}{2^n},1nN$
and of an initial value equal to the reference capacitance CAP, the capacitors of each group having a capacitance which is a multiple of the reference capacitance, the overall capacitance of the network of capacitors being equal to 2N times the reference capacitance.

(39) In operation, the signal s1 is transmitted to the input E6.

(40) Reference is now made to FIGS. 8 and 9 which respectively depict an implementation of the converter 6, and the digital encoding obtained by implementing the converter 6 from the signals s.sub.1 and s.sub.p previously defined according to time.

(41) The sampler 4 operates at the sampling frequency Fe of period T.sub.e, e.g. 1 s. It is assumed that initially the sampler 4 is off, i.e. that the signal s.sub.1 is not transmitted to the input E7, and the second terminal of each capacitor is connected to the earth via the switching circuit.

(42) In a first step 801 at instant t1, the sampler 4 is on. The signal s.sub.1 charges the network R of capacitors.

(43) In a second step 802 of storing charges, at instant t1 plus t, the signal s.sub.1 has an amplitude equal to A.sub.1. The network of capacitors is charged. The second terminals B.sub.812 and B.sub.822 are disconnected from the earth for leaving the second terminal of each capacitor floating by connecting it to the terminal B.sub.M810 and B.sub.M820 respectively.

(44) Then in step 803 of storing charges, after a duration T.sub.CM, at instant t11, the second terminals B.sub.832 and B.sub.842 are disconnected from the earth for leaving the second terminal of each capacitor floating by connecting it to the terminal B.sub.M820 and B.sub.M840 respectively. The signal s.sub.1 has an amplitude equal to A.sub.11.

(45) In step 804 of storing charges, after a duration T.sub.CM, at instant t12, the second terminals B.sub.412 and B.sub.422 are disconnected from the earth for leaving the second terminal of each capacitor floating by connecting it to the terminal B.sub.M410 and B.sub.M420 respectively. The signal s.sub.1 has an amplitude equal to A.sub.12.

(46) In step 805 of storing charges, after a duration T.sub.CM, at instant t13, the second terminals B.sub.202, B.sub.102 and B.sub.1002 are disconnected from the earth/ground potential for leaving the second terminal of each capacitor floating by connecting it to the terminal B.sub.M200, B.sub.M100 and B.sub.M1000 respectively. The signal s.sub.1 has an amplitude equal to A.sub.13.

(47) All the second terminals of the capacitors incorporated in the network of capacitors R have been successively disconnected after a predetermined duration T.sub.CM separating two disconnections from the earth for being floating.

(48) Then, in step 806, when all the capacitors have been disconnected from the earth, the sampler 4 is off.

(49) In step 807, the second terminal of each capacitor is connected to the earth. In this step, the charge contained in each capacitor is redistributed in the network R so that each capacitor stores the same charge equal to the overall charge stored in the network R divided by the total number of capacitors in the network R. Consequently, the samples of the signal s1 stored in the network R in the preceding steps are averaged.

(50) In step 808, the dichotomy algorithm known to the person skilled in the art is implemented on the value of amplitudes A.sub.100 of the signal s.sub.1 corresponding to the average of the amplitudes A.sub.1, A.sub.11, A.sub.12 and A.sub.13 recorded at instants t1, t11, t12, t13 respectively.

(51) Then in step 809, after a duration T.sub.algo equal to the duration of implementation of the dichotomy algorithm, the state machine 8 determines the digital word corresponding to the value of the signal s.sub.1 recorded by the sampler 4 and delivers the four-bit digital word.

(52) The digital word is transmitted to the output interface S6 including four outputs a6, b6, c6 and d6 by the unit UT8.

(53) The state machine 8 is configured for implementing the dichotomy algorithm used for calculating the digital word from the average by driving the switching circuit according to the output value of the comparator COMP and the signal CLK.

(54) The output a6 corresponds to the bit known to the person skilled in the art as the Most Significant Bit MSB and the output d6 corresponds here to the bit known to the person skilled in the art as the Least Significant Bit LSB.

(55) The resolution of the device 6 is such that the amplitude A1 is included in a quantum interval [C2; C3] corresponding here to the binary word 0110 while the amplitude Ap is included in a quantum interval [C3; C4] corresponding here to the digital word 0111.

(56) Then the preceding steps are repeated at instant t2 corresponding to instant t1 plus the duration T.sub.e.

(57) Four samples of the signal s1 were recorded separated by a duration T.sub.CM, then the average of these four values was calculated and finally the dichotomy algorithm was applied implemented by the converter 6 on the average value A.sub.100.

(58) The calculation of the average by charge redistribution in the network R makes it possible to filter the value of the signal s.sub.1 that will be digitized. The filter implemented during the operation of calculating the average results from the switching order of the capacitors incorporated in the network R.

(59) In order to improve the accuracy of calculating the average, the number of samples may be increased, here a maximum of eight samples may be obtained by switching successively and with a constant duration the capacitors C81 to 84, then C41, C42, C20 and finally C10 and C100 simultaneously.

(60) However, the sum of the durations of switching T.sub.CM of each capacitor or group of capacitors and of implementing the dichotomy algorithm T.sub.algo must be less than the sampling frequency T.sub.e.

(61) The duration t is negligible with respect to the duration T.sub.CM, e.g. T.sub.CM is equal to 100 ns, T.sub.algo is equal to 800 ns and t is equal to 4 ns.

(62) The capacitors are switched so that the charge switched at each instant is constant. In the example previously described, the overall switched capacitance at each of instants t1, t11, t12 and t13 is equal to twice CAP.

(63) The second terminal of capacitors is disconnected after a predetermined duration TCM so that the overall charge switched is constant.

(64) According to another embodiment, by switching different capacitors at each instant, a weighted average value is obtained.

(65) The person skilled in the art will know how adapt the number and the capacitance of the capacitors according to the frequency response of the analog-to-digital converter sought by increasing the number of samples used, on the one hand, for calculating the average of the amplitude of the signal on which the dichotomy algorithm is applied for determining the digital word associated with this value, and on the other hand, for adapting the analog-to-digital conversion device to a converter of the N-bit type, N being greater than two.

(66) Although the analog-to-digital conversion device previously described implements a dichotomy algorithm for determining a digital word, the device may, according to another implementation, implement a redundant type of algorithm known to the person skilled in the art for determining a digital word. The previously described steps of storing charges in the capacitors will be adapted to the chosen redundant type of algorithm.

(67) Furthermore, the converter 6 is configurable for optionally not using the floating terminals and connecting all the second terminals of the capacitors to the potential E7.sub.REF30 and dispensing with calculating the average in some applications.