High charge rate, large capacity, solid-state battery

Abstract

Solid-state battery structures, particularly solid-state lithium-based battery structures, which are fast charging and have a high capacity are provided. Notably, fast charging, high capacity solid-state battery structures are provided that include a plurality of solid-state-thin-film batteries that are stacked one atop the other, or that include an array of interconnected solid-state thin-film batteries, or that contain a solid-state thin-film battery located on physically exposed surfaces of fin structures.

Claims

1. A solid-state battery structure comprising: an array of solid-state thin-film batteries located on a surface of a substrate, wherein each solid-state thin-film battery of the array of solid-state thin-film batteries comprises a bottom electrode, a battery cell material stack and a top electrode; a first bus bar located on the substrate and positioned laterally adjacent to each solid-state thin-film battery of the array of solid-state thin-film batteries; a fuse element in proximity to each solid-state thin-film battery of the plurality of solid-state thin-film batteries, wherein each fuse element has a first end connected to a sidewall surface of the bottom electrode of one of the solid-state thin-film batteries and a second end connected to a sidewall surface of the first bus bar; and at least one second bus bar entirely spaced apart from the substrate and the first bus bar, wherein the at least one second bus bar has a bottommost surface that directly contacts a topmost surface of the top electrode of at least one of the solid-state thin-film batteries.

2. The solid-state battery structure of claim 1, wherein the battery cell material stack comprises a cathode and a solid-state electrolyte.

3. The solid-state battery structure of claim 2, wherein the battery cell material stack further comprises an anode region located between the solid-state electrolyte and the top electrode.

4. The solid-state battery structure of claim 3, wherein the battery cell material stack is lithium-based, the cathode comprises a lithium-based mixed oxide, and the solid-state electrolyte comprises a material that enables the conduction of lithium ions.

5. The solid-state battery structure of claim 4, wherein the anode region is composed of a plurality of lithium regions.

6. The solid-state battery structure of claim 4, wherein the anode region comprises a lithium ion generator or a lithium intercalation active material.

7. The solid-state battery structure of claim 1, wherein each fuse element is composed of a metal or metal alloy that melts when the battery is shunted and current is overflowed.

8. The solid-state battery structure of claim 7, wherein the metal or metal alloy is selected from the group consisting of indium, tin, gallium, and their alloys.

9. The solid-state battery structure of claim 1, wherein the at least one second bus bar is a single bus bar.

10. The solid-state battery structure of claim 1, wherein the at least one second bus bar comprises a plurality of spaced apart bus bars.

11. The solid-state battery structure of claim 1, further comprising a porous dielectric material encasing each fuse element.

12. The solid-state battery structure of claim 11, wherein the porous dielectric material is composed of porous carbon.

13. The solid-state battery of claim 1, wherein the battery cell material stack is located entirely above the bottom electrode, and the top electrode is located entirely above the battery cell material stack.

14. The solid-state battery of claim 1, wherein the fuse elements are configured in parallel to each other.

15. The solid-state battery of claim 1, further comprising a dielectric structure located between the second bus bar and the substrate and laterally adjacent to each of the solid-state thin-film batteries of the array of solid-state thin-film batteries.

Description

BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS

(1) FIG. 1 is a pictorial represents of an exemplary solid-state thin-film battery sheet of a battery structure located on a substrate that can be employed in the present application.

(2) FIG. 2 is a cross view of an exemplary solid-state thin-film battery structure that can be used in the solid-state thin-film battery sheet of FIG. 1.

(3) FIG. 3 is a pictorial representation of the exemplary solid-state thin-film battery sheet of FIG. 1 after cutting the battery sheet into individual solid-state thin-film battery sub-sheets and thereafter stacking the individual solid-state thin-film battery sub-sheets one atop the other.

(4) FIG. 4 is a pictorial representation of the stacked battery sub-sheet structure of FIG. 3 after providing a fuse element to each solid-state thin-film battery sub-sheet, and connecting the same to a load.

(5) FIG. 5A is a cross sectional view of an array layout containing a plurality of solid-state thin-film batteries in accordance with an embodiment of the present application.

(6) FIG. 5B is a top down view of the array layout shown in FIG. 5A prior to forming a dielectric structure and at least one second bus bar.

(7) FIG. 6 is a cross sectional view of another array layout including a plurality of battery levels containing arrays of solid-state thin-film batteries stacked one atop the other.

(8) FIG. 7 is a cross sectional view of another solid-state battery structure of the present application.

(9) FIG. 8 is a cross sectional view of yet another solid-state battery structure of the present application.

DETAILED DESCRIPTION

(10) The present application will now be described in greater detail by referring to the following discussion and drawings that accompany the present application. It is noted that the drawings of the present application are provided for illustrative purposes only and, as such, the drawings are not drawn to scale. It is also noted that like and corresponding elements are referred to by like reference numerals.

(11) In the following description, numerous specific details are set forth, such as particular structures, components, materials, dimensions, processing steps and techniques, in order to provide an understanding of the various embodiments of the present application. However, it will be appreciated by one of ordinary skill in the art that the various embodiments of the present application may be practiced without these specific details. In other instances, well-known structures or processing steps have not been described in detail in order to avoid obscuring the present application.

(12) It will be understood that when an element as a layer, region or substrate is referred to as being on or over another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being directly on or directly over another element, there are no intervening elements present. It will also be understood that when an element is referred to as being beneath or under another element, it can be directly beneath or under the other element, or intervening elements may be present. In contrast, when an element is referred to as being directly beneath or directly under another element, there are no intervening elements present.

(13) Referring first to FIG. 1, there is illustrated an exemplary solid-state thin-film battery sheet of a solid-state thin-film battery structure 12 located on a substrate 10 that can be employed in the present application. As is shown, the solid-state thin-film battery structure 12 is continuously (without any breaks or gaps) present on the entirety of the substrate 10. In FIG. 1, the dotted lines represent locations in which subsequent cutting of the exemplary solid-state thin-film battery sheet (10, 12) will be performed.

(14) The substrate 10 that can be employed in the present application includes any conventional material that is used as a substrate for a solid-state thin-film battery. In one embodiment, the substrate 10 may include one or more semiconductor materials. The term semiconductor material is used throughout the present application to denote a material having semiconducting properties.

(15) Examples of semiconductor materials that may be employed as substrate 10 include silicon (Si), germanium (Ge), silicon germanium alloys (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), III-V compound semiconductors or II-VI compound semiconductors. III-V compound semiconductors are materials that include at least one element from Group III of the Periodic Table of Elements and at least one element from Group V of the Periodic Table of Elements. II-VI compound semiconductors are materials that include at least one element from Group II of the Periodic Table of Elements and at least one element from Group VI of the Periodic Table of Elements.

(16) In one embodiment, the semiconductor material that may provide substrate 10 is a bulk semiconductor substrate. By bulk it is meant that the substrate 10 is entirely composed of at least one semiconductor material, as defined above. In one example, the substrate 10 may be entirely composed of silicon. In some embodiments, the bulk semiconductor substrate may include a multilayered semiconductor material stack including at least two different semiconductor materials, as defined above. In one example, the multilayered semiconductor material stack may comprise, in any order, a stack of Si and a silicon germanium alloy.

(17) In another embodiment, substrate 10 is composed of a topmost semiconductor material layer of a semiconductor-on-insulator (SOI) substrate. The SOI substrate would also include a handle substrate (not shown) including one of the above mentioned semiconductor materials, and an insulator layer (not shown) such as a buried oxide below the topmost semiconductor material layer.

(18) In any of the embodiments mentioned above, the semiconductor material that may provide the substrate 10 may be a single crystalline semiconductor material. The semiconductor material that may provide the substrate 10 may have any of the well known crystal orientations. For example, the crystal orientation of the semiconductor material that may provide substrate 10 may be {100}, {110}, or {111}. Other crystallographic orientations besides those specifically mentioned can also be used in the present application.

(19) In yet another embodiment, the substrate 10 is a dielectric material such as, for example, doped or non-doped silicate glass, silicon dioxide, or silicon nitride. In yet a further embodiment, the substrate 10 is composed of a polymer or flexible substrate material such as, for example, a polyimide, a polyether ketone (PEEK) or a transparent conductive polyester. In yet an even further embodiment, the substrate 10 may be composed of a multilayered stack of at least two of the above mentioned substrate materials, e.g., a stack of silicon and silicon dioxide.

(20) The substrate 10 that can be used in the present application can have a thickness from 10 m to 5 mm. Other thicknesses that are lesser than, or greater than, the aforementioned thickness values may also be used for substrate 10.

(21) In some embodiments, the substrate 10 may have a non-textured (flat or planar) surface. The term non-textured surface denotes a surface that is smooth and has a surface roughness on the order of less than 100 nm root mean square as measured by profilometry. In yet another embodiment, the substrate 10 may have a textured surface. In such an embodiment, the surface roughness of the textured substrate can be in a range from 100 nm root mean square to 100 m root mean square as also measured by profilometry. Texturing can be performed by forming a plurality of etching masks (e.g., metal, insulator, or polymer) on the surface of a non-textured substrate, etching the non-textured substrate utilizing the plurality of masks as an etch mask, and removing the etch masks from the non-textured surface of the substrate. In some embodiments, the textured surface of the substrate is composed of a plurality of pyramids. In yet another embodiment, the textured surface of the substrate is composed of a plurality of cones. In some embodiments, a plurality of metallic masks are used, which may be formed by depositing a layer of a metallic material and then performing an anneal. During the anneal, the layer of metallic material melts and balls-ups such that de-wetting of the surface of the substrate occurs. Details concerning the use of metallic masks in texturing a surface of a substrate can be found in co-pending and co-assigned U.S. patent application Ser. No. 15/474,434, filed on Mar. 30, 2017, the entire content of which is incorporated herein by reference.

(22) The solid-state thin-film battery structure 12 includes solid-state thin-film battery materials which can be formed one atop the other on substrate 10 utilizing conventional deposition processes well known to those skilled in the art. Notably, the solid-state thin-film battery structure 12 comprises a bottom electrode, a cathode layer, a solid-state electrolyte layer and a top electrode. In some embodiments, the battery structure 12 may further include an anode region located between the solid-state electrolyte layer and the top electrode. The anode region may or may not be continuously present between the solid-state electrolyte layer and the top electrode. The anode region may be a deposited anode material, or it may be generated during a charging/recharging process. In a further embodiment, the solid-state thin-film battery structure 12 may even further include a liner located between the solid-state electrolyte layer and the anode region. Collectively, the material layers of the solid-state thin-film battery structure 12 located between the bottom electrode and the top electrode define a battery cell material stack.

(23) An exemplary solid-state thin-film battery structure 12 that can be employed is shown in FIG. 2. In one embodiment, the solid-state thin-film battery structure 12 shown in FIG. 2 is a solid-state thin-film lithium-based battery. Although a solid-state thin-film lithium-based battery is exemplified herein as the solid-state thin-film battery structure 12, other types of solid-state thin-film battery structures can be employed in the present application. Although FIG. 2 discloses the anode region 22 being located above the cathode layer 16, one skilled in the art would appreciate that the anode region 22 may be located beneath the cathode layer 16 by flipping the orientation of the solid-state thin-film battery structure shown in FIG. 2.

(24) The solid-state thin-film battery structure 12 shown in FIG. 2 includes a bottom electrode 14, a cathode layer 16, a solid-state electrolyte layer 18, an optional liner 20, an anode region 22 and a top electrode 24. As stated above, the anode region 22 may be a deposited anode material, or it may be generated during a charging/recharging process. Collectively, the cathode layer 16, the solid-state electrolyte layer 18, the optional liner 20, and the anode region 22 may be referred to as a battery cell material stack 13.

(25) The bottom electrode 14 of the solid-state thin-film battery structure 12 illustrated in FIG. 2 may include any metallic electrode material such as, for example, titanium (Ti), platinum (Pt), nickel (Ni), aluminum (Al) or titanium nitride (TiN). In one example, the bottom electrode 14 includes a stack of, from bottom to top, titanium (Ti), platinum (Pt) and titanium (Ti). The bottom electrode 14 may be formed utilizing a deposition process including, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), evaporation, sputtering, or plating. The bottom electrode 14 may have a thickness from 10 nm to 500 nm. Other thicknesses that are lesser than, or greater than, the aforementioned thickness values may also be used for the bottom electrode 14.

(26) The cathode layer 16 of the solid-state thin-film battery structure 12 illustrated in FIG. 2 may include a lithiated material such as, for example, a lithium-based mixed oxide. Hence, the cathode layer 16 illustrated in FIG. 2 may be referred to as a lithiated cathode material layer. Examples of lithium-based mixed oxides that may be employed as the cathode layer 16 include, but are not limited to, lithium cobalt oxide (LiCoO.sub.2), lithium nickel oxide (LiNiO.sub.2), lithium manganese oxide (LiMn.sub.2O.sub.4), lithium vanadium pentoxide (LiV.sub.2O.sub.5) or lithium iron phosphate (LiFePO.sub.4). The cathode layer 16 illustrated in FIG. 2 may have a thickness from 10 nm to 20 m. Other thicknesses that are lesser than, or greater than, the aforementioned thickness values may also be used for cathode layer 16 of the solid-state thin-film battery structure 12.

(27) The cathode layer 16 of the solid-state thin-film battery structure 12 illustrated in FIG. 2 may be formed utilizing a deposition process such as, sputtering or plating. In one embodiment, the cathode layer 16 is formed by sputtering utilizing any conventional precursor source material or combination of precursor source materials. In one example, a lithium precursor source material and a cobalt precursor source material are employed in forming a lithium cobalt mixed oxide. Sputtering may be performed in an admixture of an inert gas and oxygen. In such an embodiment, the oxygen content of the inert gas/oxygen admixture can be from 0.1 atomic percent to 70 atomic percent, the remainder of the admixture includes the inert gas. Examples of inert gases that may be used include argon, helium, neon, nitrogen or any combination thereof.

(28) The solid-state electrolyte layer 18 of the solid-state thin-film battery structure 12 illustrated in FIG. 2 includes a material that enables the conduction of lithium ions; the solid-state electrolyte layer 18 may be referred to as a lithium-based solid-state electrolyte layer. Such materials may be electrically insulating or ionic conducting. Examples of materials that can be employed as the solid-state electrolyte layer 18 include, but are not limited to, lithium phosphorus oxynitride (LiPON) or lithium phosphosilicate oxynitride (LiSiPON).

(29) The solid-state electrolyte layer 18 may be formed utilizing a deposition process such as, sputtering or plating. In one embodiment, the solid-state electrolyte layer 18 of the lithium-based battery stack is formed by sputtering utilizing any conventional precursor source material. Sputtering may be performed in the presence of at least a nitrogen-containing ambient. Examples of nitrogen-containing ambients that can be employed include, but are not limited to, N.sub.2, NH.sub.3, NH.sub.4, NO, or NH.sub.x wherein x is between 0 and 1. Mixtures of the aforementioned nitrogen-containing ambients can also be employed. In some embodiments, the nitrogen-containing ambient is used neat, i.e., non-diluted. In other embodiments, the nitrogen-containing ambient can be diluted with an inert gas such as, for example, helium (He), neon (Ne), argon (Ar) and mixtures thereof. The content of nitrogen (N.sub.2) within the nitrogen-containing ambient employed is typically from 10% to 100%, with a nitrogen content within the ambient from 50% to 100% being more typical.

(30) The solid-state electrolyte layer 18 of the battery structure 12 illustrated in FIG. 2 may have a thickness from 10 nm to 10 m. Other thicknesses that are lesser than, or greater than, the aforementioned thickness values may also be used for the solid-state electrolyte layer 18.

(31) The liner 20 that may be present in the solid-state thin-film battery structure 12 illustrated in FIG. 2 is a continuous layer that covers the entirety of the solid-state electrolyte layer 18; in some embodiments the liner 20 is omitted. In one embodiment, the liner is a lithium nucleation enhancement liner. In such an embodiment, the lithium nucleation enhancement liner includes a material that can facilitate the subsequent nucleation of lithium upon performing a charging/recharging process. In one embodiment, lithium nucleation enhancement liner that can be used as liner 20 is composed of gold (Au), silver (Ag), zinc (Zn), magnesium (Mg), tantalum (Ta), tungsten (W), molybdenum (Mo), a titanium-zirconium-molybdenum alloy (TZM), or silicon (Si). Detailed description of lithium nucleation enhancement liners can be found in co-pending and co-assigned U.S. patent application Ser. No. 15/474,668, filed Mar. 30, 2017, the entire content of which is incorporated herein by reference. In another embodiment, liner 20 is a barrier material such as, for example, LiF.

(32) The liner 20 can be formed utilizing a deposition process. Examples of deposition processes than can be used in forming the liner 24 include chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), evaporation, sputtering or plating. The liner 20 typically has a thickness that is greater than 1 nm. In one embodiment and when employed, the liner 20 has a thickness from 2 nm to 20 nm.

(33) The anode region 22 of the solid-state thin-film battery structure 12 illustrated in FIG. 2 includes any material that is a lithium ion generator or lithium intercalation active material. Examples of materials that may be used as anode region 22 include, but are not limited to, lithium metal, a lithium-base alloy such as, for example, Li.sub.xSi, or a lithium-based mixed oxide such as, for example, lithium titanium oxide (Li.sub.2TiO.sub.3). The anode region 22 may be a continuous layer or it may be composed of a plurality of non-continuous regions.

(34) In some embodiments, the anode region 22 is formed prior to performing a charging/recharging process. In such an embodiment, the anode region 22 can be formed utilizing a deposition processes such as, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), evaporation, sputtering or plating. In other embodiments, the anode region 22 is a lithium accumulation region that is formed during a charging/recharging process.

(35) The top electrode 24 of the solid-state thin-film battery structure 12 illustrated in FIG. 2 may include any metallic electrode material such as, for example, titanium (Ti), platinum (Pt), nickel (Ni), copper (Cu) or titanium nitride (TiN). In one example, the top electrode 24 includes a stack of, from bottom to top, nickel (Ni) and copper (Cu). In one embodiment, the metallic electrode material that provides the top electrode 24 may be the same as the metallic electrode material that provides the bottom electrode 14. In another embodiment, the metallic electrode material that provides the top electrode 24 may be different from the metallic electrode material that provides the bottom electrode 14. The top electrode 24 may be formed utilizing one of the deposition processes mentioned above for forming the bottom electrode 14. The top electrode 24 may have a thickness within the range mentioned above for the bottom electrode 14. In the present application, top electrode 24 may be referred to as an anode-side electrode, while bottom electrode 12 may be referred to as a cathode-side electrode.

(36) Referring now to FIG. 3, there is illustrated the exemplary solid-state thin-film battery sheet of FIG. 1 after cutting the battery sheet (10, 12) into individual solid-state thin-film battery sub-sheets (10P, 12P) and thereafter stacking the individual solid-state thin-film battery sub-sheets (10P, 12P) one atop the other to provide a vertically stacked solid-state battery structure. In the present application, element 10P denotes a substrate material portion, while element 12P denotes a solid-state thin-film battery structure portion. Each solid-state thin-film battery structure portion 12P includes a remaining portion of the bottom electrode 12, a remaining portion of the battery cell material stack 13, and a remaining portion of the top electrode 24. In the illustrated embodiment, cutting is performed along the dotted lines shown in FIG. 1.

(37) The number of individual solid-state thin-film battery sub-sheets (10P, 12P) that can be present in the vertically stacked solid-state battery structure may vary and is not limited to 3 solid-state thin-film battery sub-sheets (10P, 12P) as shown in FIG. 3. For example, 10, 20, 30, 40, etc. battery sub-sheets (10P, 12P) may be stacked one atop the other.

(38) The size (i.e., length and width) of each individual solid-state thin-film battery sub-sheet (10P, 12P) may be determined by the defect density of the battery sheet. In one example, the length of each individual solid-state thin-film battery sub-sheet (10P, 12P) may be from 100 nm 1 meter, while the width may be from 100 nm to 1 meter. Other lengths and widths may also be used in the present application for each solid-state thin-film battery sub-sheet (10P, 12P). Upon stacking, which may be performed by hand or by mechanical means such as a robot arm, and as is shown, the sidewall surfaces of each individual solid-state thin-film battery sub-sheet (10P, 12P) are vertically aligned to each other.

(39) Cutting may be performed utilizing techniques that are well known to those skilled in the art. In one example, the cutting process may include dicing. In another example, the cutting process may include sawing.

(40) Referring now to FIG. 4, there is illustrated the vertically stacked solid-state battery structure of FIG. 3 after providing a fuse element 26 to each solid-state thin-film battery sub-sheet (10P, 12P), and connecting the same to a load 28. Each fuse element 26 is in proximity to one of the solid-state thin-film battery sub-sheets (10P, 12P). Collectively, the fuse elements 26 are configured to be in parallel with one another. That is, the fuse elements 26 are arranged so as to provide a same voltage potential to each solid-state thin-film battery sub-sheet (10P, 12P).

(41) The fuse elements 26 may include a metal or metal alloy that melts when the device is shunted and current is overflowed. In one example, the fuse elements 26 include indium, tin, gallium, or alloys thereof. The fuse elements 26 may be formed utilizing conventional techniques including deposition that are well known to those skilled in the art. Each fuse element 26 can be provided to the vertically stacked solid-state thin-film battery structure of FIG. 3 by depositing and etching a metal or metal alloy that provides the fuse elements 26. The fuse elements 26 are typically formed prior to the stacking process.

(42) In some embodiments (not shown in this embodiment), each fuse element 26 can be located in a dielectric material (not shown). In some embodiments, the dielectric material that encases each fuse element 26 may be a porous dielectric material such as, for example, porous carbon. In some embodiments (also not shown), the vertically stacked solid-state thin-film battery structure can be located within an air and/or moisture impermeable structure. The air and/or moisture impermeable structure includes any air and/or moisture impermeable material or multilayered stack of such materials. Examples of air and/or moisture impermeable materials that can be employed in the present application include, but are not limited to, parylene, a fluoropolymer, silicon nitride, and/or silicon dioxide. The air and/or moisture impermeable structure may be formed depositing the air and/or moisture impermeable material.

(43) The load 28 that can be used in the present application includes a source (i.e., charging element) that can provide a voltage to the exemplary structure shown in FIG. 4. The voltage that can be used in exemplary structure shown in FIG. 4 may vary. In one example, the voltage can be from 2 volts to 5 volts. The load 28 may be used to charge/recharge the exemplary vertical stacked solid-state battery structure shown in FIG. 4.

(44) Notably, FIG. 4 shows a solid-state battery structure in accordance with the present application. In this embodiment, the solid-state battery structure includes a plurality of solid-state thin-film battery sub-sheets (10P, 12P) vertically stacked one atop the other. A plurality of fuse elements 26 is located in proximity to the plurality of solid-state thin-film battery sub-sheets (10P, 12P). Each solid-state thin-film battery sub-sheet (10P, 12P) of the plurality of solid-state thin-film battery sub-sheets is connected to one fuse element 26, and the fuse elements 26 of the plurality of fuse elements are configured to be in parallel with one another. A load 28 is present which has a first connection to the parallel arrangement of fuse elements 26, and a second connection to the various solid-state thin-film battery structures portions 12P.

(45) Referring now to FIG. 5A, there is illustrated an array layout for a solid-state battery structure of the present application which contains a plurality of solid-state thin-film batteries. In this embodiment, the solid-state battery structure includes an array of solid-state thin-film batteries located on a surface of a substrate 10, each solid-state thin-film battery of the array of solid-state thin-film batteries comprises a bottom electrode 14 (as defined above), a battery cell material stack 13 (as defined above), and a top electrode 24 (as defined above). The battery cell material stack 13 includes the cathode layer 16, the solid-state electrolyte layer 18, the optional liner 20, and the anode region 22 as defined above. In some embodiments (and as shown in FIG. 5A), the top electrode 24 may have sidewall surfaces that are non-vertically aligned with the sidewall surfaces of the underlying battery cell material stack 13. In other embodiments, the top electrode 24 may have sidewall surfaces that are vertically aligned with the sidewall surfaces of the underlying battery cell material stack 13.

(46) In one embodiment, each solid-state thin-film battery structure of the array shown in FIG. 5A may be formed utilizing a lift-off process such as disclosed in co-pending and co-assigned U.S. patent application Ser. No. 15/474,570, filed Mar. 30, 2017, the entire content of which is incorporated herein by reference. In another embodiment, each solid-state thin-film battery structure can be formed utilizing a non-lift off process. In such an embodiment, each solid-state thin-film battery structure can be formed by deposition of the various battery layers and thereafter subjecting the same to a patterning step such as, for example, lithography and etching.

(47) The exemplary solid-state battery structure shown in FIG. 5A also includes a plurality of fuse elements 26 (as defined above). Each fuse element 26 of the plurality of fuse elements has a first end connected to the bottom electrode 14 of one of the solid-state thin-film batteries and a second end connected to a first bus bar 32. Each fuse element 26 may be formed as described above and may be encased in dielectric material 30.

(48) In some embodiments, the dielectric material 30 that encases each fuse element 26 may be a porous dielectric material such as, for example, porous carbon. The dielectric material 30 may be formed utilizing deposition and etching.

(49) The solid-state battery structure of FIG. 5A also includes first bus bars 32 located on the surface of substrate 10, and at least one second bus bar 36 is located above, and spaced apart from, each first bus bar 32, wherein the at least one second bus bar 36 contacts a surface of the top electrode 24 of each solid-state thin-film battery. In some embodiments, a single second bus bar 36 is employed and is present on the entirety of the structure. In other embodiments, a plurality of spaced apart second bus bars 36 is employed. Each first bus bar 32 and each second bus bar 36 includes a contact metal or metal alloy. Illustrative examples of contact metals or metal alloys that may be employed for the first and second bus bars (32, 36) include, tungsten, copper, aluminum, or copper-aluminum alloys. The first bus bars 32 may be formed by deposition and etching, the at least one second bus bar 36 may be formed by deposition. A patterning process may also be used in providing multiple second bus bars 36. As is shown in the top down view of FIG. 5B the fuse elements 26 are configured in parallel to each other.

(50) Prior to forming the at least one second bus bar 36, a dielectric structure 34 is formed surrounding each solid-state thin-film battery, each fuse element 26, each dielectric material 30, and each first bus bar 32. Dielectric structure 34 may include any air and/or moisture impermeable material or multilayered stack of such materials. Examples of air and/or moisture impermeable materials that can be employed in the present application include, but are not limited to, parylene, a fluoropolymer, silicon nitride, and/or silicon dioxide. The dielectric structure 34 may be formed by first depositing the air and/or moisture impermeable material and thereafter a planarization process can be used to provide a topmost surface that is coplanar with a topmost surface of each top electrode 24.

(51) In some embodiments and additional arrays of solid-state thin-film batteries can be stacked one atop the other. Each level can be formed utilizing the materials and technique mentioned above in providing the structure shown in FIG. 5A. In one example and as shown in FIG. 6, a solid-state battery structure is provided that includes a first battery level L1 comprising an array of solid-state thin-film batteries (14, 13, 24) located on a surface of a substrate 10 and a fuse element 26 in proximity to each solid-state thin-film battery of the plurality of solid-state thin-film batteries. The fuse elements 26 are encased in dielectric material 30 as defined above. Each fuse element 26 in the first battery level L1 has a first end connected to a bottom electrode 14 of one of the solid-state thin-film batteries in the first battery level L1 and a second end connected to a first bus bar 32 in the first battery level L1. The first bus bars 32 in the first battery level are located on the substrate 10. A dielectric structure 34 as defined above is also present in the first battery level L1. At least one second bus bar 36 is located above, and spaced apart from, each first bus bar 32 in the first battery level L1, wherein the at least one second bus bar 36 contacts a surface of a top electrode 24 of each solid-state thin-film battery in the first battery level L1. A second battery level L2 comprising an array of solid-state thin-film batteries (14, 13, 24) is located above the at least one second bus bar 36 that is present atop the first battery level. The second level L2 does not include any dielectric material 30 and fuse elements 32. In the present application, the top electrode 24 of the solid-state thin-film batteries in the first battery level L1 are the same type (i.e., anode-side electrode or cathode side-electrode) as the bottom electrode 14 of the solid-state thin-film batteries in the second battery level L2.

(52) In some embodiments, a third battery level L3 is formed atop the second battery level L2. In such an embodiment, the third battery level L3 comprises an array of solid-state thin-film (14, 13, 24) batteries and a fuse element 26 in proximity to each solid-state thin-film battery of the plurality of solid-state thin-film batteries in the third battery level L3. Each fuse element 26 in the third battery level has a first end connected to a bottom electrode 14 of one of the solid-state thin-film batteries in the third battery level L3 and a second end connected to a first bus bar 32 in the third battery level L3. The fuse elements 26 in the third battery level are encased in dielectric material 30, and the third level also includes dielectric structure 34. At least one second bus bar 36 is located on the third battery level L3. In accordance with the present application, each bottom electrode 14 of the plurality of solid-state thin-film batteries present in the third battery level L3 is in direct connect with one of the top electrodes 24 within the second battery level L2, and the bottom electrodes 14 of the plurality of solid-state thin-film batteries present in the third battery level L3 are of the same type (i.e., cathode-side or anode-side) as the top electrodes 24 of the plurality of solid-state thin-film batteries present in the second battery level L2. A fourth battery level L4 that is the same as the second battery level L2 can be formed atop the third battery level L3, and a fifth battery level L5 that is the same as the first and third battery levels (L1 and L3) can be formed atop the fourth battery level. A second bus bar 36 can be formed onto the fifth battery level L5. Additional battery levels can be formed atop the structure shown in FIG. 6 implying the same repetition of different battery levels.

(53) Referring now to FIG. 7, there is shown a yet other solid-state battery structure in accordance with the present application. In this embodiment, the solid-state battery structure includes a plurality of substrate layers 10 (as defined above) and dielectric material layers 35 stacked one atop the other, wherein each dielectric material layer 35 includes a solid-state thin-film battery located therein, wherein each solid-state thin-film battery comprises at least a bottom electrode 14 (as defined above), a cathode (not shown), a solid-state electrolyte (not shown), and a top electrode 24 (as defined above). A first via-filled contact structure 50 interconnects each bottom electrode together 14, and a second via-filled contact structure 52 interconnects each top electrode 24 together. Each solid-state thin-film battery may include an anode region and an optional liner. For clarity, the cathode, the solid-state electrolyte, optional liner and anode region are not shown in the drawing.

(54) The structure can be formed by first forming a plurality of structures including at least one solid-state thin-film battery (including one of the lithium-based batteries defined above) located on a surface of substrate 10. Dielectric material 35 layers which includes any air and/or moisture impermeable material or multilayered stack of such materials is then formed surrounding the at least one solid-state thin-film battery. Examples of air and/or moisture impermeable materials that can be employed in the present application include, but are not limited to, parylene, a fluoropolymer, silicon nitride, and/or silicon dioxide. The dielectric material layer 35 may be formed by first depositing the air and/or moisture impermeable material and thereafter a planarization process can be used to provide a topmost surface that is coplanar with a topmost surface of each top electrode 24. Each structure is then stacked one atop the other, and then contact openings are formed therein. The contact openings are then filled with a contact metal or metal alloy as defined above and then a planarization process is employed to provide the structure shown in FIG. 7.

(55) Referring now to FIG. 8, there is illustrated yet further solid-state battery structure of the present application. The exemplary solid-state battery structure of FIG. 8 includes at least one fin structure 10F (three fin structures are shown by way of one example) extending upwards from base substrate 10B. A solid-state thin-film battery structure is located on physically exposed surfaces of the at least one fin structure 10F and on physically exposed surfaces of the base substrate 10B. The solid-state thin-film battery structure includes a bottom electrode 12 (as defined above), a battery cell material stack 13 (as defined above), and a top electrode 24 (as defined above).

(56) The exemplary solid-state battery structure of FIG. 8 can be formed by first providing a substrate (as defined above). The substrate can then be patterned to define the fin structures 10F and the base substrate 10B. In such an embodiment, the fin structures 10F and the base substrate 10B are of unitary construction and comprise a same material. In other embodiments, a base substrate which includes one of the materials mentioned above for substrate 10 is provided. A dielectric structure having openings that expose the base substrate is then provided, and the fin structures are thereafter grown from the physically exposed surface of the base substrate 10 utilizing a conventional epitaxial growth process. The dielectric structure is then removed, and thereafter the various components of the solid-state thin-film battery structure are deposited. Following the deposition of each component, the deposited layer may be lithographically patterned to provide the exemplary solid-state battery structure shown in FIG. 8.

(57) The exemplary solid-state battery structures of the present application (and as shown in FIGS. 4, 5A, 6, 7 and 8) have a fast charge rate C, wherein C is the total charge capacity/hr. By fast charge rate C it is meant a charge rate of 3 C or greater. In some embodiments and in which no lithium anode is intentionally deposited in the battery cell material stack, the charging process may include the charging process disclosed in co-pending and co-assigned U.S. patent application Ser. No. 15/474,640, filed on Mar. 30, 2017; the entire content of which is incorporated herein by reference. In such an embodiment, charging includes at least an initial charge stage in which a charge rate of 5 C or greater is performed for a period of time of 50 seconds or less. Further charging at or below the charge rate of 5 C may follow the initial charge stage.

(58) While the present application has been particularly shown and described with respect to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in forms and details may be made without departing from the spirit and scope of the present application. It is therefore intended that the present application not be limited to the exact forms and details described and illustrated, but fall within the scope of the appended claims.