Receiver having equalization with iterative parallel processing and noise de-whitening mitigation

Abstract

This disclosure describes a receiver having equalization with noise de-whitening mitigation for wireless communication. An input port receives, via an antenna, a signal communicated over a wireless communication link, the signal comprising a noise component. Control circuitry performs zero forcing equalization of the received signal to generate a zero forcing equalization result signal. The zero forcing equalization causes de-whitening of the noise component by increasing a correlation among elements of the noise component. The control circuitry mitigates the de-whitening of the noise component by: determining a noise variance value based on channel properties of the wireless communication link, and modifying the zero forcing equalization result signal based on the noise variance value. The modified zero forcing equalization result signal is communicated, via an output port, to log-likelihood ratio (LLR) generation circuitry for LLR computation.

Claims

1. A receiver having equalization with noise de-whitening mitigation for wireless communication, comprising: an input port configured to receive, via an antenna, a signal communicated over a wireless communication link, the signal comprising a noise component; control circuitry configured to: perform zero forcing equalization of the received signal to generate a zero forcing equalization result signal, the zero forcing equalization causing de-whitening of the noise component by increasing a correlation among elements of the noise component; and mitigate the de-whitening of the noise component by: determining a noise variance value based on channel properties of the wireless communication link, and modifying the zero forcing equalization result signal based on the noise variance value; and an output port configured to communicate the modified zero forcing equalization result signal to log-likelihood ratio (LLR) generation circuitry for LLR computation, wherein the control circuitry is further configured to: decompose a channel matrix, which describes the channel properties for the wireless communication link, to determine a constituent component of the channel matrix; perform scaling of the constituent component of the channel matrix; and compute a diagonalizer of the constituent component based on the scaled constituent component, wherein the generation of the zero forcing equalization result signal is based at least in part on the diagonalizer of the constituent component.

2. The receiver of claim 1, wherein the control circuitry is configured to perform zero forcing equalization of components of the received signal in an iterative manner by reusing results of prior computations for other components of the received signal.

3. The receiver of claim 1, wherein the received signal comprises a plurality of transmitted data streams and the control circuitry is further configured to concurrently perform, in parallel, zero forcing equalization upon each of the transmitted data streams.

4. The receiver of claim 1, wherein the constituent component is a matrix and the control circuitry is further configured to compute each column of the diagonalizer of the constituent component matrix by setting a value of each entry of the column, that has a row index greater than a row index of a diagonal entry of the column, equal to zero.

5. The receiver of claim 1, wherein the scaled component is a scaled matrix, each entry of the scaled matrix has a row index and a column index, and the control circuitry is further configured to generate the scaled matrix by: setting a value of each diagonal entry of the scaled matrix equal to one; setting to zero a value of each entry of the scaled matrix for which the row index is greater than the column index; and determining a value of each entry of the scaled matrix for which the row index is less than the column index, by scaling an entry of the constituent component, that has the row index and the column index, by an inverse of a diagonal entry of the constituent component having the column index.

6. A receiver having equalization with noise de-whitening mitigation for wireless communication, comprising: an input port configured to receive, via an antenna, a signal communicated over a wireless communication link, the signal comprising a noise component; control circuitry configured to: perform zero forcing equalization of the received signal to generate a zero forcing equalization result signal, the zero forcing equalization causing de-whitening of the noise component by increasing a correlation among elements of the noise component; and mitigate the de-whitening of the noise component by: determining a noise variance value based on channel properties of the wireless communication link, and modifying the zero forcing equalization result signal based on the noise variance value; and an output port configured to communicate the modified zero forcing equalization result signal to log-likelihood ratio (LLR) generation circuitry for LLR computation, the control circuitry being further configured to compute a gain value for each of one or more wirelessly transmitted data streams based on the noise variance value and output the gain value via the output port.

7. A receiver having equalization with noise de-whitening mitigation for wireless communication, comprising: an input port configured to receive, via an antenna, a signal communicated over a wireless communication link, the signal comprising a noise component; control circuitry configured to: perform zero forcing equalization of the received signal to generate a zero forcing equalization result signal, the zero forcing equalization causing de-whitening of the noise component by increasing a correlation among elements of the noise component; and mitigate the de-whitening of the noise component by: determining a noise variance value based on channel properties of the wireless communication link, and modifying the zero forcing equalization result signal based on the noise variance value; and an output port configured to communicate the modified zero forcing equalization result signal to log-likelihood ratio (LLR) generation circuitry for LLR computation, the control circuitry being further configured to: decompose a channel matrix, which describes the channel properties for the wireless communication link, to determine a constituent component of the channel matrix; generate, based on the received signal and the constituent component, an intermediate signal value having a noise vector, wherein the zero forcing equalization result signal is generated based at least in part on the intermediate signal value; and mitigate de-whitening of elements of the noise vector based on the noise variance value.

8. The receiver of claim 7, wherein the received signal comprises a total number of wirelessly transmitted data streams and the control circuitry is further configured to generate the intermediate signal value by extracting, from a value derived from the constituent component and the received signal, a number of rows equal to the total number of wirelessly transmitted data streams.

9. The receiver of claim 7, wherein the control circuitry is further configured to modify the zero forcing equalization result signal by: dividing the zero forcing equalization result signal by a square root of the noise variance value.

10. A method for receiving a signal in a wireless communication device, the method comprising: receiving, at an input port via an antenna, a signal communicated over a wireless communication link, the signal comprising a noise component; performing zero forcing equalization of the received signal to generate a zero forcing equalization result signal, the zero forcing equalization causing de-whitening of the noise component by increasing a correlation among elements of the noise component; mitigating the de-whitening of the noise component by: determining a noise variance value based on channel properties of the wireless communication link, and modifying the zero forcing equalization result signal based on the noise variance value; and communicating, via an output port, the modified zero forcing equalization result signal to log-likelihood ratio (LLR) generation circuitry for LLR computation, wherein the method further comprises: decomposing a channel matrix, which describes the channel properties for the wireless communication link, to determine a constituent component of the channel matrix; performing scaling of the constituent component of the channel matrix; and computing a diagonalizer of the constituent component based on the scaled constituent component, wherein the zero forcing equalization result signal is generated based at least in part on the diagonalizer of the constituent component.

11. The method of claim 10, wherein zero forcing equalization of components of the received signal is performed in an iterative manner by reusing results of prior computations for other components of the received signal.

12. The method of claim 10, wherein the received signal comprises a plurality of transmitted data streams and the method further comprises concurrently performing, in parallel, zero forcing equalization upon each of the transmitted data streams.

13. The method of claim 10, wherein the constituent component is a matrix and the method further comprises computing each column of the diagonalizer of the constituent component matrix by setting a value of each entry of the column, that has a row index greater than a row index of a diagonal entry of the column, equal to zero.

14. The method of claim 10, wherein the scaled component is a scaled matrix, each entry of the scaled matrix has a row index and a column index, and generating the scaled matrix comprises: setting a value of each diagonal entry of the scaled matrix equal to one; setting to zero a value of each entry of the scaled matrix for which the row index is greater than the column index; and determining a value of each entry of the scaled matrix for which the row index is less than the column index, by scaling an entry of the constituent component, that has the row index and the column index, by an inverse of a diagonal entry of the constituent component having the column index.

15. A method for receiving a signal in a wireless communication device, the method comprising: receiving, at an input port via an antenna, a signal communicated over a wireless communication link, the signal comprising a noise component; performing zero forcing equalization of the received signal to generate a zero forcing equalization result signal, the zero forcing equalization causing de-whitening of the noise component by increasing a correlation among elements of the noise component; mitigating the de-whitening of the noise component by: determining a noise variance value based on channel properties of the wireless communication link, and modifying the zero forcing equalization result signal based on the noise variance value; and communicating, via an output port, the modified zero forcing equalization result signal to log-likelihood ratio (LLR) generation circuitry for LLR computation, wherein the method further comprises: computing a gain value for each of one or more wirelessly transmitted data streams based on the noise variance value; and outputting the gain value via the output port.

16. A method for receiving a signal in a wireless communication device, the method comprising: receiving, at an input port via an antenna, a signal communicated over a wireless communication link, the signal comprising a noise component; performing zero forcing equalization of the received signal to generate a zero forcing equalization result signal, the zero forcing equalization causing de-whitening of the noise component by increasing a correlation among elements of the noise component; mitigating the de-whitening of the noise component by: determining a noise variance value based on channel properties of the wireless communication link, and modifying the zero forcing equalization result signal based on the noise variance value; and communicating, via an output port, the modified zero forcing equalization result signal to log-likelihood ratio (LLR) generation circuitry for LLR computation, wherein the method further comprises: decomposing a channel matrix, which describes the channel properties for the wireless communication link, to determine a constituent component of the channel matrix; generating, based on the received signal and the constituent component, an intermediate signal value having a noise vector, wherein the zero forcing equalization result signal is generated based at least in part on the intermediate signal value, and mitigating de-whitening of elements of the noise vector based on the noise variance value.

17. The method of claim 16, wherein the received signal comprises a total number of wirelessly transmitted data streams and generating the intermediate signal value comprises extracting from a value derived from the constituent component, a number of rows equal to the total number of wirelessly transmitted data streams.

18. The method of claim 16, wherein modifying the zero forcing equalization result signal comprises: dividing the zero forcing equalization result signal by a square root of the noise variance value.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Further features of the disclosure, its nature and various advantages will become apparent upon consideration of the following detailed description, taken in conjunction with the accompanying drawings, in which like reference characters refer to like parts throughout, and in which:

(2) FIG. 1 is a schematic representation of a wireless communication system including a receiver having a zero forcing equalizer with iterative parallel processing and noise de-whitening in accordance with some embodiments of the subject matter of this disclosure;

(3) FIG. 2 is a flow diagram of a method for utilizing the receiver of FIG. 1 to perform zero force equalization of a received signal, in accordance with embodiments of the subject matter of this disclosure;

(4) FIG. 3 is a flow diagram of a method for matrix scaling as part of the method of FIG. 2, in accordance with embodiments of the subject matter of this disclosure;

(5) FIG. 4 is a flow diagram of a method for matrix diagonalization as part of the method of FIG. 2, in accordance with embodiments of the subject matter of this disclosure; and

(6) FIG. 5 is a flow diagram of a method for generating inputs for downstream log-likelihood ratio decoding as part of the method of FIG. 2, in accordance with embodiments of the subject matter of this disclosure.

DETAILED DESCRIPTION

(7) In view of the inefficiency of conventional zero forcing equalization in wireless receiver systems, in accordance with implementations described herein a receiver having a zero forcing equalizer with iterative parallel processing and mitigation of noise de-whitening is provided. Iterative parallel processing improves the speed (or decreases the latency) at which zero forcing equalization is performed. Mitigation of noise de-whitening minimizes or avoids the degradation, which results from the noise de-whitening characteristic of conventional zero forcing equalizers, in the accuracy of bit value estimation performed by downstream LLR computation circuitry. Mitigation of noise de-whitening improves the quality of the signal from which bits are extracted so that a signal of improved fidelity is available for subsequent operations. This differs from, and requires less processing time than, previous techniques which rely upon forward error correction to correct bit errors, including bit errors resulting from de-whitening.

(8) Specifically, embodiments described herein provide a receiver having a zero forcing equalizer that improves processing efficiency by computing values of certain matrix entries based solely upon their respective row and column positions, and by executing iterative processing to compute values of certain other matrix entries by reusing results of prior computations (e.g., for matrix diagonalization) instead of repeating computations for each entry of a matrix as performed by conventional zero forcing equalizers.

(9) Additionally, by taking advantage of the independence of matrix columns, the zero forcing equalization algorithm of the embodiments described herein is configured to perform matrix diagonalization on a column-by-column basis, thereby enabling matrix diagonalization to be performed in parallel for each column of a matrix. By computing values of certain matrix entries based solely upon their row and column positions, reusing results of prior computations for other matrix entries, and utilizing parallel processing to perform matrix diagonalization, the zero forcing equalizer of embodiments described herein significantly increase the speed at which zero forcing equalization may be completed. The benefits of such a speed increase are compounded when employed in as advanced wireless receivers, for example Wi-Fi 6-compliant systems, which utilize multiple antennas and corresponding multiple receiver channels in each device.

(10) Further, embodiments described herein compute noise variance values on a per-stream basis based on a respective row of a matrix that is derived from a channel matrix, and use those noise variance values as the basis to scale the outputs (e.g., matrix values and gain values) of the zero forcing equalizer before downstream LLR computation. Scaling based on noise variance in this manner helps bring noise variance values to unity for every bit present in a received multi-stream symbol, which, in turn, combats the de-whitening of noise that is characteristic of conventional wireless receiver systems. Scaling based on noise variance decreases the instances of inaccurate bit value estimations in downstream LLR computation and thereby significantly decreases the bit error rates (BER) and/or packet error rates (PER) relative to the BER and/or PER exhibited in conventional wireless receiver systems.

(11) In general, a white noise signal (or vector) is a noise signal consisting of elements that are uncorrelated with one another and that have the same noise variance value. As used herein, de-whitening a white noise signal (or vector) means modifying the white noise signal to cause at least some of its elements not to have the same noise variance value and/or to introduce correlation between at least some of its elements. As used herein, mitigating de-whitening of a signal (or vector) means modifying the signal to cause at least some of its elements to have the same noise variance value and/or to reduce or eliminate correlation between at least some of its elements.

(12) FIG. 1 is a schematic illustration of a wireless communication system 100 including a transmitter/receiver having zero forcing equalizer 130 with iterative parallel processing and noise de-whitening in accordance with some embodiments of the subject matter of this disclosure. System 100 includes transmitter/receiver circuitry 102, coupled to one or more transmitting/receiving antennas 104, and one or more wireless devices 106 having one or more antennas 108. Transmitter/receiver circuitry 102 is generally configured to transmit wireless signals to the one or more wireless devices 106 via communication paths including antennas 104 and 108, and to receive wireless signals from the one or more wireless devices 106 via communication paths including antennas 108 and 104. In some aspects system 100 is implemented as a system-on-chip (SoC) that is compliant with the Wi-Fi 6 wireless communication standard, which is also referred to as the IEEE 802.11ax wireless communication standard. In this regard, transmitter/receiver circuitry 102, in some aspects, utilize the multiple antennas 104 for spatial stream signal transmission and reception to facilitate full multi-user multiple-input and multiple-output (MU-MIMO) and orthogonal frequency-division multiple access (OFDMA) uplink and downlink capability.

(13) Transmitter/receiver circuitry 102 includes RF/baseband analog/digital converter 110, baseband transmitter processor circuitry 112, baseband receiver processor circuitry 114, media access control (MAC) circuitry 116, local interface(s) 118, and memory 120, which are communicatively coupled to one another via control/data bus(es) 122. Although certain components of transmitter/receiver circuitry 102 are depicted as separate components in FIG. 1, in other aspects, various components in transmitter/receiver circuitry 102 may be integrated into a single component. For instance, baseband transmitter processor circuitry 112 and baseband receiver processor circuitry 114 may be implemented as a single processor.

(14) RF/baseband analog/digital converter 110 serves as an RF front end for transmitter/receiver circuitry 102, performing functions such as filtering, amplification, downconversion of received RF signals into baseband signals for processing, upconversion of baseband signals to RF signals for wireless transmission, digitization of analog signals, and the like. Memory 120 is used for buffering transmitted and received data, storing instructions for execution by one or more of the other components of transmitter receiver circuitry 102, such as baseband transmitter processor circuitry 112, baseband receiver processor circuitry 114, and/or the like. MAC 116 provides flow control and/or multiplexing for the transmission medium (e.g., including antennas 104), in an implementation. Local interface(s) 118 may be any type of local interface, such as a 2-wire serial interface, a serial peripheral interface (SPI), a general-purpose input/output (GPIO) interface, a peripheral component interconnect express (PCIe) 3.0 interface, a modular chip interconnect, and/or the like. The one or more local interfaces 118 enable transmitter/receiver circuitry 102 to communicate control and/or data (e.g., wirelessly received data and/or data to be wirelessly transmitted) with circuitry external to transmitter/receiver circuitry 102.

(15) In one example, transmitter/receiver circuitry 102 facilitates wireless communication based on coded bits being mapped to constellation symbols which in turn get mapped to multi-stream symbols. In such an example, on the transmitting side, baseband transmitter processor circuitry 112 includes forward error correction (FEC) circuitry 124, which performs forward error correction encoding upon data to be transmitted, symbol mapper 126, which maps coded bits to constellation symbols according to a modulation scheme such as quadrature amplitude modulation (QAM) or the like, and multi-stream mapper 128, which maps the constellation symbols to multi-stream symbols to be wirelessly transmitted via antennas 104, respectively.

(16) In multi-stream communication, if x is the multi-stream transmitted symbol, then the received baseband multi-stream symbol y can be written according to equation (1) below, where N.sub.r represents the number of receive antennas, N.sub.ss represents the number of spatial streams, y is a complex-valued received vector of dimension N.sub.r1, H is a complex-valued N.sub.rN.sub.ss channel seen by baseband receiver processor circuitry 114, with its (i,j).sup.th element representing the channel gain for j.sup.th stream seen on i.sup.th receiving antenna 104, w is complex valued noise-vector of dimension N.sub.r1, and x is a N.sub.ss1 complex-valued vector transmitted by one of wireless device(s) 108.
y=Hx+w(1)

(17) On the receiving side, baseband receiver processor circuitry 114 includes zero forcing equalizer (ZFE) 130, which performs zero forcing equalization on baseband signal vectors derived from signals wirelessly received from wireless device(s) 108 via communication paths including antennas 108 and 104. In general, zero forcing equalization may be used, for example, to bring down intersymbol interference and/or to recover multiple spatial streams. Below is a brief description of the features and functionality of ZFE 130. In some implementations, ZFE 130 includes multiple instances of ZFE control circuitry 131 and/or noise de-whitening mitigation circuitry 132, to facilitate iterative parallel processing and noise de-whitening, as illustrated in the figures and as described elsewhere herein. Additional details regarding the features and functionality of ZFE 130 are provided below in connection with FIGS. 2 through 5.

(18) ZFE 130 receives baseband multi-stream symbol (or vector) y at its input port and using ZFE control circuitry 131 and noise de-whitening mitigation circuitry 132, generates an N.sub.ss1 output vector y (which represents a result of zero forcing equalization being applied to received baseband multi-stream symbol y) and gain values g.sub.i, for 1iN.sub.ss (which represent respective gains for the i.sup.th received symbols). ZFE 130 communicates, via its output port, output vector y and gain values g.sub.i, for 1iN.sub.ss, downstream to log-likelihood ratio (LLR) computation circuitry 133. LLR computation circuitry 133 uses output vector y and gain values g.sub.i to compute log-likelihood ratios for each bit present in the received multi-stream symbol output vector y. In one example, LLR computation circuitry 133 scales up a constellation that was used during transmission of the multi-stream transmitted symbol x by g.sub.i.sup.2, and then computes the LLR for each bit of multi-stream symbol output vector y by taking the difference of its square distance from the nearest scaled up constellation symbol for which the bit is 1 and nearest scaled up constellation symbol for which this bit is 0. The output of LLR computation circuitry 133 for a given bit, in some aspects, may take the form of a ratio of a logarithm of the probability of the bit being a binary zero to logarithm of the probability of the bit being a binary one. LLR computation circuitry 133 passes LLRs for each bit of the received multi-stream symbol output vector y to decoder 134, which decodes the bits into their unencoded form for downstream processing, transmission, storage, or other use.

(19) Having described wireless communication system 100, reference is now made to FIG. 2, which is a flow diagram of a method 200 for utilizing the ZFE 130 of system 100 to perform zero force equalization of a received signal, in accordance with embodiments of the subject matter of this disclosure. At 202, ZFE 130 receives, from RF/Baseband Analog/Digital Converter 110 over bus 122, a baseband multi-stream symbol, which is a complex-valued vector y of dimension N.sub.r1, that was received by wireless device(s) 108 via one of antennas 104.

(20) Channel properties of the wireless link or path that includes the antenna 104 that received the vector y are described in a channel matrix H. The channel matrix H may be determined in any number of ways, such as by using channel estimation techniques. At 204, ZFE control circuitry 131 performs QR decomposition upon the channel matrix H to determine its Q component and its R component (sometimes referred to herein as Q matrix and R matrix, respectively), with the Q component being orthonormal and the R component being an N.sub.ssN.sub.ss upper triangular matrix.

(21) At 206, ZFE control circuitry 131 determines the conjugate transpose (Q.sup.H) of the Q component that was determined at 204 for channel matrix H. At 208, ZFE control circuitry 131 multiplies the conjugate transpose (Q.sup.H) determined at 206 by the vector y received at 202 and extracts the first N.sub.ss rows of the resulting product to generate intermediate vector y of dimension N.sub.ss1. Intermediate vector y is governed by equation (2) below, where y represents a complex-valued vector of dimension N.sub.ss1, component R represents the N.sub.ssN.sub.ss upper triangular matrix obtained from QR decomposition of channel matrix H at 204, and w represents an N.sub.ss1 complex-valued noise vector which is also governed by equation (3) below.
y=R.Math.x+w(2)
w=Q.sup.Hw(3)
As an example, if N.sub.ss=8, then the R component of channel matrix H assumes the structure shown in equation (4) below, with real values denoted by lowercase letters and complex values denoted by capital letters.

(22) $\begin{array}{cc}R=\left[\begin{array}{cccccccc}{r}_{11}& R_{12}& R_{13}& R_{14}& R_{15}& R_{16}& R_{17}& R_{18}\\ 0& r_{22}& R_{23}& R_{24}& R_{25}& R_{26}& R_{27}& R_{28}\\ 0& 0& r_{33}& R_{34}& R_{35}& R_{36}& R_{37}& R_{38}\\ 0& 0& 0& r_{44}& R_{45}& R_{46}& R_{47}& R_{48}\\ 0& 0& 0& 0& r_{55}& R_{56}& R_{57}& R_{58}\\ 0& 0& 0& 0& 0& r_{66}& R_{67}& R_{68}\\ 0& 0& 0& 0& 0& 0& r_{77}& R_{78}\\ 0& 0& 0& 0& 0& 0& 0& r_{88}\end{array}\right]& \left(4\right)\end{array}$

(23) At 210, ZFE control circuitry 131 scales the R component determined at 204 to generate matrix R.sub.D, and at 212, ZFE control circuitry 131 computes a matrix R.sub.inv that diagonalizes the matrix R using matrix R.sub.D generated at 210. Details regarding an example method for scaling the R component at 210 are provided below in the context of FIG. 3, and additional details regarding an example method for using matrix R.sub.D to generate matrix R.sub.inv at 212 are provided below in the context of FIG. 4. In general, as described below, scaling the R component to generate matrix R.sub.D in the manner described herein in connection with 210 renders the columns of R.sub.D independent from one another and enables ZFE control circuitry 131 to perform parallel processing and it further enables implementation of an iterative algorithm that significantly increases the rate at which ZFE control circuitry 131 performs zero forcing equalization.

(24) At 214, ZFE control circuitry 131 computes noise variance values (NV.sub.i) for each stream i (for 1iN.sub.ss) based on the matrix R.sub.INV generated at 212. In particular, the noise variance NVi for the i.sup.th stream is computed based on equation (5) below.

(25) $\begin{array}{cc}{\mathrm{NV}}_i=\underset{j=1}{\overset{N_{\mathrm{ss}}}{.Math.}}{.Math.R_{\mathrm{inv}\left(i,j\right)}.Math.}^2& \left(5\right)\end{array}$

(26) At 216, based on the noise variance values (NV.sub.i) computed at 214 and the intermediate vector y generated at 208, ZFE control circuitry 131, in conjunction with noise de-whitening mitigation circuitry 132, generates N.sub.ss1 output vector y (which represents a result of zero forcing equalization being applied to received baseband multi-stream symbol y) and gain values g.sub.i, for 1iN.sub.ss (which represent respective gains for the i.sup.th received symbols), which are passed downstream as inputs to LLR computation circuitry 133. Additional details regarding an example method for generating inputs for downstream LLR processing or decoding at 216 are provided below in the context of FIG. 5.

(27) FIG. 3 is a flow diagram showing additional details of an example method 210 for performing matrix scaling as part of the method 200 of FIG. 2, in accordance with embodiments of the subject matter of this disclosure. At 302, ZFE control circuitry 131 initializes a column index i to a value of one. At 304, ZFE control circuitry 131 scales non-zero non-diagonal entries of column i of matrix R with the inverse of the diagonal entry of that column. At 306, ZFE control circuitry 131 determines whether matrix R includes any additional column that requires matrix scaling. At 308, if matrix R includes an additional column that requires matrix scaling (Yes at 306), ZFE control circuitry 131 increments the column index i by 1 and repeats the method of 304 to scale the non-diagonal entries of that column of matrix R in the manner described above. At 310, if matrix R includes no additional column that requires matrix scaling (No at 306), ZFE control circuitry 131 multiplies the non-diagonal entries of matrix R as modified at 304 by 1. At 312, ZFE control circuitry 131 sets the diagonal entries of matrix R as modified at 304 and 310 equal to 1. After the steps of method 210 are executed as described above, generation of matrix R.sub.D, which is a square upper triangular matrix of dimension N.sub.ssN.sub.ss, is complete. The values of the (k,i).sup.th entries of R.sub.D, which are denoted by .sub.ki, as computed via method 210, are given by equation (6) below.

(28) $\begin{array}{cc}{}_{\mathrm{ki}}=\{\begin{array}{cc}1& ki\\ 0& k>i\\ -R_{\mathrm{ki}}/r_{\mathrm{ii}}& k<i\end{array}& \left(6\right)\end{array}$

(29) FIG. 4 is a flow diagram showing additional details of an example method 212 for determining based on R.sub.D a matrix R.sub.inv that diagonalizes matrix R, as part of the method 200 of FIG. 2, in accordance with embodiments of the subject matter of this disclosure. In various embodiments, the computation of each column of R.sub.inv is independent. Put differently, computation of elements of each column of R.sub.inv does not depend on the elements of any other column of R.sub.inv. Performing computations in parallel for each column of matrix R.sub.inv, for instance by implementing separate parallel circuitry (e.g., multiple instances of ZFE control circuitry 131) for each column, processing speed and throughput of ZFE 130 are significantly increased over conventional zero forcing equalizers.

(30) At 402, a column index i for the column being processed (e.g., by retrieving a column index i from memory 120), is determined, and at 404 ZFE control circuitry 131 initializes a row index k to equal N.sub.ss.

(31) At 406, ZFE control circuitry 131 compares the row index k to the column index i. If the row index k is greater than the column index i (k>i at 406), then at 408 ZFE control circuitry 131 sets the (k,i).sup.th value of matrix R.sub.inv (R.sub.inv(k,i)) equal to zero. At 410, ZFE control circuitry 131 decrements the row index k by 1 and passes control back to 406 to compare the decremented row index with the column index i in the manner described above.

(32) If the row index k is equal to the column index i (k=i at 406), then at 412 ZFE control circuitry 131 sets the (k,i).sup.th value of matrix R.sub.inv (R.sub.inv(k,i)), which is a diagonal entry of matrix R.sub.inv, equal to one. At 414, ZFE control circuitry 131 determines whether the column index i equals 1, which would indicate that row index k also equals 1 and thus that processing of the corresponding column of matrix R.sub.inv is completed. If the column index i equals 1 (Yes at 414), then processing of column i of matrix R.sub.inv is complete and method 212 terminates. If the column index i does not equal 1 (No at 414), then at 410 ZFE control circuitry 131 decrements the row index k by 1 and compares the newly decremented row index with the column index i in the manner described above.

(33) If the row index k is less than the column index i (k<i at 406), then at 416 ZFE control circuitry 131 determines the (k,i).sup.th entry of R.sub.inv by using an iterative algorithm given by equation (7) below, with .sub.ki represents the (k,i).sup.th entries of R.sub.D as computed via method 210.

(34) $\begin{array}{cc}{R}_{\mathrm{inv}\left(k,i\right)}=\underset{j=k+1}{\overset{i}{.Math.}}{}_{\mathrm{kj}}{R}_{\mathrm{inv}\left(j,i\right)}& \left(7\right)\end{array}$
As illustrated by equation (7), the (k,i).sup.th element of matrix R.sub.inv is computed by reusing elements R.sub.inv(k,i), for k<ki, that were previously computed during prior iterations of 416 for other rows of column i. Reusing previously computed elements of R.sub.inv in this manner significantly reduces the complexity in computing R.sub.inv and reduces the processing latency of ZFE control circuitry 131.

(35) At 418, ZFE control circuitry 131 determines whether the row index k is equal to 1, which would indicate that processing of column i of matrix R.sub.inv is completed. If the row index k equals 1 (Yes at 418), then processing of column i of matrix R.sub.inv is complete and method 212 terminates. If the row index k does not equal 1 (No at 418), then ZFE control circuitry 131 decrements the row index k by 1 at 410 and, at 406, compares the newly decremented row index with the column index i in the manner described above.

(36) FIG. 5 is a flow diagram showing additional details of an example method 216 for generating the N.sub.ss1 output vector y (which represents a result of zero forcing equalization being applied to received baseband multi-stream symbol y) and gain values g.sub.i, for 1iN.sub.ss (which represent respective gains for the i.sup.th received symbols), in a manner that mitigates noise de-whitening, as part of the method 200 of FIG. 2, in accordance with embodiments of the subject matter of this disclosure. The generated output vector y and gain values g.sub.i are be passed downstream as inputs to log-likelihood ratio (LLR) computation circuitry 133 for downstream log-likelihood ratio decoding.

(37) At 502, ZFE control circuitry 131 initializes index i to equal 1. At 504, noise de-whitening mitigation circuitry 132 computes the i.sup.th element of N.sub.ss1 output vector y (denoted by y.sub.i) according to equation (8) below.

(38) $\begin{array}{cc}{y}_i^{}=\frac{{\left(R_{\mathrm{inv}}{y}^{}\right)}_i}{\sqrt{{\mathrm{NV}}_i}}& \left(8\right)\end{array}$

(39) At 506, noise de-whitening mitigation circuitry 132 computes the i.sup.th gain value (denoted by g.sub.i) according to equation (9) below.

(40) $\begin{array}{cc}{g}_i=\frac{r_{\mathrm{ii}}}{\sqrt{{\mathrm{NV}}_i}}& \left(9\right)\end{array}$
Scaling the i.sup.th element of output vector (y.sub.i) and the i.sup.th gain value (g.sub.i) based on the square root of the i.sup.th noise variance value computed at 214, helps bring the noise variance to unity for every bit present in the equalized received multi-stream symbol y. This combats or mitigates de-whitening of noise (e.g., noise vector w described above in connection with equation (2)) and thereby significantly improves the performance of LLR computation (e.g., improves the accuracy of LLR estimates of bit values) by LLR computation circuitry 133. Improved LLR computation performance yields improved LLR estimates, which facilitates improvement of (e.g., a decrease in) the bit error rate (BER) and/or packet error rate (PER) performance of decoder 134.

(41) At 508, noise de-whitening mitigation circuitry 132 determines whether the index i is equal to N.sub.ss, which would indicate that generation of N.sub.ss1 output vector y and the corresponding gain values g.sub.i (for 1iN.sub.ss) is complete. If the index i is equal to N.sub.ss (Yes at 508), then zero forcing equalization of received baseband multi-stream vector y is complete and method 216 terminates. If the index i is not equal to N.sub.ss (No at 508), then at 510 noise de-whitening mitigation circuitry 132 increments the index i by 1 and repeats the methods of 504 through 508 to generate the next i.sup.th instance of y and gain value g in the manner described above.

(42) Various embodiments discussed in conjunction with FIGS. 1-5 are performed by control circuitry or various electronic components of one or more electronic circuits, such as but not limited to an integrated circuit, application-specific integrated circuit (ASIC), Field Programmable Gate Array (FPGA), digital signal processors, and/or other like circuitry. In addition, or alternatively, various embodiments and components disclosed herein are configured to be at least partially operated and/or implemented by processor-executable instructions, for example firmware instructions, that are stored on one or more transitory or non-transitory processor-readable media in memory 120.

(43) While various embodiments of the present disclosure have been shown and described herein, such embodiments are provided by way of example only. Numerous variations, changes, and substitutions relating to embodiments described herein are applicable without departing from the disclosure. It is noted that various alternatives to the embodiments of the disclosure described herein are employed in practicing the disclosure. It is intended that the following claims define the scope of the disclosure and that methods and structures within the scope of these claims and their equivalents be covered thereby.

(44) While operations are depicted in the drawings in a particular order, this is not to be construed as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed to achieve the desirable results.

(45) Other variations are within the scope of the following claims.