High-speed full-duplex transceiver and method thereof

Abstract

A transceiver includes a first digital-to-analog converter (DAC) configured to receive a first digital code and output a first current to a first node; a second DAC configured to receive a second digital code and output a second current to a second node; first and second shunt resistors configured to shunt the first node and second nodes to a DC (direct current) node; a first DC coupling resistor coupling the first node to a third node; a second DC coupling resistor coupling the second node to the third node; an AC (alternate current) coupling capacitor coupling the third node to a fourth node; a transimpedance amplifier configured to receive an input current from the fourth node and output an output current to a fifth node; an inductive load configured to shunt the fifth node to a DC node; and an analog-to-digital conversion unit configured to receive a voltage at the fifth node and output a third digital code.

Claims

1. A transceiver comprising: a first digital-to-analog converter (DAC) configured to receive a first digital code and output a first current to a first node, wherein the first node is a media-dependent interface for the transceiver to interface with a communication media; a second DAC configured to receive a second digital code and output a second current to a second node, wherein the second digital code is an inversion of the first digital code; a first shunt resistor configured to shunt the first node to a first DC (direct current) node; a second shunt resistor configured to shunt the second node to the first DC node; a first DC coupling resistor configured to couple the first node to a third node; a second DC coupling resistor configured to couple the second node to the third node; an AC (alternate current) coupling capacitor configured to couple the third node to a fourth node; a transimpedance amplifier configured to receive an input current from the fourth node and output an output current to a fifth node; an inductive load configured to shunt the fifth node to a second DC node; and an analog-to-digital conversion circuit configured to receive a voltage at the fifth node and output a third digital code.

2. The transceiver of claim 1 further includes a shunt capacitor configured to shunt the second node to the second DC node.

3. The transceiver of claim 1, wherein the inductive load is an active inductor.

4. The transceiver of claim 3, wherein the inductive load is adjustable and adjusted in accordance with a dispersion of the communication media.

5. The transceiver of claim 1, wherein the inductive load comprises a serial connection of a passive inductor and a resistor.

6. The transceiver of claim 1, wherein the transimpedance amplifier comprises a common-gate amplifier.

7. The transceiver of claim 6, wherein the transimpedance amplifier further includes a common-source amplifier configured to provide a gain boosting for the common-gate amplifier.

8. The transceiver of claim 1, wherein the analog-to-digital conversion circuit includes a pre-amplifier in an analog domain.

9. The transceiver of claim 8, wherein the analog-to-digital conversion circuit includes a pre-filter in the analog domain.

10. The transceiver of claim 9, wherein the analog-to-digital conversion circuit includes a post processing filter in a digital domain.

11. A method comprising the following steps: outputting a first current to a first node in accordance with a first digital code, wherein the first node is shunt to a first DC (direct current) node via a first shunt resistor; outputting a second current to a second node in accordance with a second digital code, wherein the second digital code is an inversion of the first digital code, and the second node is shunt to the first DC node via a second shunt resistor; coupling the first node to a third node using a first DC coupling resistor; coupling the second node to the third node using a second DC coupling resistor; coupling the third node to a fourth node using an AC (alternate current) coupling capacitor; outputting an output current to a fifth node using a transimpedance amplifier in accordance with an input current received from the fourth node; shunting the fifth node to a second DC node with an inductive load; outputting a third digital code in accordance with a voltage at the fifth node; and interfacing with a communication media via the first node.

12. The method of claim 11, wherein the second node is shunt to the second DC node via a shunt capacitor.

13. The method of claim 11, wherein the inductive load is an active inductor.

14. The method of claim 13, wherein the inductive load is adjustable and adjusted in accordance with a dispersion of the communication media.

15. The method of claim 11, wherein the inductive load comprises a serial connection of a passive inductor and a resistor.

16. The method of claim 11, wherein the transimpedance amplifier comprises a common-gate amplifier.

17. The method of claim 16, wherein the transimpedance amplifier further includes a common-source amplifier configured to provide a gain boosting for the common-gate amplifier.

18. The method of claim 11, wherein the step of outputting the third digital code includes using a pre-amplifier in an analog domain.

19. The method of claim 18, wherein the step of outputting the third digital code includes using a pre-filter in an the domain.

20. The method of claim 19, wherein step of outputting the third digital code includes a post processing filter in a digital domain.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 shows a schematic diagram of a transceiver in accordance with an embodiment of the present disclosure.

(2) FIG. 2 shows a schematic diagram of a two-bit digital-to-analog converter.

(3) FIG. 3 shows a schematic diagram of a transimpedance amplifier.

(4) FIG. 4 shows a flow diagram of a method in accordance with an embodiment of the present disclosure.

DETAILED DESCRIPTION OF THIS INVENTION

(5) The present invention relates to full-duplex transceiver. While the specification describes several example embodiments of the invention considered favorable modes of practicing the invention, it should be understood that the invention can be implemented in many ways and is not limited to the particular examples described below or to the particular manner in which any features of such examples are implemented. In other instances, well-known details are not shown or described to avoid obscuring aspects of the invention.

(6) Persons of ordinary skill in the art understand terms and basic concepts related to microelectronics that are used in this disclosure, such as (circuit) node, ground (node), virtual ground, signal, voltage, current, Ohm's Law, bias, AC (alternate current) coupling, DC (direct current) coupling, capacitor, capacitance, resistor, inductor, transmission line, CMOS (complementary metal oxide semiconductor), PMOS (P-channel metal oxide semiconductor) transistor, NMOS (N-channel metal oxide semiconductor) transistor, frequency, shunt, switch, cascode, impedance, common-source amplifier, common-gate amplifier, and transimpedance amplifier. Terms and basic concepts like these are apparent to those of ordinary skill in the art and thus will not be explained in detail here. Those of ordinary skill in the art can also recognize symbols of PMOS transistor and NMOS transistor, and identify the source, the gate, and the drain terminals thereof.

(7) A logical signal is a signal of two states: a first logical state (or a high state), and a second logical state (or a low state). When a logical signal is said to be high (low), it means it is in the high (low) state, and it occurs when the logical signal is sufficiently above (below) a threshold level that is called a trip point. Every logical signal has a trip point, and two logical signals may not necessarily have the same trip point.

(8) The present disclosure is presented in an engineering sense. For instance, X is equal to Y means: a difference between X and Y is smaller than a specified engineering tolerance. X is substantially smaller than Y means: a ratio between X and Y is smaller than a specified engineering tolerance. For instance, in an embodiment, X is said to be substantially smaller than Y when a ratio between X and Y is smaller than three percent.

(9) As depicted in FIG. 1, a transceiver 100 in accordance with an embodiment of the present disclosure comprises: a first digital-to-analog converter DAC 111 configured to receive a first digital code D.sub.1 and output a first current I.sub.1 to a first node 101; a first shunt resistor R.sub.S1 configured to shunt the first node 101 (of a first voltage denoted by V.sub.1) to a first power supply node denoted by V.sub.DD1; a second digital-to-analog converter DAC 112 configured to receive a second digital code D.sub.2 and output a second current I.sub.2 to a second node 102 (of a second voltage denoted by V.sub.2); a second shunt resistor R.sub.S2 configured to shunt the second node 102 to V.sub.DD1; a first DC (direct current) coupling resistor R.sub.C1 configured to couple the first node 101 to a third node 103 (of a third voltage denoted by V.sub.3); a second DC coupling resistor R.sub.C2 configured to couple the second node 102 and the third node 103; an AC (alternate current) coupling capacitor C.sub.C configured to couple the third node 103 to a fourth node 104 (of a fourth voltage denoted by V.sub.4); a TIA (transimpedance amplifier) 114 configured to receive an input current I.sub.4 from the fourth node 104 and output an output current I.sub.5 to a fifth node 105 (of a fifth voltage denoted by V.sub.5); an inductive load 120 configured to shunt the fifth node 105 to a second power supply node denoted by V.sub.DD2; an analog-to-digital conversion unit 115 configured to receive a fifth voltage V.sub.5 at the fifth node 105 and output a third digital code D.sub.3. The first node 101 is a media dependent interface for transceiver 100 to interface with a transmission line TL. The first digital code D.sub.1 carries information to be sent to a remote link partner (which is also a transceiver) through the transmission line TL, while the third digital code D.sub.3 represents information sent from the remote link partner through the transmission line TL and eventually decoded by transceiver 100. The second digital code D.sub.2 is an inversion of the first digital code D.sub.1 and is used for cancelling an echo resulting from the first digital code D.sub.1. A principle of the cancellation is explained below.

(10) V.sub.1 can be decomposed into three components and mathematically represented by the following equation:
V.sub.1=V.sub.B1+v.sub.1t+v.sub.1r(1)

(11) Here, V.sub.B1 is a DC component of V.sub.1; v.sub.1t is an AC component pertaining to information represented by the first digital code D.sub.1 and to be sent to the remote link partner; and V.sub.1r is an AC component pertaining to the information received from the remote link partner and to be eventually resolved into the third digital code D.sub.3.

(12) V.sub.2 can be decomposed into two components and mathematically represented by the following equation:
V.sub.2=V.sub.B2+v.sub.ec(2)

(13) Here, V.sub.B2 is a DC component of V.sub.2; v.sub.ec is an AC component pertaining to information represented by the second digital code D.sub.2.

(14) A transimpedance amplifier, such as TIA 114, is a device having a low input impedance and a high output impedance, wherein an input current received from a preceding circuit is substantially equal to an output current output to a succeeding circuit, as far as an AC component is concerned. In an embodiment, TIA 114 of FIG. 1 has an input impedance substantially lower than an impedance of the preceding circuit (denoted by Z.sub.p) and an output impedance substantially higher than an impedance of the succeeding circuit (denoted by Z.sub.s). Note that it is an engineering issue, instead of a rigorous theoretical issue, regarding how much lower (higher) can be said to be substantially lower (higher). In this disclosure, by way of example but not limitation, the input (output) impedance of TIA 114 is thirty-times lower (higher) than Z.sub.p (Z.sub.s) and said to be substantially lower (higher) than Z.sub.p (Z.sub.s) and thus negligible. Due to the low input impedance of TIA 114, the fourth node 104 is considered a virtual ground and V.sub.4 is substantially stationary, i.e.
V.sub.4V.sub.B4(3)

(15) Here, V.sub.B4 is an DC component of V.sub.4, while an AC component of V.sub.4 is omitted.

(16) C.sub.C is an AC coupling capacitor of a substantially low impedance that can be deemed a short circuit at a frequency of interest in the communication link between transceiver 100 and the remote link partner. Therefore, the third node 103 can also be considered a virtual ground and V.sub.3 is substantially stationary, i.e.
V.sub.3V.sub.B3(4)

(17) Here, V.sub.B3 is a DC component of V.sub.3, while an AC component of V.sub.3 is omitted. By applying Kirchhoff's Voltage Law, we obtain

(18) $\begin{array}{cc}{V}_{B3}=\frac{V_{B1}{R}_{C2}+V_{B2}{R}_{C1}}{R_{C1}+R_{C2}}& \left(5\right)\end{array}$

(19) By applying the Ohm's law and Kirchhoff s Current Law on the AC components of V.sub.1 and V.sub.2, along with that third node 103 is a virtual ground, we obtain

(20) $\begin{array}{cc}{I}_4=\frac{v_{1t}+v_{1r}}{R_{C1}}+\frac{V_{\mathrm{ec}}}{R_{C2}}& \left(6\right)\end{array}$

(21) The first current I.sub.1 can be expressed by the following equation
I.sub.1=I.sub.B1+D.sub.1I.sub.U1(7)

(22) Here, I.sub.B1 is a DC component of I.sub.1, and I.sub.U1 is a unit current of DAC 111.

(23) The second current I.sub.2 can be expressed by the following equation
I.sub.2=I.sub.B2+D.sub.2I.sub.U2(8)

(24) Here, I.sub.B2 is a DC component of I.sub.2, and I.sub.U2 is a unit current of DAC 112. As mentioned earlier, D.sub.2 is an inversion of D.sub.1, i.e.
D.sub.2=D.sub.1(9)

(25) Let an impedance looking into the transmission line TL be represented by Z.sub.0. By applying the Ohm's law on the AC component of I.sub.1 and factoring in all the load impedance seen by I.sub.1, yields the following:

(26) $\begin{array}{cc}{v}_{1t}=\frac{D_1{I}_{U1}}{\frac{1}{Z_0}+\frac{1}{R_{S1}}+\frac{1}{R_{C1}}}& \left(10\right)\end{array}$

(27) Similarly:

(28) $\begin{array}{cc}{v}_{\mathrm{ec}}=\frac{D_2{I}_{U2}}{\frac{1}{R_{S2}}+\frac{1}{R_{C2}}}& \left(11\right)\end{array}$

(29) Applying equations (9), (10), and (11) to equation (6) yields:

(30) $\begin{array}{cc}{I}_4=\frac{v_{1r}}{R_{C1}}+\frac{D_1{I}_{U1}}{R_{C1}.Math.\left(\frac{1}{Z_0}+\frac{1}{R_{S1}}+\frac{1}{R_{C1}}\right)}-\frac{D_1{I}_{U2}}{R_{C2}.Math.\left(\frac{1}{R_{S2}}+\frac{1}{R_{C2}}\right)}& \left(12\right)\end{array}$

(31) On the right hand side of equation (12), the first term

(32) $\frac{V_{1r}}{R_{C1}}$
is pertaining to the information sent from the remote link partner to transceiver 100, the second term

(33) $\frac{D_1{I}_{U1}}{R_{C1}.Math.\left(\frac{1}{Z_0}+\frac{1}{R_{S1}}+\frac{1}{R_{C1}}\right)}$
is an echo of DAC 111, while the third term

(34) $\frac{D_1{I}_{U2}}{R_{C2}.Math.\left(\frac{1}{R_{S2}}+\frac{1}{R_{C2}}\right)}$
is a correction from DAC 112. In an embodiment, I.sub.U2, R.sub.S2, and R.sub.C2 are chosen in accordance with I.sub.U1, R.sub.S1, Z.sub.0, and R.sub.C2 such that the following condition holds:

(35) $\begin{array}{cc}\frac{I_{U1}}{R_{C1}.Math.\left(\frac{1}{Z_0}+\frac{1}{R_{S1}}+\frac{1}{R_{C1}}\right)}=\frac{I_{U2}}{R_{C2}.Math.\left(\frac{1}{R_{S2}}+\frac{1}{R_{C2}}\right)}& \left(13\right)\end{array}$

(36) Then, the third term

(37) 0$\frac{D_1{I}_{U2}}{R_{C2}.Math.\left(\frac{1}{R_{S2}}+\frac{1}{R_{C2}}\right)}$
cancels me second term

(38) $\frac{D_1{I}_{U1}}{R_{C1}.Math.\left(\frac{1}{Z_0}+\frac{1}{R_{S1}}+\frac{1}{R_{C1}}\right)},$
resulting in:

(39) $\begin{array}{cc}{I}_4=\frac{v_{1r}}{R_{C1}}.& \left(14\right)\end{array}$

(40) In this case, I.sub.4 contains only the information sent from the remote link partner to transceiver 100, and the echo from DAC 111 is totally cancelled by the correction from DAC 112.

(41) I.sub.5 has the same AC value as I.sub.4, thanks to the transimpedance amplifier TIA 114. By applying the Ohm's law:

(42) $\begin{array}{cc}{V}_5=V_{B5}+\frac{v_{1r}}{R_{C1}}.Math.Z_s& \left(15\right)\end{array}$

(43) Here, V.sub.B5 is a DC component of V.sub.5. The inductive load 120 comprises: a PMOS transistor 121 placed between the fifth node 105 and a second power supply node denoted by V.sub.DD2, a shunt capacitor C.sub.g placed across the gate of PMOS transistor 121 and V.sub.DD2, and a feedback resistor R.sub.f placed between the gate and the drain of the PMOS transistor 121. The inductive load 120 is a circuit known as an active inductor. By neglecting a parasitic capacitance at the first node 101, the impedance Z.sub.s can be approximated by the following equation:

(44) $\begin{array}{cc}{Z}_s=\frac{1+{\mathrm{sR}}_f{C}_g}{g_m+{\mathrm{sC}}_g}& \left(16\right)\end{array}$

(45) Here, g.sub.m is a transconductance of PMOS transistor 121, and s is a Laplace transform variable. Applying equation (16) to equation (15) yields:

(46) $\begin{array}{cc}{V}_5=V_{B5}+\frac{v_{1r}}{R_{C1}}.Math.\frac{1+{\mathrm{sR}}_f{C}_g}{g_m+{\mathrm{sC}}_g}& \left(17\right)\end{array}$

(47) In an embodiment, g.sub.m is greater than 1/R.sub.f. At a low frequency where |sR.sub.fC.sub.g|<<1, V.sub.5 is approximately

(48) $V_{B5}+\frac{v_{1r}}{R_{C1}{g}_m}.$
At a high frequency where |sC.sub.g|>>g.sub.m, V.sub.5 is approximately

(49) $V_{B5}+\frac{v_{1r}.Math.R_f}{R_{C1}}.$
Since g.sub.m is greater than 1/R.sub.f, a higher frequency component of v.sub.1r will enjoy a higher gain than a lower frequency component; this can fulfill an equalization function that is needed. In an embodiment, one of R.sub.f and C.sub.g is adjustable and adjusted in accordance with a dispersion of the transmission line TL. For instance, when the transmission TL has higher insertion loss at a high frequency, R.sub.f is adjusted to be larger.

(50) By way of example but not limitation, transceiver 100 is fabricated using a 28 nm CMOS (complementary metal oxide semiconductor) process: a baud rate of the full-duplex communication between transceiver 100 and the remote link partner is 5.625 GHz; Z.sub.0 is 50-Ohm; V.sub.DD1 is 1.8V; R.sub.S1 is 60 Ohm; I.sub.B1 is 10 mA; I.sub.U1 is 20 mA/3; D.sub.1 represents a PAM-4 (4-level pulse-amplitude modulation) signal that has four possible values: {3, 1, 1, 3}; R.sub.S2 is 240 Ohm; I.sub.B2 is 2.5 mA; I.sub.U2 is 5 mA/3; R.sub.C1 is 300-Ohm; R.sub.C2 is 480 Ohm; C.sub.C is 10 pF; R.sub.f is 2 KOhm; C.sub.g is 100 fF; the width/length of PMOS transistor 121 are 20 m/30 nm; and V.sub.DD2 is 0.9V.

(51) A two-bit digital-to-analog converter 200 suitable for implementing DAC 111 is shown in FIG. 2. Here, the first digital code D.sub.1 is a two-bit code comprising a LSB (least significant bit) D.sub.1[0] and a MSB (most significant bit) D.sub.1[1]. Digital-to-analog converter 200 comprises a first current cell 210 and a second current cell 220 configured to output a first output current I.sub.1a and a second output current I.sub.1b in accordance with D.sub.1[0] and D.sub.1[1], respectively. The first current cell 210 comprises two NMOS transistors 211 and 212 configured in a cascode topology, wherein NMOS transistor 211 embodies a current source biased by a biasing voltage V.sub.B and NMOS transistor 212 embodies a switch used to either turn on or turn off the first current cell 210 in accordance with a control by D.sub.1[0]. The second current cell 220 comprises two NMOS transistors 221 and 222 configured in a cascode topology, wherein NMOS transistor 221 embodies a current source biased by the biasing voltage V.sub.B and NMOS transistor 222 embodies a switch used to either turn on or turn off the second current cell 220 in accordance with a control by D.sub.1[1]. Both D.sub.1[0] and D.sub.1[1] are logical signals. By way of example but not limitation: I.sub.1a is equal to 20 mA/3 (0 mA) when D.sub.1[0] is high (low); and I.sub.1b is equal to 40 mA/3 (0 mA) when D.sub.1[1] is high (low). An encoding scheme for D.sub.1 is shown in the table below:

(52) TABLE-US-00001 D.sub.1 3 1 1 3 D.sub.1[0] low high Low high D.sub.1[1] low low High high

(53) Here, high and low are pertaining to logical states; by way of example but not limitation, high and low states are of 0.9V and 0V, respectively. By applying the above encoding scheme, the resultant values for I.sub.1a, I.sub.1b, and I.sub.1 is obtained (which is a sum of I.sub.1a and I.sub.1b):

(54) TABLE-US-00002 D.sub.1 3 1 1 3 I.sub.1a 0 mA 20 mA/3 0 mA 20 mA/3 I.sub.1b 0 mA 0 mA 40 mA/3 40 mA/3 I.sub.1 0 mA 20 mA/3 40 mA/3 20 mA

(55) This way, equation (7) is satisfied with I.sub.B1=10 mA and I.sub.U1=10 mA/3.

(56) By way of example but not limitation, the width/length of NMOS transistor 211 are 30 m/90 nm; the width/length of NMOS transistor 212 are 30 m/90 nm; the width/length of NMOS transistor 221 are 60 m/90 nm; the width/length of NMOS transistor 222 are 60 m/90 nm; and V.sub.B is 600 mV.

(57) The same circuit topology of the two-bit digital-to-analog converter 200 can be used to embody DAC 112, but all transistor widths need to be reduced by a proper factor to reflect the difference between I.sub.1 and I.sub.2. Also, D.sub.1[0] and D.sub.1[1] are replaced by D.sub.2 [0] and D.sub.2 [1] with the following encoding scheme for D.sub.2:

(58) TABLE-US-00003 D.sub.2 3 1 1 3 D.sub.2 [0] low high low high D.sub.2[1] low low high high

(59) A transimpedance amplifier 300 that can be used to embody TIA 114 of FIG. 1 is shown in FIG. 3. Transimpedance amplifier 300 comprises: three NMOS transistors 301, 302, and 303, and a PMOS transistor 304. NMOS transistor 302 embodies a common-gate amplifier; NMOS transistor 301 embodies a current source configured to bias the common-gate amplifier in accordance with a biasing condition determined by a bias voltage V.sub.BN; NMOS transistor 303 embodies a common-source amplifier configured to provide a negative feedback from the source to the gate of NMOS transistor 302 to embody a gain boosting function for the common-gate amplifier; and PMOS transistor 304 embodies a load for the common-source amplifier with a load resistance controlled by another bias voltage V.sub.BP. The gain boosting provided by the common-source amplifier helps to reduce an input impedance of the common-gate amplifier at node 104. Transimpedance amplifier 300 is well known in the prior art and thus not explained in detail here.

(60) Now refer to FIG. 1. The first node 101 is a media-dependent interface that in practice usually has an appreciable parasitic capacitance. Capacitor C.sub.p1 inside dashed-box DB130 models a parasitic capacitance at the first node 101. The existence of capacitor C.sub.p1 introduces a pole at the first node 101 and alters the second term of the right-hand side of equation (12). This can lead to degradation of performance of echo cancellation. To mitigate the degradation, a shunt capacitor C.sub.p1 shown inside dashed-box DB140 is introduced at the second node 102, and equation (12) is modified as follows:

(61) $\begin{array}{cc}{I}_4=\frac{v_{1r}}{R_{C1}}+\frac{D_1{I}_{U1}}{R_{C1}.Math.\left(\frac{1}{Z_0}+\frac{1}{R_{S1}}+\frac{1}{R_{C1}}+{\mathrm{sC}}_{p1}\right)}-\frac{D_1{I}_{U2}}{R_{C2}.Math.\left(\frac{1}{R_{S2}}+\frac{1}{R_{C2}}+{\mathrm{sC}}_{p2}\right)}& \left(18\right)\end{array}$

(62) In an embodiment, C.sub.p1 is chosen in accordance with C.sub.p1 such that the following condition holds:

(63) $\begin{array}{cc}\frac{I_{U1}}{R_{C1}.Math.\left(\frac{1}{Z_0}+\frac{1}{R_{S1}}+\frac{1}{R_{C1}}+{\mathrm{sC}}_{p1}\right)}=\frac{I_{U2}}{R_{C2}.Math.\left(\frac{1}{R_{S2}}+\frac{1}{R_{C2}}+{\mathrm{sC}}_{p2}\right)}& \left(19\right)\end{array}$

(64) Then, the third term

(65) 0$\frac{D_1{I}_{U2}}{R_{C2}.Math.\left(\frac{1}{R_{S2}}+\frac{1}{R_{C2}}+{\mathrm{sC}}_{p2}\right)}$
cancels the second term

(66) $\frac{D_1{I}_{U1}}{R_{C1}.Math.\left(\frac{1}{Z_0}+\frac{1}{R_{S1}}+\frac{1}{R_{C1}}+{\mathrm{sC}}_{p1}\right)}$
despite the existence of C.sub.p1.

(67) In FIG. 1, ADC 115 converts V.sub.s into D.sub.3. An analog-to-digital conversion is a function that converts a signal in an analog domain (e.g. V.sub.5) to a signal in a digital domain (e.g. D.sub.3) and is well known in the prior art and thus not described in detail here. However, ADC 115 is a functional block that embodies analog-to-digital conversion function, but does not necessarily need to be a single analog-to-digital converter circuit. An analog-to-digital conversion function takes a signal in analog domain and converts it into a counterpart in digital domain. It might further include a pre-amplifier in the analog domain for receiver's gain control purpose. It might further include a pre-filter in the analog domain. It might further include a post-processing filter in the digital domain after the analog signal is converted to a digital counterpart. Pre-filter (such as continuous-time linear equalizer anti-alias filtering) and post processing filter (such as decision feedback equalizer) are often needed to make D.sub.3 accurately represent the information sent from the remote link partner. Since there are numerous possibilities, they are not exhaustively stated here.

(68) Transceiver 100 is a single-ended signaling embodiment. By combining two single-ended signaling embodiments, a differential signaling embodiment can be implemented.

(69) Although it is shown that both R.sub.S1 and R.sub.S2 connect to the same power supply node V.sub.DD1, this is merely an example but not a limitation. As well, power supplies nodes V.sub.DD1 and V.sub.DD2 are circuits nodes that have substantially fixed electrical potentials, and can be described as DC nodes, as the voltages thereof contain negligible AC components. Further, a ground node can also be described as a DC node.

(70) In an alternative embodiment not shown in figure, the inductive load 120 is replaced with a serial connection of a passive inductor and a resistor. A passive inductor may have better linearity than an active inductor, but it usually occupied more circuit area and is thus more expensive.

(71) There are no operational amplifiers in the signal paths of transceiver 100, and all the circuits can be comfortably implemented for baud rate of 5.625 GHz as shown in the example given earlier.

(72) As illustrated by a flow diagram shown in FIG. 4, a method in accordance with an embodiment of the present disclosure comprises the following steps: (step 410) outputting a first current to a first node in accordance with a first digital code, wherein the first node is shunt to a DC (direct current) node via a first shunt resistor; (step 420) outputting a second current to a second node in accordance with a second digital code, wherein the second digital code is an inversion of the first digital code, and the second node is shunt to a DC node via a second shunt resistor; (step 430) coupling the first node to a third node using a first DC coupling resistor; (step 440) coupling the second node to the third node using a second DC coupling resistor; (step 450) coupling the third node to a fourth node using an AC (alternate current) coupling capacitor; (step 460) outputting an output current to a fifth node using a transimpedance amplifier in accordance with an input current received from the fourth node; (step 470) shunting the fifth node to a DC node with an inductive load; (step 480) outputting a third digital code in accordance with a voltage at the fifth node; and (step 490) interfacing with a communication media via the first node.

(73) Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.