WRITING APPARATUS AND METHOD FOR COMPLEMENTARY RESISTIVE SWITCH

Abstract

A reconfigurable circuit comprising: a complementary resistive switch; a write circuit to configure the complementary resistive switch; a read circuit to get ON/OFF information of the complementary resistive switch; a register to store ON/OFF information of the complementary resistive switch.

Claims

1. A reconfigurable circuit comprising: a complementary resistive switch with three terminals; a write circuit to configure said complementary resistive switch; a read circuit to get ON/OFF information of said complementary resistive switch; and a register to store ON/OFF information of the said complementary resistive switch.

2. The reconfigurable circuit according to claim 1, wherein said complementary resistive switch includes two serially connected resistive switches and three terminals, wherein a first terminal of a first resistive switch is used as a first terminal of said complementary resistive switch, a first terminal of a second resistive switch is used as a second terminal of said complementary resistive switch, second terminals of said first and second resistive switches are connected with each other and used as a third terminal of said complementary resistive switch.

3. The reconfigurable circuit according to claim 1, wherein said write circuit provides set voltage, reset voltage, ground voltage and hi-Z to said complementary resistive switch.

4. The reconfigurable circuit according to claim 1, wherein said register stores ON/OFF information obtained by said read circuit.

5. The reconfigurable circuit according to claim 1, wherein said write circuit receives ON/OFF information stored in said register.

6. A write method for reconfigurable circuit comprising a complementary resistive switch which has three terminals, wherein a first terminal of a first resistive switch is used as a first terminal of said complementary resistive switch, a first terminal of a second resistive switch is used as a second terminal of said complementary resistive switch, second terminals of said first and second resistive switches are connected with each other and used as a third terminal of said complementary resistive switch; a write circuit to configure said complementary resistive switch; a read circuit to get ON/OFF information of said complementary resistive switch; a register to store ON/OFF information of the said complementary resistive switch, the method comprising: applying set voltage from said write circuit to said first and second terminals of said complementary resistive switch simultaneously; and applying ground voltage from said write circuit to said third terminal of said complementary resistive switch.

7. The write method according to claim 6, further comprising: obtaining ON/OFF information of said complementary resistive switch by said read circuit.

8. The write method according to claim 7, further comprising: storing ON/OFF information of said complementary resistive switch in said register.

9. The write method according to claim 8, further comprising: writing OFF-state resistive switch and ON-state resistive switch sequentially.

10. The write method according to claim 8, further comprising: writing OFF-state resistive switch using high set voltage and ON-state resistive switch using low set voltage.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0013] FIG. 1 is a schematic view illustrating an exemplary structure of the FPGA using the CNVRSs.

[0014] FIG. 2 shows the NVRS and its write circuit according to a first exemplary embodiment of the present invention.

[0015] FIG. 3 illustrates a two-step write method according to a first exemplary embodiment of the present invention.

[0016] FIG. 4 illustrates a three-step write method according to a first exemplary embodiment of the present invention.

[0017] FIG. 5 illustrates structure of writing apparatus according to a first exemplary embodiment of the present invention.

[0018] FIG. 6 shows flow chart of writing apparatus according to a first exemplary embodiment of the present invention.

DESCRIPTION OF EMBODIMENTS

[0019] Exemplary embodiment of the present invention will be next described with reference to the accompanying drawings.

First Exemplary Embodiment

[0020] FIG. 2 illustrates the structure of the NVRS and its write circuit. As shown in FIG. 2 (a), The NVRS includes: active electrode T1 made of, for example, copper (Cu); inert electrode T2 made of, for example, ruthenium (Ru); and solid-electrolyte IC sandwiched between active electrode T1 and inert electrode T2. FIG. 2 (b) shows the symbolic of the NVRS. If a positive voltage (Vset) applied between T1 and T2, resistance of the NVRS becomes low, called ON state. On the other hand, if a negative voltage (Vrst) applied between T1 and T2, resistance of the NVRS becomes high, called OFF state (FIG. 2 (c)). The ratio of the high resistance and the low resistance is larger than 10.sup.5, so that the NVRS can be directly used as a switch for data routing. FIG. 2 (d) shows the CNVRS and its write circuit. Three write drivers and a programming transistor Tr. are used to configure the two NVRS. FIG. 2 (e) shows the write driver includes a set voltage (Vset), a reset voltage (Vrst) and a ground voltage (GND). Each of the above voltage line is serially connected to a constant current transistor, a voltage selection transistor and an output control transistor. A reference voltage Vref is applied to the constant current transistor to control current for each power voltage line. A voltage selection signal is applied to the voltage selection transistor to select one of the power voltage lines as an output. A high-Z selection signal is applied to the output control transistor to enable output of the write driver.

[0021] In the CNVRS, two NVRSs have different set voltages due to process version, which results in write disturb problem. We define weak switch has low set/reset voltage, while strong switch has high set/reset voltage. FIG. 3 illustrates a conventional two-step CNVRS write method. In the first step, to set NVRS S1, Vset is applied to terminal T1, GND is applied to terminal T3, and terminal T2 is set to Hi-Z. In the second step, to set NVRS S2, Vset is applied to terminal T2, GND is applied to terminal T3, and terminal T1 is set as Hi-Z. Disturb voltage is applied to S1. Disturb problem of S1 may happen. Or the ON state of S1 is not stable in harsh environment.

[0022] FIG. 4 illustrates a novel three-step write method with weak NVRS detection scheme. In the first step, to detect weak NVRS, Vset is applied to terminals T1 and T2, simultaneously, GND is applied to terminal T3. If S1 has lower set voltage than S2, S1 is set to ON state firstly. Then, the voltage of the common terminal of S1 and S2 becomes almost Vset, the voltage difference of two terminals of S2 becomes almost 0 V. S2 is kept as OFF state. Weak NVRS can be detected by reading ON/OFF state of S1 and S2. The ON-state NVRS is the weak one, while the OFF-state NVRS is the strong one. In the second step, to set strong NVRS S2 with high set voltage, a high Vset is applied to T2, GND is applied to T3 and T1 is set to Hi-Z. S1 may be disturbed as OFF state due to high Vset. In the third step, to set weak NVRS S1 with low set voltage, a low Vset is applied to T1, GND is applied to T3 and T2 is set to Hi-Z. Disturb problem will not happen in S2 because disturb voltage is smaller than reset voltage of strong NVRS S2. It is expected that fail rate of NVRS at high temperature can be reduced by at least 70%.

[0023] FIG. 5 shows a novel writing apparatus for the three-step write method. The write apparatus consists of a CNVRS, a write circuit, a read circuit and a register. The write circuit shown in FIG. 2 (d) is used to apply Vset, GND and Hi-Z to the CNVRS. A read circuit obtains ON/OFF state of the two NVRSs in the CNVRS in the first step. The register stores the ON/OFF in the first step.

[0024] FIG. 6 illustrates flow chart of writing apparatus. At first, the write circuit is used to set two NVRSs in a CNVRS simultaneously, and the read circuit is used to get ON/OFF state information of the two NVRSs. Then, the ON/OFF state information is stored in the register. Finally, the write circuit is used again to write OFF-state switch with high Vset and ON-state switch with low Vset sequentially.

[0025] The reconfigurable circuits of the above exemplary embodiment may be used in, for example, mobile phone, IoT (Internet of Things) devices, and so on. A high reliable FPGA using the CNVRSs can be realized by the reconfigurable circuits described above.

[0026] It is apparent that the present invention is not limited to the above exemplary embodiments and examples, but may be modified and changed without departing from the scope and sprit of the invention.