POWER SWITCH SYSTEM

Abstract

A power-switch-system (PSS) having a low-side transistor (LSS) and a high-side transistor (HSS), which are switchable to be conductive or switched to be blocking in respectively alternating time-segments of a switching-period of the PSS. A source-terminal of the LSS is connected to a load-terminal, and a drain-terminal of the LSS is connected to a supply-voltage via a storage-inductor. A drain-terminal of the HSS is connected to the load-terminal, and a source-terminal of the HSS is connected to the supply-voltage via the storage-inductor. Provided is a PSS of this kind, the LSS having at least two transistor-segments. At least two of the transistor-segments have a different electrical resistance in the connection to the storage-inductor. The PSS provides that at least two of the transistor-segments are switched at a different point in time during a switching operation of the PSS to reduce unwanted voltage fluctuations, without markedly increasing switching losses.

Claims

1-7. (canceled)

8. A power switch system, comprising: a low-side transistor; and a high-side transistor, wherein the low-side transistor and the high-side transistor are configured so that they are switched to be conductive or switched to be blocking in respectively mutually alternating time segments of a switching period of the power switch system; wherein a source terminal of the low-side transistor is connected to a load terminal and a drain terminal of the low-side transistor is connected to a supply voltage via a storage inductor, wherein a drain terminal of the high-side transistor is connected to the load terminal, and a source terminal of high-side transistor is connected to the supply voltage via the storage inductor, wherein the low-side transistor includes at least two transistor segments, at least two of the transistor segments having a different electrical resistance in the connection to the storage inductor, and wherein the power switch system is configured so that at least two of the transistor segments are switched at a different point in time during a switching operation of the power switch system.

9. The power switch system of claim 8, wherein at least two of the transistor segments include differently sized area proportions of the low-side transistor.

10. The power switch system of claim 8, wherein the power switch system is configured so that each one of the transistor segments is assigned to its own gate segment of the gate terminal of the low-side transistor, the associated transistor segment being switched by switching one of the gate segments.

11. The power switch system of claim 8, wherein the power switch system is configured so that the time interval during a switching operation between switching two consecutively connected transistor segments is less than 100 ns.

12. The power switch system of claim 8, wherein the power switch system is configured so that in a switching operation of the low-side transistor the transistor segments are switched sorted according to their electrical resistance to the storage inductor.

13. The power switch system of claim 12, wherein the power switch system is configured so that in a switch-on operation of the low-side transistor the transistor segments are switched on in sequence from the highest resistance to the lowest resistance in time-staggered fashion.

14. The power switch system of claim 12, wherein the power switch system is configured so that in a switch-off operation of the low-side transistor the transistor segments are switched off in sequence from the lowest resistance to the highest resistance in time-staggered fashion.

15. The power switch system of claim 8, wherein the power switch system is configured so that the time interval during a switching operation between switching two consecutively connected transistor segments is less than 30 ns.

16. The power switch system of claim 8, wherein the power switch system is configured so that the time interval during a switching operation between switching two consecutively connected transistor segments is less than 5 ns.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0018] FIG. 1 shows a circuit diagram of a specific embodiment of a power switch system according to the present invention.

[0019] FIG. 2 shows a simplified diagram of the drain current and the drain voltage of a power switch in the related art.

[0020] FIG. 3 shows a simplified diagram of the drain current and the drain voltage of a power switch system according to the invention.

[0021] FIG. 4 shows a simplified diagram of the drain voltage of a power switch in the related art.

[0022] FIG. 5 shows a simplified diagram of the drain voltage of a power switch system according to the invention.

DETAILED DESCRIPTION

[0023] FIG. 1 shows a circuit diagram of a specific embodiment of a power switch system 1 according to the invention comprising a low-side transistor LSS and a high-side transistor HSS. The low-side transistor LSS and the high-side transistor HSS are configured in such a way that they are switched to be conductive or switched to be blocking in time segments of a switching period of power switch system 1 that are respectively alternating relative to one another. A source terminal 2 of low-side transistor LSS is connected to a load terminal 3, via which a connected load 4 is supplied with an output voltage V.sub.out. A drain terminal 5 of the low-side transistor LSS is connected to a supply voltage V.sub.in via a storage inductor L.

[0024] A drain terminal 6 of the high-side transistor HSS is connected to load terminal 3, and a source terminal 7 of high-side transistor HSS is connected to supply voltage V.sub.in via storage inductor L.

[0025] According to the present invention, the low-side transistor LSS now comprises at least two (here three) transistor segments LSS1, LSS2, LSS3. At least two of the transistor segments LSS1, LSS2, LSS3 have in the connection to storage inductor L a different electrical resistance R1, R2, R3. The transistor segments LSS1, LSS2, LSS3 are here represented as power transistors, connected in parallel, having separate path resistances R1, R2, R3, although they are in fact combined in a common low-side transistor LSS. Alternatively, the transistor segments LSS1, LSS2, LSS3 may also be connected in parallel as discrete components. Power switch system 1 is configured in such a way that at least two of the transistor segments LSS1, LSS2, LSS3 are switched at a different point in time during a switching operation of power switch system 1.

[0026] At least two of the transistor segments LSS1, LSS2, LSS3 may comprise differently sized area proportions of low-side transistor LSS. Apart from a little more overhead, the area on the chip of low-side transistor LSS remains constant with respect to a non-segmented low-side transistor. The differently sized area proportions result in different path resistance values R1, R2, R3 of the transistor segments LSS1, LSS2, LSS3. Due to the time-staggered switching on of the individual transistor segments LSS1, LSS2, LSS3 within a short time, the current is not forced to commutate suddenly. Overvoltage and subsequent build-up are prevented, which results in improvements in the spectrum. In the ideal case, the steepness of the voltage switching edge (for example of the drain voltage of low-side transistor LSS) is not influenced in the process. Alternatively, transistor segments LSS1, LSS2, LSS3 may comprise area proportions of equal size, it then being possible to interconnect differently dimensioned resistors to storage inductor L. In the circuit in FIG. 1, resistors R1, R2, R3 are then to be understood as separate switching elements and not, as may be provided, as representations of the different path resistances of transistor segments LSS1, LSS2, LSS3.

[0027] Each one of the transistor segments may be assigned to its own gate segment 8 of the gate terminal of low-side transistor LSS, the associated transistor segment LSS1, LSS2, LSS3 being switched by switching one of gate segments 8. The gate terminal is then likewise segmented in accordance with the transistor segments LSS1, LSS2, LSS3 so that switching a gate segment 8 effects the switching of the associated transistor segment LSS1, LSS2, LSS3.

[0028] FIGS. 2 and 3 elucidate the background of the present invention. A simplified diagram respectively shows the drain current and the drain voltage of a low-side transistor LSS over time t across two switching operations.

[0029] FIG. 2 shows the drain current I.sub.DS and the drain voltage V.sub.DS of a low-side transistor LSS in the related art. Switching edges 9 of drain voltage V.sub.DS are in this case comparatively sharp and result in overvoltages (see also FIG. 4) if the duration of the switching operation is selected to be too short. Thus there only remains the choice of accepting longer switching times and greater switching losses in order to achieve a sufficient EMC compatibility.

[0030] FIG. 3 shows the drain current I.sub.DS and the drain voltage V.sub.DS of a low-side power switch LSS of a power switch system according to the present invention. Here the switching edges 10 of drain voltage V.sub.DS are now less steep and no longer result in overvoltages, even if the duration of the switching operation in the middle of the switching operation of the low-side transistor LSS is selected to be quite short. The greater steepness of the switching edge in the middle of the switching operation and the shorter switching time result in lower switching losses, while improving the EMC emission nevertheless.

[0031] FIGS. 4 and 5 elucidate the main effect of the present invention. Compared to FIGS. 2 and 3, a somewhat more realistic curve of the drain voltage V.sub.DS of a low-side power switch LSS is shown in each case over time t across two switching operations.

[0032] FIG. 4 shows a low-side power switch LSS of the related art (corresponding to FIG. 2), which has a relatively short switching time, low switching losses and thus a steep switching edge. Unfortunately, such a low-side power switch LSS also results in switching oscillations 11 at the end of a switch-off operation or a switch-on operation that are quite pronounced. This may result in overvoltages and worsen the EMC compatibility.

[0033] FIG. 5 shows a low-side power switch LSS according to the present invention (corresponding to FIG. 3), which has a relatively short switching time, low switching losses and thus a steep switching edge. Because of the fact that the low-side transistor LSS now comprises at least two transistor segments LSS1, LSS2, LSS3, which have a different electrical resistance R1, R2, R3 in the connection to storage inductor L, it is possible to achieve markedly reduced switching oscillations 12 at the end of a switch-off operation or a switch-on operation by a staggered switching of transistor segments LSS1, LSS2, LSS3. Overvoltages are thereby reduced and the EMC compatibility is improved, without markedly increasing switching losses.