Light emitting diode and fabrication method therof

Abstract

A light-emitting diode includes from bottom to up: a substrate, a first-conductive type semiconductor layer, a super lattice, a multi-quantum well layer and a second-conductive type semiconductor layer. At least one layer of granular medium layer is inserted in the super lattice. The granular medium layer is used for forming V pits with different widths and depths in the super lattice. The multi-quantum well layer fills up the V pits and is over the top surface of the super lattice. The number of micro-particle generations, positions and densities can be adjusted by introducing granular medium layers and controlling the number of layers, position and growth conditions during super lattice growth process, to ensure V pits of different depths and densities. This can change hole injection effect, effectively improve hole injection efficiency and distribution uniformity in all quantum wells, thus improving LED light-emitting efficiency.

Claims

1. A light-emitting diode, comprising: a first-conductive type semiconductor layer; a super lattice; a multi-quantum well layer; a second-conductive type semiconductor layer; wherein, at least one medium layer having a plurality of grains therein is embedded in the super lattice; the medium layer is used for forming V pits with different widths and depths in the super lattice; the multi-quantum well layer fills up the V pits and is over a top surface of the super lattice; and a density of the plurality of grains in the medium layer is approximately same as that of the V pits.

2. The light-emitting diode of claim 1, wherein, sizes of the plurality of grains in the medium layer are 0.5-5 nm, and the V pits are 50-500 nm wide.

3. The light-emitting diode of claim 1, wherein, the depth H of the V pits depends on a total thickness of the super lattice T1, a total thickness of the multi-quantum well layer T2 and a position of the medium layer in the super lattice layer, and satisfies T2<H<T1+T2.

4. The light-emitting diode of claim 1, wherein, the density of the plurality of grains in the medium layer ranges from 110.sup.7 cm.sup.2 to 110.sup.9 cm.sup.2.

5. The light-emitting diode of claim 1, wherein, the medium layer comprises at least one of Mg.sub.xN.sub.y, Si.sub.xN.sub.y, Si.sub.xO.sub.y, Ti.sub.xO.sub.y, Zr.sub.xO.sub.y, Hf.sub.xO.sub.y, or Ta.sub.xO.sub.y.

6. The light-emitting diode of claim 1, wherein, three granular medium layers are inserted during growth of the super lattice.

7. A method of fabricating the light-emitting diode according to claim 1, the method comprising: (1) providing a substrate; (2) growing a first-conductive type semiconductor layer over the substrate; (3) forming a super lattice over the first-conductive type semiconductor layer, and inserting at least one medium layer having a plurality of grains therein during growth of the super lattice, wherein, the medium layer is used for forming V pits with different widths and depths in the super lattice; (4) growing a multi-quantum well layer over the V pits and a top surface of the super lattice; (5) growing a second-conductive type semiconductor layer over the multi-quantum well layer.

8. The fabrication method of claim 7, wherein: sizes of the plurality of grains in the medium layer are 0.5-5 nm, and the V pits are 50-500 nm wide.

9. The fabrication method of claim 7, wherein, the depth H of the V pits depends on a total thickness of the super lattice T1, a total thickness of the multi-quantum well layer T2 and a position of the granular medium layer in the super lattice layer, and satisfies T2<H<T1+T2.

10. The fabrication method of claim 7, wherein, the density of the plurality of grains in the medium layer ranges from 110.sup.7 cm.sup.2 to 110.sup.9 cm.sup.2.

11. The fabrication method of claim 7, wherein, the medium layer comprises at least one of Mg.sub.xN.sub.y, Si.sub.xN.sub.y, Si.sub.xO.sub.y, Ti.sub.xO.sub.y, Zr.sub.xO.sub.y, Hf.sub.xO.sub.y, or Ta.sub.xO.sub.y.

12. The fabrication method of claim 7, wherein, a growth temperature for the super lattice is 700-900 C.

13. The fabrication method of claim 7, wherein, in step (3), at least one medium layer is inserted during growth of the super lattice; thereby facilitating the super lattice to form the V pits at the medium layer from an epitaxial surface due to low growth temperature and poor lateral epitaxial capacity.

14. A light-emitting system comprising a plurality of light-emitting diodes, wherein each light-emitting diode comprises: a first-conductive type semiconductor layer; a super lattice; a multi-quantum well layer; a second-conductive type semiconductor layer; wherein, at least one medium layer having a plurality of grains therein is embedded in the super lattice; the medium layer is used for forming V pits with different widths and depths in the super lattice; the multi-quantum well layer fills up the V pits and is over a top surface of the super lattice; and a density of the plurality of grains in the medium layer is approximately same as that of the V pits.

15. The light-emitting system of claim 14, wherein, sizes of the plurality of grains in the medium layer are 0.5-5 nm, and the V pits are 50-500 nm wide.

16. The light-emitting system of claim 14, wherein, the depth H of the V pits depends on a total thickness of the super lattice T1, a total thickness of the multi-quantum well layer T2 and a position of the granular medium layer in the super lattice layer, and satisfies T2<H<T1+T2.

17. The light-emitting system of claim 14, wherein, the density of the plurality of grains in the medium layer ranges from 110.sup.7cm.sup.2 to 110.sup.9cm.sup.2.

18. The light-emitting system of claim 14, wherein, the medium layer comprises at least one of Mg.sub.xN.sub.y, Si.sub.xN.sub.y, Si.sub.xO.sub.y, Ti.sub.xO.sub.y, Zr.sub.xO.sub.y, Hf.sub.xO.sub.y, or Ta.sub.xO.sub.y.

19. The light-emitting system of claim 14, wherein, three medium layers are inserted during growth of the super lattice.

20. The light-emitting system of claim 14, wherein, a growth temperature for the super lattice is 700-900 C.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The accompanying drawings, which are included to provide a further understanding of the disclosure and constitute a part of this specification, together with the embodiments, are therefore to be considered in all respects as illustrative and not restrictive. In addition, the drawings are merely illustrative, which are not drawn to scale.

(2) In the drawings: 1: substrate; 2: buffer layer; 3: U-GaN layer; 4: N-GaN layer; 5: super lattice; 6 (6A, 6B, 6C): granular medium layer; 7: multi-quantum well layer; 8: electronic blocking layer; 9: P-GaN layer; 10: contact layer.

(3) FIG. 1 illustrates a sectional view of the LED epitaxial structure according to some embodiments in the present disclosure.

(4) FIG. 2 illustrates a top view of the LED epitaxial structure according to some embodiments of the present disclosure.

(5) FIG. 3 shows a schematic diagram of hole injection positions in MQW of V pits at different depths.

DETAILED DESCRIPTION

(6) The present disclosure will be explained in details with reference to the accompanying drawings. Before further description, it should be understood, however, that various modifications and changes may be made to these embodiments. Therefore, the present disclosure is not limited to the embodiments below. It should also be noted that the scope of the present disclosure should still be subjected to the scope defined in the claims and the embodiments are merely for purposes of illustration, rather than restricting. Unless otherwise specified, all technical and scientific words shall have the same meanings as understood by persons skilled in the art.

Embodiment 1

(7) With reference to FIGS. 1 and 2, an LED epitaxial structure is provided, which includes from bottom to up: a substrate 1, a buffer layer 2, a first-conductive type semiconductor layer including a U-GaN layer 3 and an N-GaN layer 4, a super lattice 5, a multi-quantum well layer 7 and a second-conductive type semiconductor layer comprising an electronic blocking layer 8, a P-GaN layer 9 and a contact layer 10; wherein, at least one granular medium layer 6 is inserted in the super lattice. The granular medium layer 6 is used for forming V pits of different widths and depths in the super lattice, and the multi-quantum well layer 7 fills up the V pits and is over the super lattice.

(8) Specifically, the substrate 1 in this embodiment is selected from at least one of sapphire (Al.sub.2O.sub.3), SiC, GaAs, GaN, ZnO, Si, GaP, InP and Ge. In some embodiments, a plain sapphire substrate is preferred, which is not illustrated. The sapphire substrate can also be a patterned sapphire substrate (PSS), but the embodiments are not limited thereto.

(9) The buffer layer 2 is formed over the substrate 1 with InAlGaN semiconductor material, which eliminates the lattice mismatch caused by lattice constant difference between the substrate 1 and the first-conductive type semiconductor layer, thus improving epitaxial growth quality.

(10) The U-GaN layer 3 and the N-GaN layer 4 form a first-conductive type semiconductor layer, which are grown over the buffer layer 2 in successive. The U-GaN layer 3 can eliminate the lattice mismatch caused by lattice constant difference between the substrate 1 and the N-GaN layer 4. In addition, the U-GaN layer 3 can improve the crystallization property of the semiconductor layer formed over this layer.

(11) The super lattice 5 is formed over the first-conductive type semiconductor layer, which is repeatedly and alternatively stacked by InGaN layers and GaN layers for about 15-25 times. Insert three granular medium layers 6 (6A, 6B and 6C) in the super lattice 5, which are used for forming V pits in the super lattice. The material of the granular medium layers is Mg.sub.xN.sub.y, Si.sub.xN.sub.y, Si.sub.xO.sub.y, Ti.sub.xO.sub.y, Zr.sub.xO.sub.y, Hf.sub.xO.sub.y, Ta.sub.xO.sub.y or any of their combinations. In this embodiment, Si.sub.xN.sub.y is preferred with grain size of 0.5-5 nm. The depth H (such as H.sub.6A) of the V pits depends on the total thickness of the super lattice T1, the total thickness of the multi-quantum well layer T2 and the position of the granular medium layer in the super lattice layer, and satisfies T2<H<T1+T2. The density of the SiN granular medium layer is basically corresponding to that of the V pits, which ranges from 110.sup.7 cm.sup.2 to 110.sup.9 cm.sup.2.

(12) A multi-quantum well layer 7 fills up the V pits and is over the top surface of the super lattice 5. The multi-quantum well layer can be In.sub.xAl.sub.yGa.sub.1-x-yN (0x1, 0y1, 0x+y1) semiconductor material, which is alternatively stacked by a plurality of well layers and barrier layers, in some embodiments, for 4-20 times.

(13) An electronic blocking layer 8, a P-GaN layer 9 and a contact layer 10 form a second-conductive type semiconductor layer, which are formed over the multi-quantum well layer 7 in successive.

(14) Referring to FIG. 3, QW-6A, QW-6B and QW-6C represent hole injection concentration of V pits of three different depths in main positions of the MQW. 6A is the deepest layer of V pits, wherein, when holes are injected to the MQW through this layer of V pits, hole injection is distributed at the bottom QW. 6B is the middle layer of V pits, wherein, when holes are injected to the MQW through this layer of V pits, hole injection is mainly distributed in the middle QW. 6C is the shallowest layer of V pits, wherein, when holes are injected to the MQW through this layer of V pits, hole injection is mainly distributed over the uppermost QW. In the present disclosure, space distribution of holes in MQW and hole injection concentration of the LED can be improved by controlling sizes, depths and densities of V pits of layers 6A, 6B and 6C, thus improving hole injection efficiency of all QWs and lighting efficiency of LED.

Embodiment 2

(15) Referring to FIGS. 1-2, a fabrication method of a LED epitaxial structure is provided, which includes: (1) providing a substrate 1, which can be at least one of sapphire (Al.sub.2O.sub.3), SiC, GaAs, GaN, ZnO, Si, GaP, InP and Ge. In some embodiments, a patterned sapphire substrate (PSS) is preferred. (2) forming a buffer layer 2 over the substrate 1. In some embodiments, InAlGaN semiconductor material is preferred. The epitaxial growth method can be MOCVD (metal-organic chemical vapor deposition), CVD (chemical vapor deposition), PECVD (plasma enhanced vapor deposition), MBE (molecular beam epitaxy) and HVPE (hydride vapor phase epitaxy). It is preferred to be MOCVD, but the embodiments are not limited thereto. (3) growing a U-GaN layer 3 and an N-GaN layer 4 in successive over the buffer layer 2 to form a first-conductive type semiconductor layer. (4) growing a super lattice 5 via epitaxial growth over the first-conductive type semiconductor layer under 700-900 C., which is repeatedly and alternatively stacked by InGaN layers and GaN layers for about 15-25 times. Insert 3 layers of silicon nitride (Si.sub.xN.sub.y) granular medium layers 6 (6A, 6B and 6C) in the super lattice 5. It is easy to form V pits over the granular medium layer from the epitaxial surface due to the low growth temperature and poor lateral epitaxial capacity of the super lattice. In this embodiment, the grain size of the granular medium layer prefers to be 0.5-5 nm, and the width of V pits ranges from 50 nm to 500 nm. The depth H of the V pits depends on the total thickness of the super lattice T1, the total thickness of the multi-quantum well layer T2 and the position of the granular medium layer in the super lattice layer, and satisfies T2<H<T1+T2. The density of the granular medium layer is basically corresponding to that of the V pits, which ranges from 110.sup.7 cm.sup.2 to 110.sup.9 cm.sup.2. The growth sequence of 3 granular medium layers is: 6A, 6B and 6C. The size, depth and density of the V pits are to be optimized based on chip design and working current. Based on theoretical calculation and reference to experimental results, in this embodiment, preferably, V pits depth relationship is: 6A>6B>6C; and position depth in the super lattice relationship is: 6A>6B>6C; and density relationship is: 6B>6C>6A. (5) forming a multi-quantum well layer 7 over the V pits and the top surface of the super lattice 5 via epitaxial growth. The multi-quantum well layer is In.sub.xAl.sub.yGa.sub.1-x-yN (0x1, 0y1, 0x+y1), and is alternatively stacked by a plurality of well layers and barrier layers, preferably, for 4-20 times. (6) forming an electronic blocking layer 8, a P-GaN layer 9 and a contact layer 10 over the multi-quantum well layer 7 via epitaxial growth to form a second-conductive type semiconductor layer.

(16) Although specific embodiments have been described above in detail, the description is merely for purposes of illustration. It should be appreciated, therefore, that many aspects described above are not intended as required or essential elements unless explicitly stated otherwise. Various modifications of, and equivalent acts corresponding to, the disclosed aspects of the exemplary embodiments, in addition to those described above, can be made by a person of ordinary skill in the art, having the benefit of the present disclosure, without departing from the spirit and scope of the disclosure defined in the following claims, the scope of which is to be accorded the broadest interpretation so as to encompass such modifications and equivalent structures.