Power detection circuit for tracking maximum power point of solar cell and method thereof

Abstract

Provided is a power detection circuit for tracking a maximum power point of a solar cell. The power detection circuit includes: an average voltage extracting unit which extracts an average voltage V.sub.PV,LPF from an external voltage V.sub.PV input from an external energy source; a ripple voltage extracting unit which extracts a ripple voltage including current information of the external voltage V.sub.PV from the external voltage V.sub.PV; a voltage-time converter which generates a ramp voltage V.sub.RAMP changing at a predetermined rate and converts the average voltage V.sub.PV,LPF and the ripple voltage into corresponding time information t.sub.1 and t.sub.2 based on the ramp voltage V.sub.RAMP; a time-digital converter which converts the time information t.sub.2 for the ripple voltage into a digital code t.sub.2 [n:0]; and a time multiplier which multiplies the digital code t.sub.2 [n:0] and the time information t.sub.1 for the average voltage V.sub.PV,LPF to output a specific voltage value.

Claims

1. A power detection circuit, comprising: an average voltage extracting unit which extracts an average voltage from an external voltage input from an external energy source; a ripple voltage extracting unit which extracts a ripple voltage from the external voltage; a voltage-time converter which generates a ramp voltage changing at a predetermined rate and converts the average voltage and the ripple voltage into corresponding time information based on the ramp voltage; a time-digital converter which converts the time information for the ripple voltage into a digital code; and a time multiplier which multiplies the digital code and the time information for the average voltage and outputs a specific voltage value, wherein the voltage-time converter includes: a ramp generator which generates the ramp voltage; a first comparator which compares the ramp voltage and the average voltage; a first D flip-flop which synchronizes a result signal of the first comparator with a system clock to output a first pulse wave having time information for the average voltage; a second comparator which compares the ramp voltage with the maximum value of the external voltage; a third comparator which compares the ramp voltage with the minimum value of the external voltage; and a second D flip-flop which synchronizes a result signal of the second and third comparators with the system clock to output a second pulse wave having time information for the ripple voltage.

2. The power detection circuit according to claim 1, wherein the external energy source is a solar cell and the external voltage has a triangular waveform.

3. The power detection circuit according to claim 1, wherein the average voltage extracting unit includes a low pass filter (LPF) through which the external voltage passes to extract the average voltage.

4. The power detection circuit according to claim 1, wherein the ripple voltage extracting unit includes a sample and hold circuit (S/H) which extracts a maximum value and a minimum value of the external voltage by sampling the external voltage .

5. The power detection circuit according to claim 1, wherein the voltage-time converter further includes: a first switch which controls the ramp voltage to be transmitted to the first comparator; and a second switch which controls the ramp voltage to be transmitted to the second and third comparators; and the first switch and the second switch oppositely operate to selectively operate the first comparator and the second and third comparators.

6. The power detection circuit according to claim 5, wherein the voltage-time converter further includes: first and second capacitors which reduce a noise when the first and second switches are on/off.

7. The power detection circuit according to claim 1, wherein the time-digital converter includes multi-stage D flip-flops.

8. The power detection circuit according to claim 1, wherein the time multiplier includes: n+1 current sources which mirror a current reference; a switch group which includes n+1 switches corresponding to the n+1 current sources one by one and determines a magnitude of a current flowing the time multiplier depending on whether the n+1 switches are on/off; a first capacitor which charges a voltage with a magnitude of the current determined in the switch group; and a third switch which controls connection of the switch group and the first capacitor depending on whether to be on/off, the n+1 switches included in the switch group are controlled to be on/off by the digital code and the third switch is controlled to be on/off by time information for the average voltage.

9. The power detection circuit according to claim 8, wherein the time multiplier further includes: a second capacitor which is selected alternately with the first capacitor to charge a voltage with a magnitude of a current determined in the switch group; fourth and fifth switches which control the first and second capacitors to be alternately selected on the basis of a specific unit time; and a comparator which compares a voltage charged in the first capacitor and a voltage charged in the second capacitor to output an up-down signal.

10. A power detecting method of a power detection circuit for tracking a maximum power point of an external voltage input from an external energy source, the method comprising: an average voltage extracting step of extracting an average voltage from an external voltage; a ripple voltage extracting step of extracting a ripple voltage from the external voltage; a ramp voltage generating step of generating a ramp voltage changing at a predetermined rate; a voltage-time converting step of converting the average voltage and the ripple voltage into corresponding time information based on the ramp voltage; a time-digital converting step of converting the time information for the ripple voltage into a digital code; and a time multiplying step of multiplying the digital code and the time information for the average voltage to output a specific voltage value; wherein the voltage-time converting step includes: a first comparing step of comparing the ramp voltage and the average voltage; a first synchronizing step of synchronizing a result signal of the first comparing step with a system clock to output a first pulse wave having time information for the average voltage; a second comparing step of comparing the ramp voltage with a maximum value of the external voltage; a third comparing step of comparing the ramp voltage with a minimum value of the external voltage; and a second synchronizing step of synchronizing a result signal of the second and third comparing steps with the system clock to output a second pulse wave having time information for the ripple voltage.

11. The method according to claim 10, wherein the external energy source is a solar cell and the external voltage has a triangular waveform.

12. The method according to claim 10, wherein in the average voltage extracting step, the average voltage is extracted by passing the external voltage through a low pass filter LPF.

13. The method according to claim 10, wherein in the ripple voltage extracting step, a maximum value and a minimum value of the external voltage are extracted by sampling the external voltage.

14. The method according to claim 10, wherein the time multiplying step includes: determining a magnitude of a current to determine a specific voltage value by the digital code; determining a charging time based on time information for the average voltage; and charging a first capacitor with the determined magnitude of current during the determined time.

15. The method according to claim 14, wherein the time multiplying step further includes: charging the current by alternately selecting the first capacitor and a second capacitor in accordance with an elapse of time; and comparing a voltage charged in the first capacitor and a voltage charged in the second capacitor to output an up-down signal.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The above and other aspects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

(2) FIG. 1 is a schematic block diagram of a power detection circuit.

(3) FIG. 2 is a circuit diagram of a voltage-time converter (V-T converter).

(4) FIG. 3 is a circuit diagram of a time-digital converter (T-D converter).

(5) FIG. 4 is a circuit diagram of a time multiplier.

(6) FIG. 5 is a processing flowchart of a power detecting method.

(7) FIG. 6 is a processing flowchart of a voltage-time converting process.

(8) FIG. 7 is a processing flowchart of a time multiplying process.

(9) FIG. 8 is a view illustrating equations representing a principle for tracking a maximum power point by a power detection circuit and a method thereof.

(10) FIG. 9 is a view illustrating waveforms generated during a process of tracking a maximum power point by a power detection circuit and a method thereof.

(11) FIG. 10 is a view illustrating a power graph of a solar cell and a simulation result for a power value tracked by the present disclosure.

(12) FIG. 11 is a performance comparison table obtained by comparing performances of the present disclosure and the related art.

DETAILED DESCRIPTION

(13) In the following detailed description, only certain exemplary embodiments of the present disclosure have been described so that those skilled in the art may easily carry out the present disclosure. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present disclosure. In the meantime, the drawings and description are to be regarded as illustrative in nature and not restrictive. Like reference numerals designate like elements throughout the specification. Further, even though a detailed description is omitted, if those skilled in the art may easily understand the description, the description will be omitted.

(14) In the specification and the claim, unless explicitly described to the contrary, the word comprise and variations such as comprises or comprising, will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.

(15) FIG. 1 is a schematic block diagram of a power detection circuit. In an example of FIG. 1, a power detection circuit 100 operates based on a direct power detecting method and operates in response to a voltage V.sub.PV input from a solar cell (PV cell) 10 which is an external energy source. That is, the power detection circuit 100 illustrated in FIG. 1 operates to detect a power of the voltage V.sub.PV input from the solar cell (PV cell) 10.

(16) Referring to FIG. 1, the power detection circuit 100 of the present disclosure includes a low pass filter (LPF) 110, a sample and hold circuit (S/H) 120, a voltage-time converter (V-T converter) 130, a time-digital converter (T-D converter) 140, and a time multiplier 150.

(17) The low pass filter (LPF) 110 obtains an average voltage V.sub.PV,LPF from an external voltage V.sub.PV having a triangular waveform.

(18) The sample and hold circuit (S/H) 120 extracts a ripple voltage including current information of the external voltage V.sub.PV from the external voltage V.sub.PV. That is, since the power detection circuit 100 of the present disclosure tracks the power by detecting only the voltage, the sample and hold circuit (S/H) 120 performs sampling on the external voltage V.sub.PV having a triangular waveform and then obtains a maximum value V.sub.S2 and a minimum value V.sub.S1 of the external voltage V.sub.PV.

(19) In the meantime, FIG. 9 is a view illustrating waveforms generated during a process of tracking a maximum power point by a power detection circuit and a method thereof. In FIG. 9A, an external voltage V.sub.PV having a triangular waveform, an average voltage V.sub.PV,LPF value obtained by passing the external voltage V.sub.PV through the low pass filter LPF 110, a maximum value (peak sample) V.sub.S2 and a minimum value (under peak sample) V.sub.S1 of the external voltage V.sub.PV obtained by sampling the external voltage V.sub.PV are represented.

(20) Referring to FIG. 1 again, the voltage-time converter 130 converts an input voltage value into time information to detect a power at a time domain. For example, the voltage-time converter (V-T converter) 130 receives the average voltage V.sub.PV,LPF output from the low pass filter (LPF) 110 and the maximum value V.sub.S2 and the minimum value V.sub.S1 of the external voltage V.sub.PV output from the sample and hold circuit (S/H) 120 as inputs to convert the inputs into corresponding time information t.sub.1 and t.sub.2 and output the converted time information. To this end, the voltage-time converter 130 is configured as illustrated in FIG. 2 and generates an independent ramp signal V.sub.RAMP and compares the average voltage V.sub.PV,LPF and the maximum value V.sub.S2 and the minimum value V.sub.S1 of the external voltage V.sub.PV with the ramp signal V.sub.RAMP, respectively. A specific operation of the voltage-time converter 130 will be mentioned again in description with reference to FIG. 2. The ramp signal V.sub.RAMP A, the average voltage V.sub.PV,LPF, and the maximum value V.sub.S2 and the minimum value V.sub.S1 of the external voltage V.sub.PV are illustrated in FIG. 9B and examples of the time information t.sub.1 and t.sub.2 generated by the comparison result are illustrated in FIGS. 9C and 9D. That is, FIG. 9C illustrates a pulse wave VS_TIME having the time information t.sub.1 for the average voltage and FIG. 9D illustrates a pulse wave DV_TIME having the time information t.sub.2 for the ripple voltage.

(21) The time-digital converter 140 converts the input time information into a digital code. That is, the time-digital converter receives the pulse wave DV_TIME having the time information t.sub.2 for the ripple voltage from the voltage-time converter 130 and converts the pulse wave into a digital code t.sub.2 [n:0] and output the digital code. To this end, the time-digital converter 140 may be implemented by multi-stage D flip-flops as illustrated in FIG. 3. In this case, a series of processes of generating the digital code t.sub.2 [n:0] from the pulse wave DV_TIME having the time information t.sub.2 for the ripple voltage using the circuit of FIG. 3 may be performed using a known technique. In the meantime, in an example of FIG. 1, the time-digital converter 140 outputs (n+1) bits of digital code. However, the present disclosure is not limited to (n+1) bits. That is, a high n value or a low n value may be applied depending on the time-digital converter 140. In FIG. 9E, an example of the digital code t.sub.2 [n:0] output from the time-digital converter 140 is illustrated.

(22) The time multiplier 150 converts a value which is converted into a digital code in the time-digital converter 140 into analog voltage information and outputs the converted analog voltage information. Further, the time multiplier 150 compares the generated analog voltage with a previous analog voltage to detect the power. To this end, the time multiplier 150 is configured as illustrated in FIG. 4 and multiplies the digital code t.sub.2 [n:0] and the time information t.sub.1 to output a specific voltage value. In this case, the digital code t.sub.2[n:0] determines a magnitude of a current for determining the specific voltage value and the time information t.sub.1 determines a charging time. A specific operation of the time multiplier 150 will be mentioned again in description with reference to FIG. 4. In FIG. 9F, an example of a voltage value V.sub.TM,n obtained by multiplying the digital code t.sub.2[n:0] and the time information t.sub.1 is illustrated.

(23) In the meantime, the DC-DC converter 20 illustrated in FIG. 1 is provided to receive a power from the solar cell V.sub.PV to supply the power to a circuit having a different voltage level and is necessary for verification of the power detection circuit 100.

(24) As described above, when an external voltage V.sub.PV having a triangular waveform as illustrated in FIG. 9A is input, the power detecting circuit 100 of the present disclosure extracts a ripple voltage value during a minute interval and an average voltage value (see FIG. 9B) based on the external voltage V.sub.PV, converts the ripple voltage value and the average voltage value into time information (see FIGS. 9C and 9D), and then obtains a voltage value V.sub.TM (see FIG. 9F) through the time-digital converter 140 and the time multiplier 150. The voltage V.sub.TM represents the relative magnitude of power in various environment energy conditions.

(25) FIG. 2 is a circuit diagram of a voltage-time converter (V-T converter) and illustrates a detailed configuration of the voltage-time converter 130 illustrated in FIG. 1.

(26) Referring to FIG. 2, the voltage-time converter 130 includes a ramp generator, first and second switches 131 and 132, first to third comparators 133 to 135, and first and second D flip-flops 136 and 137.

(27) The ramp generator is to generate a ramp voltage V.sub.RAMP which is a reference for converting a voltage into a time and includes a current reference I.sub.bias, a reset switch which is controlled to be on/off in response to an RST signal, and a capacitor C.sub.RAMP. In the meantime, an operation principle of the ramp generator is as follows: when the reset switch is off, the current reference I.sub.bias is charged in the capacitor C.sub.RAMP for a predetermined time, and a voltage of the capacitor C.sub.RAMP is discharged through a periodical reset signal RST to generate the ramp voltage V.sub.RAMP. In this case, the generated ramp voltage V.sub.RAMP has a triangular waveform A as illustrated in FIG. 9B.

(28) The first comparator 133 compares the ramp voltage V.sub.RAMP and the average voltage V.sub.PV,LPF and transmits the comparison result to the first D flip-flop 136. By doing this, the first D flip-flop 136 synchronizes a result signal of the first comparator 133 with a system clock to output a first pulse wave VS_TIME t.sub.1 having time information for the average voltage V.sub.PV,LPF.

(29) The second comparator 134 and the third comparator 135 compare the ramp voltage V.sub.RAMP and the maximum value V.sub.S2 of the external voltage V.sub.PV and compare the ramp voltage V.sub.RAMP and the minimum value V.sub.S1 of the external voltage V.sub.PV and transmit the result to the D flip-flop 137. By doing this, the second D flip-flop 137 synchronizes the result signals of the second comparator 134 and the third comparator 135 with a system clock and outputs a second pulse wave DV_TIME t.sub.2 having the time information for the ripple voltage.

(30) In the meantime, the first switch 131 controls the ramp voltage V.sub.RAMP to be transmitted to the first comparator 133 and the second switch 132 controls the ramp voltage V.sub.RAMP to be transmitted to the second and third comparators 134 and 135. In this case, the first switch 131 and the second switch 132 oppositely operate to selectively operate the first comparator 133 and the second and third comparators 134 and 135. That is, only when the comparators 133 to 134 operate, the ramp voltage V.sub.RAMP is applied to the corresponding comparator. The reason is to suppress power consumption due to the continuously turned-on comparators which operate at high speed. The first to third comparators 133 to 135 are synchronized with the first switch 131 and the second switch 132 to perform power gating.

(31) Further, capacitors C.sub.1 and C2 having a small capacity are placed in a connection line of the first and second switches 131 and 132 and comparators 133 to 135 at subsequent ends. The reason is to reduce a noise when the first and second switches 131 and 132 are on/off.

(32) FIG. 4 is a circuit diagram of a time multiplier and illustrates a detailed configuration of the time multiplier 150 illustrated in FIG. 1.

(33) Referring to FIG. 4, the time multiplier 150 includes a current reference I.sub.UNIT, a third switch 151, n+1 current sources 152, a switch group 153 including n+1 switches, and a voltage value storing and comparing unit 154.

(34) The third switch 151 controls a connection between the switch group 153 and the voltage value storing and comparing unit 154 depending on whether to be on/off. Specifically, the third switch 151 controls the connection of the first or second capacitor C.sub.1 or C.sub.2 and the switch group 153 which are included in the voltage value storing and comparing unit 154 to store the voltage value. Therefore, it is possible to determine whether to charge depending on the on/off of the third switch 151. However, an on-time of the third switch 151 is determined by the time information t.sub.1 for the average voltage V.sub.PV,LPF so that as a result, the time information t.sub.1 for the average voltage V.sub.PV,LPF may determine a charging time.

(35) n1 current sources 152 mirror the current reference I.sub.UNIT.

(36) The switch group 153 includes n+1 switches corresponding to n+1 current sources 152 one by one and determines a current amount in the time multiplier 150 depending on on/off of the switches. That is, the switch group 153 determines a magnitude of the current which is transmitted to the first or second capacitor C.sub.1 or C.sub.2 depending on the number of switches which are on. For example, when five switches are on, a magnitude of the current which is transmitted to the first or second capacitor C.sub.1 or C.sub.2 is I.sub.UNIT5.

(37) In this case, since the n+1 switches included in the switch group 153 are controlled to be on/off by the digital code t.sub.2[n:0], the current amount in the time multiplier 150 is determined by the digital code t.sub.2[n:0].

(38) The voltage value storing and comparing unit 154 includes first and second capacitors C.sub.1 and C.sub.2, fourth and fifth switches, and a comparator. The first and second capacitors C.sub.1 and C.sub.2 are alternately selected on the basis of a specific unit time and charges the voltage in accordance with the magnitude of the current determined by the switch group 153. The fourth and fifth switches control the first and second capacitors C.sub.1 and C.sub.2 to be alternately selected on the basis of the specific unit time. Further, the comparator compares the voltages charged in the first and second capacitors C.sub.1 and C.sub.2 to compare a current power value and a previous power value and then output an up-down signal UP_DN.

(39) FIG. 5 is a processing flowchart of a power detecting method. Referring to FIGS. 1 and 5, a power detecting method of a power detection circuit 100 of the present disclosure is as follows.

(40) First, a power detection circuit 100 operates based on a direct power detecting method and operates in response to an external voltage V.sub.PV input from a solar cell (PV cell) 10 which is an external energy source. That is, the power detection circuit 100 illustrated in FIG. 1 operates to detect a power of the external voltage V.sub.PV input from the solar cell (PV cell) 10.

(41) To this end, in step S100, an external voltage V.sub.PV having a triangular waveform passes through the LPF 110 to extract an average voltage V.sub.PV,LPF. In step S200, the S/H 120 extracts a ripple voltage including current information of the external voltage V.sub.PV from the external voltage V.sub.PV. That is, the S/H 120 samples the external voltage V.sub.PV to extract a maximum value V.sub.S2 and a minimum value V.sub.S2 of the external voltage V.sub.PV. In FIG. 9A, an external voltage V.sub.PV having a triangular waveform, an average voltage V.sub.PV,LPF obtained by passing the external voltage V.sub.PV through the low pass filter LPF 110, a maximum value (peak sample) V.sub.S2 and a minimum value (under peak sample) V.sub.S1 of the external voltage V.sub.PV obtained by sampling the external voltage V.sub.PV are represented.

(42) In step S300, the V-T converter 130 generates a ramp voltage V.sub.RAMP which changes at a predetermined rate. In this case, the ramp voltage V.sub.RAMP is a signal which serves as a reference for converting a voltage into a time and has a triangular waveform A as illustrated in FIG. 9B.

(43) As described above, when the ramp voltage V.sub.RAMP is generated, in step S400, the V-T converter 130 converts the average voltage V.sub.PV,LPF and the ripple voltage into corresponding time information t.sub.1 and t.sub.2 based on the ramp voltage V.sub.RAMP. To this end, the V-T converter 130 performs a process of comparing the average voltage V.sub.PV,LPF, the maximum value V.sub.S2 and the minimum value V.sub.S1 of the external voltage V.sub.PV with the ramp voltage V.sub.RAMP. A specific process of the V-T converter 130 for performing the voltage-time conversion in step S400 will be mentioned again with reference to FIG. 6. The ramp voltage V.sub.RAMP A, the average voltage V.sub.PV,LPF, and the maximum value V.sub.S2 and the minimum value V.sub.S1 of the external voltage V.sub.PV are illustrated in FIG. 9B and an example of the time information t.sub.2 and t.sub.2 generated by the comparison result is illustrated in FIGS. 9C and 9D. That is, FIG. 9C illustrates a pulse wave VS_TIME having the time information t.sub.1 for the average voltage and FIG. 9D illustrates a pulse wave DV_TIME having the time information t.sub.2 for the ripple voltage.

(44) In step S500, the T-D converter 140 converts the time information t.sub.2 for the ripple voltage into the digital code t.sub.2[n:0]. That is, the T-D converter 140 converts the input time information into a digital code. That is, the time-digital converter receives the pulse wave DV_TIME having the time information t.sub.2 for the ripple voltage from the voltage-time converter 130 and converts the pulse wave into a digital code t.sub.2[n:0]. In FIG. 9E, an example of the digital code t.sub.2[n:0] output from the time-digital converter 140 is illustrated.

(45) In step S600, the time multiplier 150 multiplies the digital code t.sub.2[n:0] and the time information t.sub.1 for the average voltage V.sub.PV,LPF to output a specific voltage value. In this case, the digital code t.sub.2[n:0] determines a magnitude of a current for determining the specific voltage value and the time information t.sub.1 determines a charging time. A specific operation of the time multiplier 150 will be mentioned again in description with reference to FIG. 7. In FIG. 9F, an example of a voltage value V.sub.TM,n obtained by multiplying the digital code t.sub.2[n:0] and the time information t.sub.1 is illustrated.

(46) FIG. 6 is a processing flowchart of a voltage-time converting process. Referring to FIGS. 2 and 6, a voltage-time converting process S400 is as follows:

(47) First, in step S410, the first comparator 133 compares the ramp voltage V.sub.RAMP and the average voltage V.sub.PV,LPF and outputs a result thereof. Thereafter, in step S420, the first D flip-flop 136 synchronizes a result signal of the first comparator 133 with a system clock to output a first pulse wave VS_TIME t.sub.1 having time information for the average voltage V.sub.PV,LPF.

(48) In step S430, the ramp voltage V.sub.RAMP and the ripple voltage are compared. That is, the second comparator 134 compares the ramp voltage V.sub.RAMP and the maximum value V.sub.S2 of the external voltage V.sub.PV and the third comparator 135 compares the ramp voltage V.sub.RAMP and the minimum value V.sub.S1 of the external voltage V.sub.PV.

(49) In step S440, a second D flip-flop synchronizes a comparison result signal of the second and third comparators 134 and 135 with the system clock to output a second pulse wave DV_TIME t.sub.2 having time information for the ripple voltage.

(50) FIG. 7 is a processing flowchart of a time multiplying process. Referring to FIGS. 4 and 7, a time multiplying process S600 is as follows:

(51) First, in step S610, the switch group 153 determines a current amount in the time multiplier 150 by the digital code t.sub.2[n:0] converted in step S500. That is, the switch group 150 turns on the same number of switches as the number of 1 included in the digital code t.sub.2[n:0], to determine the current amount in the time multiplier 150. That is, the switch group 153 determines a magnitude of the current which is transmitted to the first or second capacitor C.sub.1 or C.sub.2 depending on the number of switches which are on. For example, when five switches are on based on the number of 1 included in the digital code t.sub.2[n:0], a magnitude of the current which is transmitted to the first or second capacitor C.sub.1 or C.sub.2 is I.sub.UNIT5.

(52) Further, in step S620, the third switch 151 determines a charging time based on the time information t.sub.1 for the average voltage V.sub.PV,LPF. That is, the charging time is determined by determining the on-time of the third switch 151 by the time information t.sub.1.

(53) Further, the voltage value storing and comparing unit 154 determines capacitor selection information in step S630 and charges the corresponding capacitor based on the selection information in step S640 or S650. For example, when the first capacitor C.sub.1 is selected in step S630, the voltage value storing and comparing unit charges the first capacitor C.sub.1 in step S640 and when the second capacitor C.sub.2 is selected in step S630, the voltage value storing and comparing unit charges the second capacitor C.sub.2 in step S650. In this case, in step S640 or S650, the voltage is charged with the magnitude of the current determined in step S610 during a time determined in step S620. In the meantime, in step S630, the voltage value storing and comparing unit 154 alternately selects the first capacitor C.sub.1 and the second capacitor C.sub.2. The reason is to compare current and past charging values. Further, the voltage value storing and comparing unit 154 compares the voltages across a first capacitor and a second capacitor in step S660 and outputs an up-down signal UP_DOWN based on the result in step S670.

(54) FIG. 8 is a view illustrating equations representing a principle for tracking a maximum power point by a power detection circuit and a method thereof.

(55) First, FIG. 8A illustrates a power equation of a solar cell (PV cell). Referring to FIG. 8A, it is understood that a power P.sub.PV of the solar cell is represented by a product of the average voltage V.sub.PV,LPF and a ripple voltage V.sub.S2-V.sub.S1.

(56) FIG. 8B illustrates Equations 2 and 3 represented by converting the average voltage and the ripple voltage into time information by the voltage-time converter.

(57) FIG. 8C illustrates Equation 4 obtained by multiplying Equations 2 and 3. The value is proportional to Equation 1 which represents the power of the solar cell, which may be established when the capacitance and a period T do not change. Therefore, it is understood that the time information is multiplied to replace the power information.

(58) FIG. 8D is an equation for converting time information of the ripple voltage into a digital code prior to multiplying the time information. That is, the Equation is for calculating a number of stages of time of the digital converter. Further, in FIG. 8D, N indicates the number of delay cells in the digital converter, t.sub.d indicates a delay time of a unit delay cell, ands indicates a quantization error.

(59) FIG. 8E is an equation obtained through the time multiplier of the present disclosure. As seen from the equation of FIG. 8E, it is confirmed that a multiplying function of t.sub.1 and t.sub.2 is successfully performed. Therefore, the proposed circuit can detect the relative magnitude of the power by using only the voltage, which can be expressed through the magnitude of the voltage V.sub.TM.

(60) FIG. 10 is a view illustrating a power graph of a solar cell when illumination is 200 Lux and a simulation result for a power value tracked by the present disclosure. In FIG. 10, a black solid line indicates a power graph of the solar cell and a blue solid line indicates an output of the time multiplier. Referring to FIG. 10, it is understood that the power graph of the solar cell and the voltage V.sub.TM of the power detection circuit show the same tendency. Therefore, according to the present disclosure, it can be confirmed that the amount of power can be estimated by using only the voltages.

(61) FIG. 11 is a performance comparison table obtained by comparing performances of the present disclosure and the related art and is a performance comparison table obtained by comparing VLSI 2013 (a), ISSCC 2015 (b), TCAS-I 2017 (c), and the power detection circuit (d) of the present disclosure with respect to eight criteria of a technology, a converter type, an MPPT type, output dependence, an input range, a throughput power, a tracking efficiency, and P.sub.MPP,CONT.

(62) Referring to FIG. 11, VLSI 2013(a) and ISSCC 2015(b) are capacitively implemented and are dependent on a variation of the output voltage so that it is difficult to precisely track the power.

(63) In the meantime, an inductor type converter is applied to TCAS-I 2017 (d) and MPPT is performed not at an output end of a DC-DC converter, but at an input end so that it is non-dependent on the variation of the output voltage. Therefore, it is possible to more precisely track and detect the power. However, there are disadvantages in that a low tracking efficiency is obtained at a low intensity of light (for example, 200 lux) and power consumption of a circuit for detecting a power is large.

(64) In contrast, according to the present disclosure, there are advantages in that a forward type maximum power point tracking method which is independent on the output is implemented, a high tracking efficiency is obtained, and a power consumption of a circuit for detecting a power is small. Further, according to the present disclosure, as compared with a research paper of TCAS-I 2017 having the same converter type and an independent characteristic, it is understood that the power consumption to detect the power and track the maximum power point of solar cell has been drastically reduced (0.9 W), and it has a high tracking efficiency (97.9%) at low illumination (200 lux) due to a low power consumption and a high power detection accuracy.

(65) In the above-described exemplary system, even though the methods are described as a series of steps or blocks based on a flowchart, the present disclosure is not limited to sequences of the steps and some steps may be performed in different sequences from the steps described above or simultaneously performed.

(66) Further, those skilled in the art may understand that steps illustrated in the flowchart are not exclusive, other steps may be included therein, or one or more steps of the flowchart may be deleted without affecting the scope of the present disclosure.