High-speed clocked comparator and method thereof

Abstract

A clocked comparator includes an upper-side sampling latch configured to output a first decision in accordance with a detection of a sign of an input voltage signal plus an offset voltage at an edge of a clock signal; a lower-side sampling latch configured to output a second decision in accordance with a detection of a sign of the input voltage signal minus the offset voltage at the edge of the clock signal; and a decision-arbitrating latch configured to receive the first decision and the second decision and output a final decision in accordance with whichever one of the first decision and the second decision that is resolved earlier.

Claims

1. A clocked comparator comprising: an upper-side sampling latch configured to output a first decision in accordance with a detection of a sign of an input voltage signal plus an offset voltage at an edge of a clock signal; a lower-side sampling latch configured to output a second decision in accordance with a detection of a sign of the input voltage signal minus the offset voltage at the edge of the clock signal; and a decision-arbitrating latch configured to receive the first decision and the second decision and output a final decision in accordance with whichever one of the first decision and the second decision that is resolved earlier.

2. The clocked comparator of claim 1, wherein the upper-side sampling latch and the lower-side sampling latch are of the same circuit except for a polarity inversion.

3. The clocked comparator of claim 1, wherein the upper-side sampling latch comprises a differential pair, a cross-coupling inverter pair, a plurality of switches, an offset circuit, and a dummy circuit, wherein the differential pair is enabled during a first state of the clock signal, the offset circuit is enabled during the first state of the clock signal and configured to aid one side of the differential pair, said plurality of switches are configured to reset the cross-coupling inverter pair load during a second state of the clock signal, and the dummy circuit is configured to make the upper-side sampling latch balanced.

4. The clocked comparator of claim 1, wherein the decision-arbitrating latch comprises: a first pseudo-differential pair, a second pseudo-differential pair, and a regenerative load, wherein the first pseudo-differential pair is configured to receive the first decision and output a first current to the regenerative load, the second pseudo-differential pair is configured to receive the second decision and output a second current to the regenerative load, and the final decision is a state of the regenerative load.

5. The clocked comparator claim 4, wherein the decision-arbitrating latch further comprises a first inverter pair configured to receive the first decision and output a first auxiliary decision, a second inverter pair configured to receive the second decision and output a second auxiliary decision, a third pseudo-differential pair configured to receive the first auxiliary decision and output a third current to the regenerative load, and a fourth pseudo-differential pair configured to receive the second auxiliary decision and output a fourth current to the regenerative load.

6. A method comprising: receiving an input voltage signal and a clock signal; resolving a first decision using a first sampling latch configured to detect a sign of the input voltage signal plus an offset voltage at an edge of the clock signal; resolving a second decision using a second sampling latch configured to detect a sign of the input voltage signal minus the offset voltage at the edge of the clock signal; resolving a selection signal using a timing comparator configured to identify and indicate which one of the first decision and the second decision is resolved earlier; and selecting one of the first decision and the second decision to be a final decision in accordance with the selection signal.

7. The method of claim 6, wherein the first sampling latch and the second sampling latch are of the same circuit except for a polarity inversion.

8. The method of claim 6, wherein the first sampling latch comprises a differential pair, a cross-coupling inverter pair, a plurality of switches, an offset circuit, and a dummy circuit, wherein the differential pair is enabled during a first state of the clock signal, the offset circuit is enabled during the first state of the clock signal and configured to aid one side of the differential pair, said plurality of switches are configured to reset the cross-coupling inverter pair load during a second state of the clock signal, and the dummy circuit is configured to make the first sampling latch balanced.

9. The method of claim 6, wherein the decision-arbitrating latch comprises: a first pseudo-differential pair, a second pseudo-differential pair, and a regenerative load, wherein the first pseudo-differential pair is configured to receive the first decision and output a first current to the regenerative load, the second pseudo-differential pair is configured to receive the second decision and output a second current to the regenerative load, and the final decision is a state of the regenerative load.

10. The method of claim 6, wherein the decision-arbitrating latch further comprises a first inverter pair configured to receive the first decision and output a first auxiliary decision, a second inverter pair configured to receive the second decision and output a second auxiliary decision, a third pseudo-differential pair configured to receive the first auxiliary decision and output a third current to the regenerative load, and a fourth pseudo-differential pair configured to receive the second auxiliary decision and output a fourth current to the regenerative load.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 shows a transfer characteristic of a prior art clocked comparator.

(2) FIG. 2A shows a conceptual functional block diagram of a clocked comparator in accordance with an embodiment of the present disclosure.

(3) FIG. 2B shows a transfer characteristic of the clocked comparator of FIG. 2A.

(4) FIG. 3 shows a schematic diagram of a sampling latch in accordance with an embodiment of the present invention.

(5) FIG. 4 shows a schematic diagram of a decision-arbitrating latch in accordance with an embodiment of the present invention.

(6) FIG. 5 shows a schematic diagram of an inverter.

(7) FIG. 6 shows a flow diagram of a method in accordance with the present invention.

DETAILED DESCRIPTION OF THIS DISCLOSURE

(8) The present disclosure is directed to clocked comparator. While the specification describes several example embodiments of the disclosure considered favorable modes of practicing the invention, it should be understood that the invention can be implemented in many ways and is not limited to the particular examples described below or to the particular manner in which any features of such examples are implemented. In other instances, well-known details are not shown or described to avoid obscuring aspects of the disclosure.

(9) Persons of ordinary skill in the art understand terms and basic concepts related to microelectronics that are used in this disclosure, such as voltage, current, node, signal, clock, CMOS (complementary metal oxide semiconductor), NMOS (N-channel metal oxide semiconductor) transistor, PMOS (N-channel metal oxide semiconductor) transistor, differential pair, pseudo-differential pair, switch, latch, inverter, clock, frequency, logical signal, return-to-zero, non-return-to-zero, pull up, pull down and differential signal. Terms like these are used in a context of microelectronics, and the associated concepts are apparent to those of ordinary skills in the art and thus will not be explained in detail here. Those of ordinary skill in the art can also recognize a symbol of a NMOS transistor and a symbol of a PMOS transistor and identify the source, the gate, and the drain terminals thereof. Those of ordinary skills in the art also understand units such as m (micron), nm (nanometer), and ps (picosecond).

(10) This present disclosure is disclosed from an engineering perspective. For instance, X is equal to Y means a difference between X and Y is smaller than a specified engineering tolerance; X is much smaller than Y means X divided by Y is smaller than an engineering tolerance; and X is zero means X is smaller than a specified engineering tolerance.

(11) In this disclosure, a signal is either a voltage or a current that represents information.

(12) A logical signal is a voltage signal of two states: a high state and a low state. A logical signal is said to be in the high (low) state when a level of said logical signal is above (below) a certain level or trip point pertaining to said logical signal. Stating (the logical signal) X is high, is stating it in a context of logical signal and what is meant is: (the logical signal) X is in the high state. Stating (the logical signal) X is low, is stating it in a context of logical signal and what is meant is: (the logical signal) X is in the low state. The high state is also known as the 1 state, and the low state is also known as the 0 state. Stating that (the logical signal) X is 1, is stating it in a context of logical signal and what is meant is: (the logical signal) X is in the high state. Likewise, stating that (the logical signal) X is 0, is stating it in a context of logical signal and what is meant is: (the logical signal) X is in the low state.

(13) A clock signal (or simply a clock) is a logical signal that cyclically toggles between a high state and a low state.

(14) Throughout this disclosure, V.sub.DD denotes a power supply node. For convenience, V.sub.DD can also refer to a power supply voltage provided at the power supply node. That is, V.sub.DD is 0.9V means a power supply voltage at the power supply node V.sub.DD is 0.9V. By way of example but not limitation, throughout this disclosure a circuit is fabricated using a 28 nm CMOS (complementary metal oxide semiconductor) process and V.sub.DD is 0.9V.

(15) Throughout this disclosure, a differential signaling scheme is used, wherein a voltage signal comprises two voltages denoted with suffixes + and , respectively, attached in subscript, and a value of the voltage signal is represented by a difference between said two voltages. For instance, V.sub.X (D.sub.1, D.sub.2, D.sub.1, D.sub.2) comprises V.sub.X+ (D.sub.1+, D.sub.2+, D.sub.1+, D.sub.2+) and V.sub.X(D.sub.1, D.sub.2, D.sub.1, D.sub.2), and a value of V.sub.X (D.sub.1, D.sub.2, D.sub.1, D.sub.2) is represented by a difference between V.sub.X+ (D.sub.1+, D.sub.2+, D.sub.1+, D.sub.2+) and V.sub.X (D.sub.1, D.sub.2, D.sub.1, D.sub.2). Likewise, a current signal comprises two currents denoted with suffixes + and , respectively, attached in subscript. For instance, I.sub.x (I.sub.1, I.sub.2, I.sub.1, I.sub.2) comprises I.sub.X+ (I.sub.1+, I.sub.2+, I.sub.1+, I.sub.2+) and I.sub.X (I.sub.1, I.sub.2, I.sub.1, I.sub.2) and a value of I.sub.X(I.sub.1, I.sub.2, I.sub.1, I.sub.2) is represented by a difference between I.sub.X+ (I.sub.1+, I.sub.2+, I.sub.1+, I.sub.2+) and I.sub.X (I.sub.1, I.sub.2, I.sub.1, I.sub.2).

(16) This present disclosure is based on exploiting a characteristic of metastability (of clocked comparator) to virtually eliminate metastability. A conceptual functional block diagram of a clocked comparator 200 in accordance with an embodiment of the present disclosure is depicted in FIG. 2A. Clocked comparator 200 comprises: an upper-side sampling latch 210 configured to receive an input voltage V.sub.X and output a first decision D.sub.1 in accordance with a clock signal V.sub.CK; a lower-side sampling latch 220 configured to receive the input voltage V.sub.X and output a second decision D.sub.2 in accordance with the clock signal V.sub.CK; and a decision-arbitrating latch 230 configured to receive the first decision D.sub.1 and a second decision D.sub.2 and output a final decision D.sub.F.

(17) The upper-side sampling latch 210 comprises a first offset circuit 211 and a first clocked arbiter 212. The first offset circuit 211 embodies the following function:
V.sub.X1=V.sub.X+V.sub.OS,(1)

(18) where V.sub.OS is an offset voltage that is greater than a threshold voltage V.sub.M determined by a metastability condition of the first clocked arbiter 212, and V.sub.X, is an upshifted voltage. The first clocked arbiter 212 embodies the following function:

(19) $\begin{array}{cc}{D}_1=\{\begin{array}{cc}1& \mathrm{if}{V}_{X1}>0\mathrm{at}a\mathrm{sampling}\mathrm{instant}\mathrm{defined}\mathrm{by}{V}_{\mathrm{CK}}\\ 0& \mathrm{otherwise}\end{array}.& \left(2\right)\end{array}$

(20) Therefore, the upper-side sampling latched 210 embodies a function that can be mathematically modeled by the following equation:

(21) $\begin{array}{cc}{D}_1=\{\begin{array}{cc}1& \mathrm{if}\left(V_X+V_{\mathrm{OS}}\right)>0\mathrm{at}a\mathrm{sampling}\mathrm{instant}\mathrm{defined}\mathrm{by}{V}_{\mathrm{CK}}\\ 0& \mathrm{otherwise}\end{array}.& \left(3\right)\end{array}$

(22) The lower-side sampling latch 220 comprises a second offset circuit 221 and a second clocked arbiter 222. The second offset circuit 221 embodies the following function:
V.sub.X2=V.sub.XV.sub.OS(4)

(23) where V.sub.X2 is a downshifted voltage. The second clocked arbiter 222 embodies the following function:

(24) $\begin{array}{cc}{D}_2=\{\begin{array}{cc}1& \mathrm{if}{V}_{X2}>0\mathrm{at}a\mathrm{sampling}\mathrm{instant}\mathrm{defined}\mathrm{by}{V}_{\mathrm{CK}}\\ 0& \mathrm{otherwise}\end{array}.& \left(5\right)\end{array}$

(25) Therefore, the lower-side sampling latched 220 embodies a function that can be mathematically modeled by the following equation:

(26) $\begin{array}{cc}{D}_2=\{\begin{array}{cc}1& \mathrm{if}\left(V_X-V_{\mathrm{OS}}\right)>0\mathrm{at}a\mathrm{sampling}\mathrm{instant}\mathrm{defined}\mathrm{by}{V}_{\mathrm{CK}}\\ 0& \mathrm{otherwise}\end{array}.& \left(6\right)\end{array}$

(27) Exemplary transfer characteristics between V.sub.X and (which is a time needed to resolve a decision for V.sub.X) for the two sampling latches 210 and 220 are shown in FIG. 2B. Here, we assume the first clocked arbiter 212 and the second clocked arbiter 222 are embodied by the same clocked comparator that has the transfer characteristic shown in FIG. 1. As shown, the transfer characteristics in FIG. 2B are the same as that in FIG. 1 except that the upper-side sampling latches 210 (whose transfer characteristics are shown in a solid line) has an offset of V.sub.OS in the horizontal axis (i.e. shifted to the left by V.sub.OS), while the lower-side sampling latch 220 (whose transfer characteristics are shown in a dashed line) has an offset of V.sub.OS in the horizontal axis (i.e. shifted to the right by V.sub.OS). For the upper-side sampling latch 210, D.sub.1 is 1 when V.sub.X is greater than V.sub.OS and 0 otherwise. However, the upper-side sampling latch 210 will encounter metastability (i.e. fail to resolve within .sub.M) when V.sub.X is between V.sub.MV.sub.OS and V.sub.MV.sub.OS, as |V.sub.x+V.sub.OS| is smaller than V.sub.M. For the lower-side sampling latch 220, D.sub.2 is 1 when V.sub.X is greater than V.sub.OS and 0 otherwise. However, the lower-side sampling latch 220 will encounter metastability (i.e. fail to resolve within .sub.M) when V.sub.X is between V.sub.M+V.sub.OS and V.sub.M+V.sub.OS, as |V.sub.XV.sub.OS| is smaller than V.sub.M. A table of values of D.sub.1 and D.sub.2 along with a correct decision of V.sub.X versus V.sub.X is shown below.

(28) TABLE-US-00001 Correct V.sub.X decision D.sub.1 D.sub.2 below V.sub.M V.sub.OS 0 0 0 between V.sub.M V.sub.OS and 0 metastable 0 V.sub.M V.sub.OS between V.sub.M V.sub.OS and 0 0 1 but resolved 0 and resolved later than D.sub.2 earlier than D.sub.1 between 0 and V.sub.M + V.sub.OS 1 1 and resolved 0 but resolved earlier than D.sub.2 later than D.sub.1 between V.sub.M + V.sub.OS and 1 1 metastable V.sub.M + V.sub.OS above V.sub.M + V.sub.OS 1 1 1

(29) The correct decision is 1 if V.sub.X>0 and 0 if V.sub.X<0. From the table, whichever one of the two decisions D.sub.1 and D.sub.2 that gets resolved earlier will be the correct decision, and the metastability thus can be virtually eliminated for the correct decision.

(30) Now refer to FIG. 2A. The decision-arbitrating latch 230 embodies the following function:

(31) $\begin{array}{cc}{D}_F=\{\begin{array}{cc}{D}_1& \mathrm{if}{D}_1\mathrm{is}\mathrm{resolved}\mathrm{earlier}\mathrm{than}{D}_2\\ D_2& \mathrm{otherwise}\end{array}.& \left(7\right)\end{array}$

(32) A schematic diagram of a sampling latch 300 that can be used to embody the upper-side sampling latch 210 is shown in FIG. 3. Sampling latch 300 is in a reset state when V.sub.CK is low and is in a resolution state when V.sub.CK is high. Sampling latch 300 comprises: NMOS transistors 309, 311, 312, 351, 352, 361, 362, 331, and 332, and PMOS transistors 321, 322, 333, 334, 341, and 342. NMOS transistor 309 embodies a switch configured to enable a comparison between V.sub.X+ and V.sub.X when V.sub.CK is high; NMOS transistors 311 and 312 embody a differential pair 310 configured to receive V.sub.X+ and V.sub.X and draw currents I.sub.X and I.sub.X+ from nodes 301 and 302, respectively to embody a comparison between V.sub.X+ and V.sub.X; NMOS transistors 331 and 332 along with PMOS transistors 333 and 334 form a cross-coupling inverter pair 330 configured to establish D.sub.1 and D.sub.1+ in accordance with currents drawn from nodes 301 and 302; PMOS transistors 321, 322, 341, and 342 embody pull-up switches configured to pull up nodes 301, 302, 303, and 304, respectively, to V.sub.DD and effectively reset a state of the cross-coupling inverter pair 330 when V.sub.CK is low; NMOS transistor 351 and 352 embody an offset circuit 350 configured to draw an offset current I.sub.OS from node 301 and thus give V.sub.X+ an advantage over V.sub.X during a comparison when V.sub.CK is high; and NMOS transistors 361 and 362 embody a dummy circuit 360 configured to make the overall circuitry more balanced. Upon a rising edge of the clock signal V.sub.CK, node 301 will be pulled down regardless of a value of V.sub.X+ thanks to the offset current I.sub.OS, while node 302 might be pulled down, depending on a value of V.sub.X. If node 301 (302) is pulled down faster than node 302 (301), D.sub.1(D.sub.1+) will be latched to 0 while D.sub.1+(D.sub.1) will be latched to 1, thanks to the cross-coupling inverter pair 330.

(33) Except for the offset circuit 350 and the dummy circuit 360, sampling latch 300 is widely known in the prior art as a strong-arm latch and thus not explained in detail here. That the offset circuit 350 can give V.sub.X+ an advantage over V.sub.X during a comparison is understood to those of ordinary skill in the art and thus not described in detail here. The function of the offset circuit 211 and the offset voltage V.sub.OS in FIG. 2A are implied by the advantage that V.sub.X+ has due to the offset current I.sub.OS provided by the offset circuit 350. That the dummy circuit 360 can make the overall circuitry more balanced is also understood to those of ordinary skill in the art and thus not explained in detail here.

(34) The offset current I.sub.OS from the offset circuit 350 must be sufficiently large that when V.sub.X+ is equal to V.sub.X, D.sub.1 can be latched to 0 within the maximum time allowed.

(35) By way of example, but not limitation, widths/lengths of NMOS transistors 309, 311, 312, 351, 352, 361, 362, 331, and 332 are: 4 m/30 nm, 4 m/30 nm, 4 m/30 nm, 1 m/30 nm, 1 m/30 nm, 1 m/30 nm, 1 m/30 nm, 3 m/30 nm, and 3 m/30 nm, respectively; and widths/lengths of PMOS transistors 321, 322, 333, 334, 341, and 342 are: 2 m/30 nm, 2 m/30 nm, 3 m/30 nm, 3 m/30 nm, 3 m/30 nm, and 3 m/30 nm, respectively.

(36) Sampling latch 300 can be used to embody the lower-side sampling latch 220 by replacing V.sub.X+, V.sub.X, D.sub.1+, and D.sub.1 with V.sub.X, V.sub.X+, D.sub.2, and D.sub.2+, respectively. In this case, the offset circuit 350 can give V.sub.X an advantage over V.sub.X+ during a comparison. Note the upper-side sampling latch 210 is of the same circuit as the lower-side sampling latch 220 except for a polarity inversion in both the input and the output.

(37) A schematic diagram of a decision-arbitrating latch 400 that can be used to embody decision-arbitrating latch 230 is shown in FIG. 4. Decision-arbitrating latch 400 comprises: a 1.sup.st inverter pair 450 comprising inverters 451 and 452 configured to receive D.sub.1+ and D.sub.1_and output D.sub.1 and D.sub.1+, respectively, wherein D.sub.1+ and D.sub.1 jointly embody a first auxiliary decision D.sub.1; a 2.sup.nd inverter pair 460 comprising inverters 461 and 462 configured to receive D.sub.2+ and D.sub.2 and output D.sub.2 and D.sub.2+, respectively, wherein D.sub.2+ and D.sub.2 jointly embody a second auxiliary decision D.sub.2; a 1.sup.st pseudo-differential pair 410 comprising PMOS transistors 411 and 412 configured to receive D.sub.1+ and D.sub.1 and supply currents I.sub.1 and I.sub.1+ to nodes 401 and 402, respectively; a 2.sup.nd pseudo-differential pair 420 comprising PMOS transistors 421 and 422 configured to receive D.sub.2+ and D.sub.2 and supply currents I.sub.2 and I.sub.2+ to nodes 401 and 402, respectively; a 3.sup.rd pseudo-differential pair 430 comprising NMOS transistors 431 and 432 configured to receive D.sub.1+ and D.sub.1 and draw currents I.sub.1+ and I.sub.1 from nodes 401 and 402, respectively; a 4.sup.th pseudo-differential pair 440 comprising NMOS transistors 441 and 442 configured to receive D.sub.2+ and D.sub.2 and draw currents I.sub.2+ and I.sub.2 from nodes 401 and 402, respectively; and a cross-coupling inverter pair 480 comprising inverters 481 and 482 configured to embody a regenerative load across nodes 401 and 402.

(38) A schematic diagram of an inverter 500 that can be instantiated to embody inverters 451, 452, 461, 462, 481, and 482 is shown in FIG. 5. Inverter 500 comprises a NMOS transistor MN and a PMOS transistor MP and is well understood by those of ordinary skill in the art and thus not explained in detail here.

(39) When V.sub.CK is low, the upper-side sampling latch 210 and the lower-side sampling latch 220 are reset, D.sub.1+, D.sub.1, D.sub.2+ and D.sub.2 are all pulled up to V.sub.DD (see FIG. 3); consequently, D.sub.1+, D.sub.1, D.sub.2+ and D.sub.2 are all pulled down to ground by inverters 452, 451, 462, and 461, respectively. As a result, PMOS transistors 411, 412, 421, and 422 and NMOS transistors 431, 432, 441, and 442 are all shut off and the cross-coupling inverter pair 480 is latched to a present state.

(40) Upon a rising edge of V.sub.CK, the upper-side sampling latch 210 and the lower-side sampling latch 220 are enabled and D.sub.1 and D.sub.2 are being resolved. There are two possibilities for D.sub.1 as summarized by the following table:

(41) TABLE-US-00002 D.sub.1 is resolved to be 1 D.sub.1 is resolved to be 0 D.sub.1+ remains high D.sub.1+ drops to ground D.sub.1 drops to ground D.sub.1 remains high D.sub.1 remains low D.sub.1 rises to VDD D.sub.1+ rises to V.sub.DD D.sub.1+ remains low PMOS transistor 412 is PMOS transistor 411 is pulling up D.sub.F+ (via I.sub.1+) pulling up D.sub.F (via I.sub.1) NMOS transistor 431 is pulling NMOS transistor 432 is pulling down D.sub.F (via I.sub.1+) down D.sub.F+ (via I.sub.1) PMOS transistor 411 and NMOS PMOS transistor 412 and NMOS transistor 432 remain shut off transistor 431 remain shut off

(42) There are two possibilities for D.sub.2 as summarized by the following table:

(43) TABLE-US-00003 D.sub.2 is resolved to be 1 D.sub.2 is resolved to be 0 D.sub.2+ remains high D.sub.2+ drops to ground D.sub.2 drops to ground D.sub.2 remains high D.sub.2 remains low D.sub.2 rises to V.sub.DD D.sub.2+ rises to V.sub.DD D.sub.2+ remains low PMOS transistor 422 is PMOS transistor 421 is pulling up D.sub.F+ (via I.sub.2+) pulling up D.sub.F (via I.sub.2) NMOS transistor 441 is pulling NMOS transistor 442 is pulling down D.sub.F (via I.sub.2+) down D.sub.F+ (via I.sub.2) PMOS transistor 421 and NMOS PMOS transistor 422 and NMOS transistor 442 remain shut off transistor 441 remain shut off

(44) If both D.sub.1 and D.sub.2 are resolved to be 1, D.sub.F+ will be pulled up to V.sub.DD by both PMOS transistors 412 and 422 and D.sub.F will be pulled down to ground by both NMOS transistors 431 and 441, and the regenerative load 480 will help to latch the state. If both D.sub.1 and D.sub.2 are resolved to be 0, D.sub.F will be pulled up to V.sub.DD by both PMOS transistors 411 and 421 and D.sub.F+ will be pulled down to ground by both NMOS transistors 432 and 442, and the regenerative load 480 will help to latch the state. As shown in FIG. 2B, if V.sub.OS is larger than V.sub.M, it is impossible that both D.sub.1 and D.sub.2 can be metastable. If either one of D.sub.1 and D.sub.2 is in a metastability (i.e. fails to resolve in a timely manner), the other one will not be metastable and can establish the final decision D.sub.F on its own. If D.sub.1 and D.sub.2 are resolved to different values, a racing condition occurs, wherein one of PMOS transistors 411 and 421 is trying to pull up D.sub.F and one of NMOS transistors 431 and 441 is trying to pull down D.sub.F, and at the same time one of PMOS transistors 412 and 422 is trying to pull up D.sub.F+ and one of NMOS transistors 432 and 442 is trying to pull down D.sub.F+. In this case, the one (between D.sub.1 and D.sub.2) that gets resolved earlier will have a head start and dictate the final decision, due to a latch function provided by the regenerative load 480.

(45) For instance, if D.sub.1 (D.sub.2) is resolved to be 1, D.sub.2 (D.sub.1) is resolved to be 0, but D.sub.1 (D.sub.2) is resolved earlier than D.sub.2 (D.sub.1), then PMOS transistor 412 (422) will start pulling up D.sub.F+ before NMOS transistor 442 (432) starts pulling down D.sub.F+, and NMOS transistor 431 (441) will start pulling down D.sub.F before PMOS transistor 421 (411) starts pulling up D.sub.F; as a result, D.sub.F+ and D.sub.F will be latched to 1 and 0, respectively, thanks to the regenerative load 480. On the other hand, if D.sub.1 (D.sub.2) is resolved to be 0, D.sub.2 (D.sub.1) is resolved to be 1, but D.sub.1 (D.sub.2) is resolved earlier than D.sub.2 (D.sub.1), then PMOS transistor 411 (421) will start pulling up D.sub.F before NMOS transistor 441 (431) starts pulling down D.sub.F, and NMOS transistor 432 (442) will start pulling down D.sub.F+ before PMOS transistor 422 (412) starts pulling up D.sub.F+; as a result, D.sub.F+ and D.sub.F will be latched to 0 and 1, respectively, thanks to the regenerative load 480.

(46) By way of example, but not limitation: widths/lengths of NMOS transistor 431, 432, 441, 442 are all 2 m/30 nm; widths/lengths of PMOS transistor 411, 412, 421, 422 are all 3 m/30 nm; and for inverters 451, 452, 461, 462, 481, and 482, width/length of PMOS transistor MP therein is 1.5 m/30 nm and width/length of NMOS transistor MN therein is 1 m/30 nm.

(47) Note that the decision-arbitrating latch 400 may still work if inverters 451, 452, 461, 462 and NMOS transistors 431, 432, 441, 442 are removed. For instance, if D.sub.F+ is pulled up by PMOS transistor 412 and/or PMOS transistor 422, D.sub.F can still be pulled down by inverter 482; if D.sub.F is pulled up by PMOS transistor 411 and/or PMOS transistor 421, D.sub.F+ can still be pulled down by inverter 481. In this case, however, the decision-arbitrating latch 400 will likely be slower due to having no direct pull-down currents (I.sub.1+, I.sub.1, I.sub.2+, I.sub.2) and must fully rely on the regenerative load 480 to enforce the pull-down after the pull-up happens.

(48) As shown in a flow diagram depicted in FIG. 6, a method in accordance with an embodiment of the present disclosure comprises: (step 610) receiving an input voltage signal and a clock signal; (step 620) resolving a first decision using a first sampling latch configured to detect a sign of the input voltage signal plus an offset voltage at an edge of the clock signal; (step 630) resolving a second decision using a second sampling latch configured to detect a sign of the input voltage signal minus the offset voltage at the edge of the clock signal; (step 640) and resolving a final decision using a decision-arbitrating latch configured to receive the first decision and the second decision and output the final decision in accordance with whichever one of the first decision and the second decision that is resolved earlier.

(49) This present disclosure can be very useful in a high-speed serial link receiver, wherein a decision must be resolved within a very short period of time.

(50) Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the disclosure. Accordingly, the above disclosure should not be construed as limited only by the metes and bounds of the appended claims.