Abstract
A method of manufacturing first and second component carriers includes: i) providing a separation component comprising a first separation surface and a second separation surface being opposed to the first separation surface, ii) coupling a first base structure having a first cavity with the first separation surface, iii) coupling a second base structure having a second cavity with the second separation surface, iv) placing a first electronic component in the first cavity, v) connecting the first base structure with the first electronic component to form the first component carrier, vi) placing a second electronic component in the second cavity, vii) connecting the second base structure with the second electronic component to form the second component carrier, viii) separating the first component carrier from the first separation surface of the separation component, and ix) separating the second component carrier from the second separation surface of the separation component.
Claims
1. A method of manufacturing a first component carrier and a second component carrier, the method comprising: providing a separation component comprising a first separation surface and a second separation surface being opposed to the first separation surface; coupling a first base structure having a first cavity with the first separation surface; coupling a second base structure having a second cavity with the second separation surface; placing a first electronic component in the first cavity; connecting the first base structure with the first electronic component to form the first component carrier; placing a second electronic component in the second cavity; connecting the second base structure with the second electronic component to form the second component carrier; separating the first component carrier from the first separation surface of the separation component; and separating the second component carrier from the second separation surface of the separation component.
2. The method according to claim 1, further comprising: forming, in particular laminating, a first electrically insulating layer on the first separation surface before coupling the first base structure with the first separation surface, and afterwards attaching the first base structure on the first electrically insulating layer; and forming, in particular laminating, a second electrically insulating layer on the second separation surface before coupling the second base structure with the second separation surface, and afterwards attaching the second base structure on the second electrically insulating layer.
3. The method according to claim 2, wherein the first electrically insulating layer and the second electrically insulating layer comprise or consist of prepreg material, in particular a low Young modulus material.
4. The method according to claim 2, wherein the first electrically insulating layer and the second electrically insulating layer are formed of a low Young modulus material, in particular a Young modulus of less than 10 GPa.
5. The method according to claim 1, wherein placing the first electronic component in the first cavity is done after coupling the first base structure with the first separation surface; wherein placing the second electronic component in the second cavity is done after coupling the second base structure with the second separation surface.
6. The method according to claim 2, wherein placing the first electronic component in the first cavity is done before coupling the first base structure with the first separation surface; and wherein placing the second electronic component in the second cavity is done before coupling the second base structure with the second separation surface; the method further comprising: attaching the first base structure on the first electrically insulating layer such that a main surface of the first electronic component is directly attached to the first electrically insulating layer; and attaching the second base structure on the second electrically insulating layer such that a main surface of the second electronic component is directly attached to the second electrically insulating layer.
7. The method according to claim 6, further comprising: pressing the first electronic component in the first electrically insulating layer so that the first electronic component becomes at least partially embedded by the first electrically insulating layer; and/or pressing the second electronic component in the second electrically insulating layer so that the second electronic component becomes at least partially embedded by the second electrically insulating layer.
8. The method according to claim 1, further comprising: laminating a first further electrically insulating layer structure on the first base structure or the first component carrier, in particular such that the first electronic component is at least partially embedded with the first further electrically insulating layer structure; and/or laminating a second further electrically insulating layer structure on the second base structure or the second component carrier, in particular such that the second electronic component is at least partially embedded with the second further electrically insulating layer structure; forming a first electrically conductive interconnection, in particular a first via, more in particular through the first further electrically insulating layer structure, in order to electrically contact a first electric contact of the first electronic component; and/or forming a second electrically conductive interconnection, in particular a second via, more in particular through the second further electrically insulating layer structure, in order to electrically contact a first electric contact of the second electronic component.
9. The method according to claim 8, further comprising: forming a second electric contact, in particular formed as a solder ball, on a main surface of the first component carrier, and electrically connecting the second electric contact through the first electrically conductive interconnection with the first electric contact of the first electronic component, wherein the second electric contact is larger than the first electric contact of the first electronic component so that a first redistribution structure is provided; and/or forming a further second electric contact, in particular formed as a solder ball, on a further main surface of the second component carrier, and electrically connecting the further second electric contact through the second electrically conductive interconnection with the second electric contact of the second electronic component, wherein the further second electric contact is larger than the further second electric contact of the second electronic component so that a second redistribution structure is provided.
10. The method according to claim 9, wherein the first electronic component is sandwiched between the first electrically insulating layer, in particular at least partially embedded in the first electrically insulating layer, and the first redistribution structure; and/or wherein the second electronic component is sandwiched between the second electrically insulating layer, in particular at least partially embedded in the second electrically insulating layer, and the second redistribution structure.
11. The method according to claim 2, wherein separating comprises: detaching the first component carrier including the first electrically insulating layer from the separation component; and/or detaching the second component carrier including the second electrically insulating layer from the separation component.
12. The method according to claim 2, wherein attaching the first base structure on top of the first electrically insulating layer further comprises: piercing at least one first electrically conductive pillar structure of the first base structure into the first electrically insulating layer; and/or wherein attaching the second base structure on top of the second electrically insulating layer further comprises: piercing at least one second electrically conductive pillar structure of the second base structure into the second electrically insulating layer.
13. The method according to claim 2, wherein the separation component is fully surrounded by material of the first electrically insulating layer and the second electrically insulating layer.
14. The method according to claim 1, wherein the separation component is a detachment core, in particular a core structure sandwiched between two detach copper foils.
15. The method according to claim 1, wherein the first component carrier and/or the second component carrier is a coreless component carrier.
16. The method according to claim 1, wherein the first electronic component is placed on a first temporary carrier of the first base structure, wherein the method further comprises: removing the first temporary carrier after coupling the first base structure with the first separation surface; and/or wherein the second electronic component is placed on a second temporary carrier of the second base structure, wherein the method further comprises: removing the second temporary carrier after coupling the second base structure with the second separation surface.
17. A component carrier, comprising: a layer stack comprising electrically conductive layer structures and electrically insulating layer structures, wherein at least one electrically insulating layer structure is a low Young modulus layer structure formed of a low Young modulus material, in particular with a Young modulus of less than 10 GPa, and wherein the layer stack is at least partially formed as a redistribution structure; an electronic component embedded in a cavity of the layer stack and electrically connected with the redistribution structure such that a first electric contact of the electronic component is transferred via the redistribution structure to a second electric contact at a main surface of the layer stack, wherein the second electric contact is larger than the first electric contact; and wherein the electronic component is arranged between, in particular directly between, the low Young modulus layer structure and the redistribution structure.
18. The component carrier according to claim 17, comprising at least one of the following features: wherein the low Young modulus layer structure comprises or consists of prepreg material; wherein the electronic component is at least partially embedded in the low Young modulus layer structure; wherein the layer stack comprises a further electrically insulating layer structure arranged at another main surface of the electronic component being opposite to the main surface of the electronic component in contact with the Young modulus layer structure, and wherein the redistribution structure comprises at least one electrically conductive interconnection which extends through the further electrically insulating layer structure and electrically connects the first electric contact of the electronic component with the second electric component, in particular wherein the second electronic component is formed as a solder-ball; the component carrier further comprising: a heat distribution layer formed on the low Young modulus layer and facing the main surface of the electronic component, in particular wherein the heat distribution layer is electrically and thermally connected with the electrically conductive interconnection such that the heat distribution layer and the electrically conductive interconnection at least partially surround the cavity; wherein at least one of the electrically insulating layer structures comprises at least one of the group consisting of resin, in particular epoxy resin or Bismaleimide-Triazine resin, cyanate ester, polyphenylene derivate, glass, in particular glass fibers, multi-layer glass, glass-like materials, prepreg material, in particular FR-4 or FR-5, polyimide, polyamide, liquid crystal polymer, epoxy-based Build-Up Film, polytetrafluoroethylene, a ceramic, and a metal oxide.
19. A semi-finished product, comprising: a separation component having a first separation surface and a second separation surface, wherein the second separation surface is opposed to the first separation surface; a first component carrier or first base structure comprising a first electronic component placed in a cavity of the first component carrier or first base structure, wherein the first component carrier or first base structure is coupled with the first separation surface; a second component carrier or second base structure comprising a second electronic component placed in a cavity of the second component carrier or second base structure; wherein the second component carrier or second base structure is coupled with the second separation surface; a first electrically insulating layer formed between the first separation surface and the first component carrier or first base structure such that the first component carrier or first base structure is attached to the first electrically insulating layer; and a second electrically insulating layer formed between the second separation surface and the second component carrier or second base structure such that the second component carrier or first base structure is attached to the second electrically insulating layer.
20. The semi-finished product according to claim 19, comprising at least one of the following features: wherein the first electrically insulating layer and the second electrically insulating layer are low Young modulus layer structures formed of a low Young modulus material, in particular with a Young modulus of less than 10 GPa; wherein the low Young modulus layer structure comprises or consists of prepreg material; wherein the first electronic component is at least partially embedded in the first electrically insulating layer; and wherein the second electronic component is at least partially embedded in the second electrically insulating layer; wherein the first component carrier comprises a first redistribution structure, and wherein the first electronic component is sandwiched between the first electrically insulating layer and the first redistribution structure; and wherein the second component carrier comprises a second redistribution structure, and wherein the second electronic component is sandwiched between the second electrically insulating layer and the second redistribution structure.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0065] FIGS. 1A, 1B, 1C, 1D, 1E, 1F, 1G, 1H and 1I illustrate exemplary embodiments of a method of manufacturing component carriers according to embodiments of the invention.
[0066] FIGS. 2A, 2B, 2C and 2D illustrate a prior art process (see description above).
[0067] FIGS. 3A, 3B and 3C illustrate specific advantageous effects according to exemplary embodiments of the invention.
[0068] FIGS. 4A, 4B, 4C and 4D illustrate exemplary embodiments of component carriers according to the invention.
[0069] FIGS. 5A, 5B, 5C, 5D, 5E, 5F, 5G, 5H, 5I, 5J and 5K illustrate exemplary embodiments of the method of manufacturing component carriers according to a further embodiment of the invention.
[0070] FIGS. 6A, 6B, 6C, 6D, 6E, 6F, 6G, 6H, 6I, 6J and 6K illustrate exemplary embodiments of the method of manufacturing component carriers according to a further embodiment of the invention.
[0071] FIGS. 7A, 7B, 7C, 7D, 7E, 7F, 7G, 7H and 7I illustrate exemplary embodiments of the method of manufacturing component carriers according to a further embodiment of the invention.
[0072] FIGS. 8A, 8B and 8C illustrate exemplary embodiments of a method of manufacturing component carriers according to a further embodiment of the invention.
[0073] FIGS. 9A, 9B, 9C, 9D, 9E, 9F, 9G, 9H and 9I illustrate exemplary embodiments of a method of manufacturing component carriers according to a further embodiment of the invention.
[0074] FIGS. 10A, 10B, 10C, 10D, 10E, 10F, 10G, 10H, 10I and 10J illustrate exemplary embodiments of a method of manufacturing component carriers according to a further embodiment of the invention.
DETAILED DESCRIPTION OF ILLUSTRATED EMBODIMENTS
[0075] The aspects defined above and further aspects of the invention are apparent from the examples of embodiment to be described hereinafter and are explained with reference to these examples of embodiment.
[0076] The illustrations in the drawings are schematically presented. In different drawings, similar or identical elements are provided with the same reference signs.
[0077] Before, referring to the drawings, exemplary embodiments will be described in further detail, some basic considerations will be summarized based on which exemplary embodiments of the invention have been developed.
[0078] According to an exemplary embodiment of the invention, the following steps are included in the manufacturing process: i) providing a low cost detach core (DCF) sandwiched between two prepreg (PPG) layers, ii) performing a lay-up using two base structures (comprising each an electronic component on a temporary carrier), iii) hot pressing (laminating) and trimming (cutting edges), iv) de-taping the temporary carrier and performing a first step of layer build-up, v) performing a second step of layer build-up, vi) providing surface finish and solder resist, vii) again trimming and then detaching the component carriers from the DCF, and viii) attaching a heat distribution layer at the PPG layer and provide solder balls to the redistribution structure.
[0079] According to an exemplary embodiment of the invention, a fan-out wafer level packaging (FOWLP) is one of the latest packaging trends in microelectronics. It has a high potential for significant package miniaturization concerning package volume but also its thickness. Technological core of FOWLP is the formation of a reconfigured molded wafer combined with a thin film redistribution layer to yield an SMD-compatible package. Main advantages of FOWLP are the substrate-less package, low thermal resistance, improved RF performance due to shorter interconnects together with direct IC connection by thin film metallization instead of wire bonds or flip chip bumps and lower parasitic effects. Especially the inductance of FOWLP is much lower compared to FC-BGA packages. In addition, the redistribution layer can also provide embedded passives as well as antenna structures using a multi-layer structure. It can be used for multi-chip packages for system-in-package (SiP) and heterogeneous integration. For higher productivity and resulting lower cost, larger mold embedding form factors are forecast for the near future. Besides increasing wafer diameter, an alternative option would be moving to panel sizes leading to fan-out panel level packaging (FOPLP). Panel sizes could range from 1824 (a PCB manufacturing standard) to even larger sizes. However, a FO-PLP (fan-out panel level packaging) substrate embedding the functional chip needs an efficient thermal management to facilitate smooth chip operation. An object of the invention is hence to provide a high yield production method for single side build FO-PLP products with thin core (i.e. component carriers) using DCF (detach copper foil) as a separation component. The FO-PLP products further have an enhanced heat dissipation capacity by surrounding the cavity with the embedded component with heat spread metal (e.g. an electrically conductive interconnection) and a heat dissipation layer (e.g. a heat distribution layer) on the top layer. The heat spread metal and the heat dissipation layer are hereby interconnected by one or more vias.
[0080] According to an exemplary embodiment of the invention, in particular when placing the electronic components in the cavities after the base structures have been coupled with the separation component, the following advantages may be provided: i) solving the tape (temporary carrier) twisty issue and make sure it is flat during front side encapsulation, especially for a large component-package ratio, ii) prevent the movement or deformation during lamination, iii) flexible application and more efficiency on first lamination or hot press; two panels (component carriers) proceed at one time is possible, iv) warpage performance becomes better during and after first lamination, v) applying the thermal released adhesive may help to reduce the risk of leaving residuals, and vi) making it more feasible to remove the temporary adhesive layer or carrier (temporary carrier or separation component) with a thermal release adhesive.
[0081] According to an exemplary embodiment of the invention, the following steps are performed: i) laminating a double side adhesive (adhesive material) on two sides of a separation component (could be a FR4 material with 400 m thickness), ii) attaching the base structures with completed cavity and pattern on two sides of the separation component, iii) proceeding the pick & place process for both cores on two sides, iv) proceeding the first lamination or hot press or both cores on two sides at the same time, v) removing the separation component by additional thermal treatment or merely removing it after a lamination step or a hot press process (based on the adhesive selection and process flow requirements), and vi) continuing the further processes as normal CCE (Center Core Embedded) process, laminating or hot pressing on the back side or both sides.
[0082] In the following description of exemplary embodiments, generally a double-side build-up (from both separation surfaces of the separation component) is described. However, each of these processes can also be performed with a single-side build-up, i.e. using just one separation surface of the separation component to build just one component carrier. In this case, it may be reasonably sufficient if the separation component has only one separation surface on that surface which is used for realizing the build-up.
[0083] FIGS. 1A to 1I illustrate exemplary embodiments of a method for manufacturing a first component carrier 100a and a second component carrier 100b.
[0084] FIG. 1A: A separation component 150 comprising a first separation surface 151 and a second separation surface 152, which is opposed to the first separation surface 151, is provided. The separation component 150 is a detachment core, wherein a core structure of electrically insulating material is sandwiched between two copper foils which are prone to enable later-on feasible detachment properties. In another embodiment, the separation component 150 comprises a dummy core sandwiched between two dummy insulator layers which are respectively covered by separation copper foils. The dummy core may hereby comprise a through-via structure. A first electrically insulating layer 130 is then laminated directly on the first separation surface 151 of the separation component 150 and a second electrically insulating layer 140 is laminated directly on the second separation surface 152. The first electrically insulating layer 130 and the second electrically insulating layer 140 are formed of a prepreg material with a low Young modulus, i.e. a Young modulus of less than 10 GPa. Hereby, the first electrically insulating layer 130 and the second electrically insulating layer 140 consist of prepreg material with a Young modulus around 7 GPa (for example TD002 or Dusan).
[0085] FIG. 1B: A first base structure 110 and a second base structure 120 are provided (only the first base structure is shown in this Figure). Each base structure 110, 120 comprises an electrically insulating layer structure 102 and an electrically conductive layer structure 104, the last in form of interconnection vias. Furthermore, each base structure 110, 120 comprises a cavity 111, 121 formed in the electrically insulating layer structure 102. In order to provide a space for accommodating an electronic component, each base structure 110, 120 comprises a temporary carrier 190 arranged below the electrically insulating layer structure 102 and the cavity 111, 121.
[0086] FIG. 1C: A first electronic component 115 is placed in the first cavity 111 such that the electronic component 115 is attached to the temporary carrier 190. The electronic component 115 comprises a first main surface 117 without electric contacts that faces away from the temporary carrier 190. The electronic component 115 comprises a further first surface 118, opposed to the first main surface 117, which comprises first electric contacts 116. Hereby, the first electric contacts 116 are attached to the temporary carrier 190. Furthermore, the same procedure is performed for the second base structure 120, whereby a second electronic component 125 with second electric contacts 126 is placed into the cavity 121 (not shown). In this exemplary embodiment, the electronic component 115, 125 is placed in the cavity 111, 121 before the base structure 110, 120 is coupled with the separation component 150. However, in another embodiment, the electronic component 115, 125 may be placed in the cavity after the base structure 110, 120 has been coupled with the separation component 150.
[0087] In an embodiment (not shown in this Figure), the first electronic component 115 is at least partially embedded (using an electrically insulating material) in the first cavity 111 of the first base structure 110 before attaching the first base structure 110 on top of the first electrically insulating layer 130 and/or the second electronic component 125 is at least partially embedded (using an electrically insulating material) in the second cavity 121 of the second base structure 120 before attaching the second base structure 121 on top of the second electrically insulating layer 140.
[0088] FIG. 1D: The first base structure 110 is coupled to the first separation surface 151 and the second base structure 120 is coupled to the second separation surface 152 of the separation component 150. The coupling is done by attaching the first base structure 110 directly on top of the first electrically insulating layer 130 and attaching the second base structure 120 directly on top of the second electrically insulating layer 140. The first base structure 110 is hereby attached on top of the first electrically insulating layer 130 such that the first main surface 117 of the first electronic component 115 is directly attached to the first electrically insulating layer 130, and the second base structure 120 is attached on top of the second electrically insulating layer 140 such that the second main surface 127 of the second electronic component 125 is directly attached to the second electrically insulating layer 140. In this manner, a semi-finished product 195 is obtained. The electrically insulating layers 130, 140 are made of prepreg, i.e. they are in an uncured state. In the uncured state the material is to some extent deformable so that the base structures 110, 120 can be pressed into the prepreg layers 130, 140. In this manner, first electrically conductive pillar structures 114 of the first base structure 110 pierce into the first electrically insulating layer 130 and second electrically conductive pillar structures 124 of the second base structure 120 pierce into the second electrically insulating layer 140. Also, the first and second electronic components 115, 125 can be pressed into the electrically insulating layers 130, 140, respectively, such that they pierce the uncured prepreg material 130, 140. Thereby, the electronic components 115, 125 can be embedded in the prepreg material 130, 140.
[0089] FIG. 1E: a lamination step is then performed by applying temperature and/or pressure. The prepreg material of the electrically insulating layers 130, 140 is cured in this manner. Thereby, tight connections between the electrically insulating layers 130, 140 and the respective base structures 110, 120 are formed. Furthermore, the first electronic component 115 becomes embedded in the first electrically insulating layer 130 and the second electronic component 125 becomes embedded in the second electrically insulating layer 140. At this stage, the electronic components 115, 125 can be considered as being in connection to their respective base structure 110, 120. Hence, the base structures 110, 120 could also already be termed first component carrier 100a and second component carrier 110b, respectively. Because the area of the separation component 150 is slightly smaller than the area of the base structures 110, 120 and of the electrically insulating layers 130, 140 (for example 510*515 mm for base structures and electrically insulating layers and 508*513 mm for the separation component), a step of trimming (removing) of the edges 191 is performed so that all layers have the same area size.
[0090] FIG. 1F: at this point, the temporary carriers 190 can be removed. Then, a first further electrically insulating layer structure 108 is laminated on the base structure 110. Additionally, a second further electrically insulating layer structure 109 is laminated on the second base structure 120. Alternatively, an electrically conductive (metal) layer can be applied by sputtering followed by the application of chemical copper and/or galvanic copper (e.g. performing a plating process). A further possibility is to start directly with chemical copper instead of sputtering. First electrically conductive interconnections 170 in form of first vias and metal layers are formed through the first further electrically insulating layer structure 108, in order to electrically contact the first electric contacts 116 of the first electronic component 115. The same is done using second electrically conductive interconnections 180 through the second further electrically insulating layer structure 109, in order to electrically contact the first electric contacts of the second electronic component 125. In this manner, a first redistribution structure 160 is formed at the first component carrier 100a and a second redistribution structure 161 is formed at the second component carrier 100b. The described procedure of FIG. 1F could be repeated one or more times. Hereby, other further electrically insulating layer structures may be laminated on top of the further first and second electrically insulating layer structures 108, 109 and other electrically conductive interconnections may be formed through these layers.
[0091] FIG. 1G: the main surfaces 165, 166 of the semi-finished product 195 receive a solder resist layer 196.
[0092] FIG. 1H: after a further trimming step, the first component carrier 100a and the second component carrier 100b are separated from the separation component 150. In particular, the first component carrier 100a and the second component carrier 100b are respectively detached from the first separation side 151 and the second separation side 152. Because the electrically insulating layers 130, 140 are tightly connected to the component carriers 100a, 100b after curing, said layers do not attach to the separation component 150 anymore after separation.
[0093] FIG. 1I: the final component carrier 100a (the same description holds true for the component carrier 100b not shown) is a coreless component carrier and comprises a layer stack 101 comprising electrically conductive layer structures 104 and electrically insulating layer structures 102. Hereby, one electrically insulating layer structure 130 is a low Young modulus layer structure formed of a low Young modulus material. Furthermore, the layer stack 101 is at least partially formed as a redistribution structure 160. The electronic component 115 embedded in the cavity 111 of the layer stack 101 is electrically connected with the redistribution structure 160 such that the first electric contacts 116 of the electronic component 115 are transferred via the redistribution structure 160 to second electric contacts 162 at the main surface 165 of the layer stack 101. The second electric contacts 162 are formed as solder balls and are larger than the first electric contact 116. The electronic component 115 is arranged directly between, the low Young modulus layer structure 130 and the redistribution structure 160. Especially, the electronic component 115 is embedded in the low Young modulus layer structure 130. In a last step, a heat distribution layer 199, e.g. a metal layer made of copper, is attached below the electrically insulating layer 130. The heat distribution layer 199 is connected to the electrically conductive interconnection 170 of the component carrier 100a. In particular, the heat distribution layer 199 electrically and thermally connected to vias that reach through the component carrier 100a. The electrically conductive interconnection 170 can also connect the heat distribution layer 199 is the redistribution structure 160. In this manner, the heat distribution layer 199 efficiently dissipates heat produced by the embedded electronic component 115. In a last step, a surface finish 197 is provided on top of the heat distribution layer 199.
[0094] FIGS. 3A to 3C show specific advantages of exemplary embodiments of the invention.
[0095] FIG. 3A: the electrically insulating layers 130, 140 are attached to the first separation surface 151 and to the second separation surface 152, respectively, of the separation component 150, e.g. a detach copper foil (DCF) as has already been described above. In the present embodiment, the area size of the electrically insulating layers 130, 140 is larger than the area size of the separation component 150. Thus, the separation component 150 can also be laminated at the sides 153 with the electrically insulating layers 130, 140. As a consequence, the separation component 150 can be fully surrounded by the electrically insulating layers 130, 140, i.e. prepreg material. In this manner, an undesired separation of the electrically insulating layers 130, 140 and the separation component 150 is efficiently prevented.
[0096] FIG. 3B: at the left side there is an example of a printed circuit board 200 from the prior art shown (see also FIG. 2 above). The lamination of further layers is asymmetrical according to the prior art and thus, problems with respect to bending/warpage (shown by dotted line) occur. Hence, thick core structures have to be used. At the right side there is shown a semi-finished product 195 according to an exemplary embodiment of the invention. Lamination is done in a symmetrical manner above and below the separation component 150. Because the semi-finished product 195 already comprises a certain thickness, there is no need for a core structure. As a result, coreless structures can be used without issues regarding warpage.
[0097] FIG. 3C: a component carrier 100a is shown which comprises an embedded component 115. The component 115 produces heat which can be efficiently dissipated using the electrically conductive material (e.g. copper) of the electrically conductive interconnection 170 which are present anyway in the component carrier 100a. The electrically conductive interconnection 170 comprises vias which are electrically connected to a heat distribution layer 199. The heat distribution layer 199 may be formed of metal (e.g. copper) or another material with a high thermal conductivity, e.g. diamond-like carbon or aluminum nitride. Furthermore, the heat distribution layer 199 may be covered with a surface finish 197. The heat distribution layer 199 and the vias of the electrically conductive interconnection 170 are electrically and thermally connected such that the heat distribution layer 199 and the electrically conductive interconnection 170 at least partially surround the cavity 111 in which the electronic component 115 is placed. In this manner, an efficient heat dissipation is provided, even though the electronic component 115 is embedded in a thick layer of electrically insulating material (which generally comprises a very low thermal conductivity).
[0098] FIGS. 4A to 4D show exemplary embodiments of component carriers according to the invention, wherein the component carrier application depends on the core type and the front side structure. The component carriers 400a, 400b are shown directly after separation from a separation component 150. The component carriers 400a, 400b comprise each an embedded electronic component 115 which is sandwiched between a redistribution structure 160, 161 and an electrically insulating layer 130, 140.
[0099] FIG. 4A: an LTH (laser through hole) core 402 is applied with completely filled vias 404 as through-hole connections.
[0100] FIG. 4B: a PTH (plated through hole) core 402 is applied with not completely filled vias 404 as through-hole connections.
[0101] FIG. 4C: a core structure 402 is applied without a through-hole connection.
[0102] FIG. 4D: a core structure (no PTH core) 402 is applied. The electrically insulating layers 130, 140 are not covered by a further layer.
[0103] FIGS. 5A to 5K show exemplary embodiments of a further method of manufacturing component carriers.
[0104] FIG. 5A: a base structure 510 is provided comprising an electrically insulating layer structure 502 sandwiched between two electrically conductive layer structures 504, i.e. a copper-clad laminate (CCL).
[0105] FIG. 5B: holes are drilled through the base structure 510 and are consequently filled with electrically conductive material 504 in order to form vias (LTH patterning).
[0106] FIG. 5C: a cavity 511 is formed in the center of the base structure 510, e.g. by laser drilling, sand-blasting, or other known methods.
[0107] FIG. 5D and 5E: the vias 504 are enlarged to (copper) pillar structures 514 using known methods.
[0108] FIG. 5F: a temporary carrier 190 is attached to the base structure 510 at the opposite side of the pillar structures 514.
[0109] FIG. 5G: an electronic component 115 is placed into the cavity 511 and onto the temporary carrier 190.
[0110] FIG. 5H: the base structure 510 and a further base structure 520 are coupled to the two separation surfaces 151, 152, respectively, of a separation component 150. Between the separation surfaces 151, 152 and the base structures 510, 520 there are arranged electrically insulating layers 130, 140 of (uncured) prepreg material.
[0111] FIG. 5I: the base structures 510, 520 have been pressed into the uncured electrically insulating layers 130, 140 such that the pillar structures 514, 524 pierce into the electrically insulating layers 130, 140, respectively, and the electronic components 115, 125 become embedded by the electrically insulating layers 130, 140. Using a lamination process (high temperature and pressure), the prepreg material becomes cured and a semi-finished product 595 is obtained. The base structures 510, 520 are now connected to their respective electronic component 115, 125 and can be termed component carriers.
[0112] FIG. 5J: the temporary carrier 190 is removed.
[0113] FIG. 5K: an additional plasma 507 step is performed to the main surfaces of the semi-finished product 595. The purpose of the plasma process is to remove temporary carrier residues and clean electric contacts.
[0114] FIGS. 6A to 6K show exemplary embodiments of a further method of manufacturing component carriers.
[0115] FIG. 6A: a semi-finished product 695 (e.g. as described above) is provided.
[0116] FIG. 6B: the temporary carrier 190 is detached and, after a step of plasma treatment, a first layer build-up is performed. Thereby, further electrically insulating layer structures 108, 109 are laminated and electrically conductive interconnections 170, 180 are provided.
[0117] FIG. 6C: a second layer build-up step is performed and a protection film 607 (e.g. polyimide) is provided.
[0118] FIG. 6D: the edges are trimmed and the component carriers 600a, 600b are detached from the separation component 150.
[0119] FIG. 6E: holes are drilled through the electrically insulating layer 130 using X-ray and/or laser drilling.
[0120] FIG. 6F: the holes are filled with electrically conductive material in order to form vias and a heat distribution layer 199 is formed on the electrically insulating layer 130.
[0121] FIG. 6G: the protection film 607 is removed.
[0122] FIG. 6H: a solder resist 196 is provided at both sides.
[0123] FIG. 6I: a surface finish layer 197 is provided at both sides.
[0124] FIG. 6J: second electric contacts 162 are formed at the main surface 165 of the component carrier 600a. The contacts 162 are formed as solder balls and the redistribution structure 160 is finished.
[0125] FIG. 6K: an electric check (shown symbolically with a flash) is performed in order to finish the component carrier 600a.
[0126] FIGS. 7A to 7I show exemplary embodiments of a further method of manufacturing component carriers.
[0127] FIG. 7A: a semi-finished product 795 (e.g. as described above) is provided and a first layer build-up is performed. Thereby, further electrically insulating layer structures 108, 109 are laminated and electrically conductive interconnections 170, 180 are provided.
[0128] FIG. 7B: a second layer build-up step is performed and solder resist 196 is provided.
[0129] FIG. 7C: a protection film 707 (e.g. polyimide) is provided.
[0130] FIG. 7D: the edges are trimmed and the component carriers 700a, 700b are detached from the separation component 150.
[0131] FIGS. 7E and 7F: copper etching and/or laser direct ablation (LDA) are used to pattern the surface of the electrically insulating layer 130 and the pillar structures 114 pierced there into. On the right side of FIG. 7F, there are two embodiments shown after performing the LDA step. Further to the right side, there are two embodiments shown after performing an additional ENEPIG (electroless nickel electroless palladium immersion gold) step. Then, an additional plasma 507 step is performed to the main surfaces of the component carrier 700a.
[0132] FIG. 7G: a surface finish 197 is provided.
[0133] FIG. 7H: a further trimming step is performed and second electric contacts 162 are formed at the main surface 165 of the component carrier 700a. The contacts 162 are formed as solder balls and the redistribution structure 160 is finished.
[0134] FIG. 7I: an electric check (shown symbolically with flashes) is performed in order to finish the component carrier 700a.
[0135] FIGS. 8A to 8C show exemplary embodiments of a further method of manufacturing component carriers.
[0136] FIG. 8A: a first base structure 110, comprising an electrically insulating structure 102 and an electrically conductive structure 104, is provided. A first electronic component 115 is placed in a cavity 111 in the electrically insulating structure 102 and is fixed using a temporary carrier 190. Then, the first electronic component 115 is (at least partially) embedded/encapsulated, using an electrically insulating material 802, in the first cavity 111 of the first base structure 110. Then the temporary carrier 190 is removed.
[0137] FIG. 8B: a semi-finished product 895 (e.g. as described above) is provided with a first base structure 110 and a second base structure 120 arranged on opposing main surfaces of a separation component 150. The first base structure 110 with the embedded electronic component 115 is attached on top of a first electrically insulating layer 130 of a separation component 150. Hereby, the electronic component 115 is already embedded in an electrically insulating material 802. The same is done for a second electronic component 125 which is (at least partially) embedded (using a further electrically insulating material 802) in a second cavity 121 of a second base structure 120, before the second base structure 121 is attached on top of the second electrically insulating layer 140 of the separation component 150. Later on, further electrically insulating structures 108, 109 and additional electrically conductive structures 170, 180 are attached on top of the base structures 110, 120, respectively. Alternatively, an electrically conductive (metal) layer can be applied by sputtering followed by the application of chemical copper and/or galvanic copper (e.g. performing a plating process). A further possibility is to start directly with chemical copper instead of sputtering. Layer build-up is done using known methods such as subtractive, mSAP or SAP.
[0138] FIG. 8C: two component carriers 100a, 100b are detached from the separation component 150. These component carriers 100a, 100b show an asymmetric build-up with a respective redistribution structure 160, 161 on one side of the respective component 115, 125, and a respective heat distribution layer 199 on the opposed side of the respective electronic component 115, 125. While the first component carrier 100a has an exposed heat distribution layer 199, the second component carrier 100b comprises a layer of solder resist 196 over the heat distribution layer 199. The redistribution structure 160 includes one or more second electric contacts 162. Similarly, the redistribution structure 161 includes one or more further second electric contacts 163.
[0139] FIGS. 9A to 9I show exemplary embodiments of a further method of manufacturing component carriers. While a double-side build-up (from both separation surfaces of the separation component) is described in the following, the whole process can also be performed with a single-side build-up, i.e. using just one separation surface of the separation component to build the component carrier.
[0140] FIG. 9A: a separation component 150 is provided. The separation sides 151 and 152 are covered by a first temporary carrier 990a and a second temporary carrier 990b, respectively, which are constructed to allow a temporary adhering.
[0141] FIG. 9B: a first base structure 110 is coupled with the first separation surface 151 such that a first cavity 111 is provided, and a second base structure 120 is coupled with the second separation surface 152 such that a second cavity 121 is provided.
[0142] FIG. 9C: a first electronic component 115 is placed into the first cavity 111 and is adhered to the first temporary carrier 990a. Furthermore, a second electronic component 125 is placed into the second cavity 121 and is adhered to the second temporary carrier 990b. In this manner, a semi-finished product 995 is obtained.
[0143] FIG. 9D: the first base structure 110 is laminated with a further electrically insulating layer structure 908a so that the first electronic component 115 is embedded in the material of the further electrically insulating layer structure 908a. Furthermore, the second base structure 120 is laminated with a further electrically insulating layer structure 909a so that the second electronic component 125 is embedded in the material of the further electrically insulating layer structure 909a.
[0144] FIGS. 9E and 9F: a first component carrier 100a and a second component carrier 100b are detached from the separation component 150. Optionally this step is accompanied by thermal treatment. The temporary carriers 990a, 990b do hereby not adhere to the component carriers 100a, 100b anymore.
[0145] FIG. 9G: a further electrically insulating layer structure 908b is laminated to the backside of the first component carrier 100a so that the first electronic component 115 becomes fully embedded.
[0146] FIG. 9H: a first electrically conductive interconnection 170, comprising a plurality of vias, is formed through the first further electrically insulating layer structure 908a, in order to electrically contact a first electric contact of the first electronic component 115.
[0147] FIG. 9I: after a second lamination and electrically contacting step, the final component carrier 100a is provided with a first redistribution structure 160.
[0148] FIGS. 10A to 10J show exemplary embodiments of a further method of manufacturing component carriers. While a double-side build-up (from both separation surfaces of the separation component) is described in the following, the whole process can also be performed with a single-side build-up, i.e. using just one separation surface of the separation component to build the component carrier.
[0149] FIG. 10A: a separation component 150 is provided. The separation sides 151 and 152 are covered by a first temporary carrier 990a and a second temporary carrier 990b, respectively. These function as an adhesive material.
[0150] FIG. 10B: a first base structure 110 is coupled with the first separation surface 151 such that a first cavity 111 is provided, and a second base structure 120 is coupled with the second separation surface 152 such that a second cavity 121 is provided.
[0151] FIG. 10C: a first electronic component 115 is placed into the first cavity 111 and is adhered to the first temporary carrier 990a. Furthermore, a second electronic component 125 is placed into the second cavity 121 and is adhered to the second temporary carrier 990b. Hereby, a semi-finished product 1095 is obtained.
[0152] FIG. 10D: the first base structure 110 is laminated with a further electrically insulating layer structure 908a so that the first electronic component 115 is embedded in the material of the further electrically insulating layer structure 908. Furthermore, the second base structure 120 is laminated with a further electrically insulating layer structure 909a so that the second electronic component 125 is embedded in the material of the further electrically insulating layer structure 909a.
[0153] FIG. 10E: a first electrically conductive interconnection 170, comprising a plurality of vias, is formed through the first further electrically insulating layer structure 908a, in order to electrically contact a first electric contact of the first electronic component 115. Furthermore, a second electrically conductive interconnection 180, comprising a plurality of vias, is formed through the second further electrically insulating layer structure 909a, in order to electrically contact a first electric contact of the second electronic component 125.
[0154] FIG. 10F: a further step of laminating and electrically contacting is performed.
[0155] FIGS. 10G and 10H: a first component carrier 100a and a second component carrier 100b are detached from the separation component 150. Optionally this step is accompanied by thermal treatment. The temporary carriers 990a, 990b do hereby not adhere to the component carriers 100a, 100b. The component carrier 100a comprises a first redistribution structure 160.
[0156] FIG. 10I: a further lamination and electrically contacting step is performed. A further electrically insulating layer structure 908b is laminated to the backside of the first component carrier 100a so that the first electronic component 115 becomes fully embedded.
[0157] FIG. 10J: the final component carrier 100a is provided with a heat distribution layer 199.Implementation of the invention is not limited to the preferred embodiments shown in the figures and described above. Instead, a multiplicity of variants are possible which use the solutions shown and the principle according to the invention even in the case of fundamentally different embodiments.
[0158] It should be noted that the term comprising does not exclude other elements or steps and the use of the article a or an does not exclude a plurality. Also, elements described in association with different embodiments may be combined.
REFERENCE SIGNS
[0159] 100a, 400a, 600a, First component carrier 700a [0160] 100b, 400b, 600b, Second component carrier 700b [0161] 101 Layer stack [0162] 102, 402, 502 Electrically insulating layer structure [0163] 104, 404, 504 Electrically conductive layer structure [0164] 108, 908a, 908b First further electrically insulating layer structure [0165] 109, 909a Second further electrically insulating layer structure [0166] 110, 110b, 510 First base structure [0167] 111, 511 First cavity [0168] 114, 514 First pillar structure [0169] 115 First electronic component [0170] 116 First electric contact [0171] 117 Main surface of first electronic component [0172] 118 Further main surface of first electronic component [0173] 120, 520 Second base structure [0174] 121 Second cavity [0175] 124, 524 Second pillar structure [0176] 125 Second electronic component [0177] 126 Further first electric contact [0178] 127 Main surface of second electronic component [0179] 130 First electrically insulating layer/low Young modulus layer structure [0180] 140 Second electrically insulating layer [0181] 150 Separation component [0182] 151 First separation surface [0183] 152 Second separation surface [0184] 153 Sidewall of separation component [0185] 160 First redistribution structure [0186] 161 Second redistribution structure [0187] 162 Second electric contact [0188] 163 Further second electric contact [0189] 165 Main surface of component carrier [0190] 166 Further main surface of component carrier [0191] 170 First electrically conductive interconnection [0192] 180 Second electrically conductive interconnection [0193] 190 Temporary carrier [0194] 191 Edge part [0195] 195, 595, 695, 795, 895 Semi-finished product 995, 1095 [0196] 196 Solder resist [0197] 197 Surface finish [0198] 199 Heat distribution layer [0199] 200 Prior art core structure [0200] 202 Prior art electrically insulating layer [0201] 204 Prior art electrically conductive structure [0202] 208, 209 Prior art embedding material [0203] 215 Prior art chip [0204] 290 Prior art tape [0205] 507 Plasma [0206] 607, 707 Protection layer [0207] 802 Electrically insulating material for embedding [0208] 990a First temporary carrier [0209] 990b Second temporary carrier
