DRIVER CIRCUIT

Abstract

The present invention is targeted at suppressing ringing and overvoltage.

A driver circuit (200) drives a plurality of loads (Z.sub.1 to Z.sub.N). A plurality of output terminals (Po.sub.1 to Po.sub.N) are connected to the plurality of loads (Z.sub.1 to Z.sub.N). A plurality of drivers (Dr.sub.1 to Dr.sub.N) correspond to the plurality output terminals (Po.sub.1 to PO.sub.N), and generate driving signals (Vo.sub.#) applied to the respectively corresponding load (Z.sub.#). A plurality of clamp circuits (260_1 to 260_N) correspond to the plurality of drivers (Dr.sub.1 to Dr.sub.N), and include Schottky diodes (SD) connected to input nodes or output nodes of the respectively corresponding drivers (Dr).

Claims

1. A driver circuit, driving a plurality of load devices, the driver circuit comprising: a plurality of output terminals, connected to the plurality of load devices; a plurality of drivers, corresponding to the plurality of output terminals, generating driving signals applied to the respectively corresponding load devices; and a plurality of clamp circuits, corresponding to the plurality of drivers, comprising Schottky diodes connected to input nodes or output nodes of the respectively corresponding drivers; wherein, the driver circuit is integrated on a semiconductor substrate.

2. The driver circuit according to claim 1, wherein each of the clamping circuit comprises: an upper-side Schottky diode, provided between the input node or the output node of the corresponding driver and a power line; and a lower-side Schottky diode, provided between the input node or the output node of the corresponding driver and a ground line.

3. The driver circuit according to claim 1, further comprising: a plurality of bypass circuits, corresponding to the plurality of drivers, comprising capacitors connected to the input nodes or the output nodes of the respectively corresponding drivers.

4. The driver circuit according to claim 3, wherein the capacitor is a gate capacitor of a metal-oxide-semiconductor (MOS) transistor.

5. The driver circuit according to claim 3, wherein each of the bypass circuits comprises: an upper-side capacitor, provided between the input node or the output node of the corresponding driver and a power line; and a lower-side capacitor, provided between the input node or the output node of the corresponding driver and a ground line.

6. The driver circuit according to claim 1, wherein the driver circuit is in a package having a first direction as lengthwise and a second direction as widthwise; the plurality of output terminals are disposed and aligned in the first direction; and the driver and the clamp circuit corresponding to one of the output terminals are disposed and aligned in the second direction.

7. The driver circuit according to claim 1, further comprising: a plurality of protection circuits, corresponding to the plurality of output terminals, comprising protection diodes connected to the respectively corresponding output terminals.

8. The driver circuit according to claim 1, wherein each of the plurality of drivers comprises an analog switch.

9. The driver circuit according to claim 1, wherein each of the plurality of drivers comprises an amplifier.

10. The driver circuit according to claim 1, wherein each of the plurality of drivers comprises an inverter outputting a high-level voltage and a low-level voltage.

11. The driver circuit according to claim 1, wherein the driver circuit drives a matrix-type display panel.

12. The driver circuit according to claim 1, the driver circuit drives a print head.

13. A driver circuit, driving a plurality of load devices, the driver circuit comprising: a plurality of output terminals, connected to the plurality of load devices; a plurality of drivers, corresponding to the plurality of output terminals, generating driving signals applied to the respectively corresponding load devices; a plurality of first diodes, corresponding to the plurality of output terminals, connected to the respectively corresponding output terminals; and a plurality of clamp circuits, corresponding to the plurality of drivers, comprising second diodes connected to input nodes or output nodes of the respectively corresponding drivers; wherein, the driver circuit is integrated on a semiconductor substrate, and a forward voltage of the second diode is smaller than that of the first diode.

14. The driver circuit according to claim 13, wherein the second diode is a Schottky diode.

15. The driver circuit according to claim 13, further comprising: a plurality of bypass circuits, corresponding to the plurality of drivers, comprising capacitors connected to the input nodes or output nodes of the respectively corresponding drivers.

16. A driver circuit, driving a plurality of load devices, the driver circuit comprising: a plurality of output terminals, connected to the plurality of load devices; a plurality of drivers, corresponding to the plurality of output terminals, generating driving signals applied the respectively corresponding load devices; and a plurality of bypass circuits, corresponding to the plurality of drivers, comprising capacitors connected to input nodes or output nodes of the respectively corresponding drivers; wherein, the driver circuit is integrated on a semiconductor substrate.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0025] FIG. 1 is a block diagram of a display system;

[0026] FIGS. 2(a) to (c) are waveforms of a source driving voltage V.sub.S generated by a source driver;

[0027] FIGS. 3(a) to (c) are waveforms of a gate driving voltage V.sub.G generated by a gate driver;

[0028] FIG. 4 is a circuit diagram of a driver circuit according to embodiment 1;

[0029] FIGS. 5(a) and (b) are diagrams illustrating actions of the driver circuit in FIG. 4;

[0030] FIG. 6 is a circuit diagram of a specific exemplary structure (embodiment 1.1) of the driver circuit according to embodiment 1;

[0031] FIGS. 7(a) to (c) are circuit diagrams of exemplary structures of an analog switch;

[0032] FIG. 8 is a circuit diagram of a specific exemplary structure (embodiment 1.2) of the driver circuit according to embodiment 1;

[0033] FIG. 9 is a circuit diagram of a specific exemplary structure (embodiment 1.3) of the driver circuit according to embodiment 1;

[0034] FIG. 10 is a circuit diagram of a driver circuit according to embodiment 2;

[0035] FIG. 11 is a diagram illustrating actions of the driver circuit in FIG. 10;

[0036] FIG. 12 is a circuit diagram of a specific exemplary structure (embodiment 2.1) of the driver circuit according to embodiment 2;

[0037] FIGS. 13(a) to (c) are circuit diagrams of exemplary structures of an analog switch and a bypass circuit;

[0038] FIG. 14 is a circuit diagram of a specific exemplary structure (embodiment 2.2) of the driver circuit according to embodiment 2;

[0039] FIG. 15 is a circuit diagram of a specific exemplary structure (embodiment 2.3) of the driver circuit according to embodiment 2;

[0040] FIG. 16 is a layout diagram of the driver circuit in FIG. 12;

[0041] FIG. 17 is a layout diagram of the driver circuit in FIG. 14; and

[0042] FIG. 18 is a layout diagram of the driver circuit in FIG. 15.

DETAILED DESCRIPTION OF THE EMBODIMENTS

[0043] The present invention is described by way of appropriate embodiments with the accompanying drawings below. The same symbols and denotations are assigned to the same or equivalent constituents, components and processes in the drawings, and repeated description is appropriately omitted. Further, the embodiments are merely illustrative and exemplary, and are not to be construed as limitations to the present invention. Further, not all features and combinations thereof stated in the embodiments are necessarily essentials of the present invention.

[0044] In the description, an expression of so-called a state in which component A is connected to component B includes a situation where component A is physically and directly connected to component B, and further includes a situation where component A is indirectly connected to component B via other components without affecting an electrical connection state. Similarly, the expression of so-called a state in which component C is disposed between component A and component B further includes, in addition to a situation where component A, component B and component C are directly connected, a situation of indirect connection via other components without affecting an electrical connection state.

Embodiment 1

[0045] FIG. 4 shows a circuit diagram of a driver circuit 200 according to embodiment 1. The driver circuit 200 includes N channels of N outputs so as to drive N load devices (to be referred to load devices) Z.sub.1 to Z.sub.N. The driver circuit 200 includes a plurality of output terminals Po.sub.1 to PO.sub.N, a plurality of drivers Dr.sub.1 to Dr.sub.N, a plurality of protection circuits 250_1 to 250_N, and a plurality of clamp circuits 260_1 to 260_N, and is integrated on a function integrated circuit (IC) on a semiconductor substrate.

[0046] The driver circuit 200 forms a system 300 jointly with a load circuit 310 and a main processor that is not shown in the drawing.

[0047] The load circuit 310 includes N load devices Z.sub.1 to Z.sub.N. For example, the load device Z is a transistor, a piezoelectric device, a light emitting diode (LED) or a thermistor.

[0048] The plurality of output terminals Po.sub.1 to PO.sub.N are connected to the plurality of load devices Z.sub.1 to Z.sub.N. The plurality of drivers Dr.sub.1 to Dr.sub.N correspond to the plurality of output terminals Po.sub.1 to PO.sub.N. The output of the driver Dr.sub.# (where #=1 to N)) is connected to the corresponding load device Z.sub.# through the corresponding output terminal Po.sub.#. The driver Dr.sub.# generates a driving signal Vo.sub.# applied to the corresponding load device Z.sub.# according to a control signal CTRL.sub.# and outputs the driving signal Vo.sub.# via the output terminal Po.sub.#. The driving signal Vo.sub.# can be a voltage signal or a current signal. Controls signals CTRL.sub.1 to CTRL.sub.N can be generated in the driver circuit 200, or can be provided externally to the driver circuit 200.

[0049] The plurality of protection circuits 250_1 to 250_N correspond to the plurality of output terminals Po.sub.1 to PO.sub.N. Each protection circuit 250_# includes a first diode D.sub.# for protection against electrostatic discharge (ESD), wherein the first diode D.sub.# is formed by PN junction. For example, an upper-side first diode D.sub.# H is disposed between the output terminal Po.sub.# and a power line, and a lower-side first diode D.sub.# L is disposed between the output terminal Po.sub.# and a ground line.

[0050] The plurality of clamp circuits 260_1 to 260_N correspond to the plurality of drivers Dr.sub.1 to Dr.sub.N. Each clamp circuit 260_# includes a second diode SD.sub.# connected to the output node (or the input node) of the corresponding driver Dr.sub.#. A forward voltage Vf.sub.2 of the second diode SD.sub.# is preferably smaller than a forward voltage Vf.sub.1 of the first diode D.sub.# and is high-speed (having a shorter recovery time), and from such perspective, the second diode SD.sub.# is preferably implemented by a Schottky diode (Vf.sub.1=0.7 V, and Vf.sub.2=0.1 V).

[0051] For example, the clamp circuit 260_# includes: an upper-side second diode SD.sub.# H, disposed between the output node of the driver Dr.sub.# and the power line; and a lower-side second diode SD.sub.# L, disposed between the output node of the driver Dr.sub.# and the ground line.

[0052] The structure of the driver circuit 200 is described below. Refer to FIGS. 5(a) and (b) for description on the actions of the driver circuit 200. For comparison, the waveforms of the actions of the second diodes SD.sub.1 to SD.sub.N are omitted from FIG. 5(a), and the actions of the driver circuit 200 in FIG. 4 are shown in FIG. 5(b). It is assumed that abnormality has occurred in the load impedance in a channel CH.sub.#. The abnormality in the load impedance brings ringing to a potential Vo.sub.# of the output terminal Po.sub.# of the channel CH.sub.#. Given that only the first diode D.sub.# for ESD protection is present, the upper-side first diode D.sub.# H is caused to be conducted by the voltage Vo.sub.# exceeding V.sub.DD+Vf.sub.1, and is thus clamped at V.sub.DD+Vf.sub.1. Further, the lower-side first diode D.sub.# L is caused to be conducted by a voltage lower thanz Vf.sub.1, and is thus clamped at Vf.sub.1. That is to say, as shown in FIG. 5(a), the potential Vo.sub.# of the output terminal Po.sub.# varies within a range of Vf.sub.1 to V.sub.DD+Vf.sub.1.

[0053] In contrast, given that the second diode SD.sub.# is disposed, the upper-side second diode SD.sub.# H is caused to be conducted by the voltage Vo.sub.# exceeding V.sub.DD+Vf.sub.2, and is thus clamped at V.sub.DD+Vf.sub.2. Further, the lower-side second diode SD.sub.# L is caused to be conducted by a voltage lower than Vf.sub.2, and is thus clamped at Vf.sub.2. The result is that, as shown in FIG. 5(b), the potential Vo.sub.# of the output terminal Po.sub.# is limited within the range of Vf.sub.2 to V.sub.DD+Vf.sub.2, which has a reduced range compared to the situation without the second diode. Therefore, overvoltage and ringing can be suppressed.

[0054] In another approach, a structure (a comparison technology) in which a Schottky diode is externally provided for each output terminal Po of the driver circuit 200 is considered. In embodiment 1, the second diodes SD.sub.1 to SD.sub.N are integrated on the semiconductor chip of the driver circuit 200, and the installation area and costs of the circuit can be significantly reduced compared to the comparison technology.

[0055] In addition, in the comparison technology, the physical distance between a node (to be referred to as a protected node) at which overvoltage and ringing should be suppressed and the Schottky diode is increased, and the influence of the parasitic impedance between the protected node and the Schottky diode is also increased, such that the voltage clamping effect of the Schottky diode is limited. In comparison, in embodiment 1, the distance between the protected node and the second diode SD.sub.# can be reduced and the parasitic impedance therebetween can be accordingly decreased, such that the effects of suppressing overvoltage and ringing for the second diode SD.sub.# can be maximized.

Embodiment 1.1

[0056] FIG. 6 shows a circuit diagram of a specific exemplary structure of a driver circuit (embodiment 1.1, denoted as 200A) according to embodiment 1. The driver circuit 200A is a switch-type driver, and is capable of enabling the output terminal Po of any channel to generate an input voltage Vcom supplied to an input terminal Pi. For example, the driver circuit 200A is a printer driver, and the driver circuit 200A and a load circuit 310A serving as a print head jointly form a printer system 300A.

[0057] A driver Dr of each channel includes an analog switch SWA, and the state of each analog switch SWA.sub.# (where #=1 to N) is controlled by a corresponding control signal CTRL.sub.#.

[0058] When the analog switch SWA.sub.# is conducted, the input terminal Pi and the output terminal Po.sub.# are conducted, and the input signal Vcom is present in the output terminal Po.sub.#.

[0059] The driver circuit 200A includes a plurality of level shifters LS.sub.1 to LS.sub.N, a signal processing portion 220, and an interface circuit 230. The interface circuit 230 receives from a main processor 320A data for controlling outputs of the channels. The signal processing portion 220 is a logic circuit, and generates control signals CTRL.sub.1 to CTRL.sub.N based on the data received by the interface circuit 230. Each level shifter LS.sub.# receives the control signal CTRL.sub.# of the corresponding channel, converts the control signal CTRL.sub.# to an appropriate voltage level, and drives the corresponding analog switch SWA.sub.#.

[0060] In embodiment 1.1, an ESD protection circuit 250_# is connected to each output terminal Po.sub.#, and an ESD protection circuit 270 is connected to the common input terminal Pi. The protection circuit 270 can have a same structure as the protection circuit 250.

[0061] Further, in embodiment 1.1, a clamp circuit 280_# is disposed on an input side of each driver Dr.sub.#. The clamp circuit 280_# includes a diode having a forward voltage smaller than that of the protection circuit 270. The structure of the clamp circuit 280_# can be the same as that of the clamp circuit 260_#, and can include a Schottky diode.

[0062] When the driver Dr includes the analog switch SWA, the effects of suppressing overvoltage and ringing can be further enhanced by using the clamp circuit 280_# disposed on the input side.

[0063] FIGS. 7(a) to (c) are circuit diagrams of exemplary structures of the analog switch SWA. The analog switch SWA in FIG. 7(a) includes a P-channel metal-oxide-semiconductor (PMOS) transistor, which has its back gate connected to a power line V.sub.DD. The analog switch SWA in FIG. 7(b) includes an N-channel metal-oxide-semiconductor (NMOS) transistor, which has its back gate grounded. The analog switch SWA in FIG. 7(c) is formed by a pair of NMOS transistor and PMOS transistor. The structure of the analog switch SWA is designed according to the signal level (the voltage range) of the input signal Vcom.

Embodiment 1.2

[0064] FIG. 8 shows a circuit diagram of a specific exemplary structure of a driver circuit (embodiment 1.2, denoted as 200B) according to embodiment 1. The driver circuit 200B is a binary driver selectively outputting two values including a high-level voltage and a low-level voltage to the output terminal Po of each channel. For example, the driver circuit 200B is a gate driver, and the driver circuit 200B and a load circuit 310B serving as a display panel jointly form a display system 300B.

[0065] The driver Dr of each channel includes an inverter INV capable of outputting two values including a high-level voltage and a low-level voltage. The state of each inverter INV.sub.# (where #=1 to N) is controlled by a corresponding control signal CTRL.sub.#.

[0066] The inverter INV includes a high-side transistor M.sub.H and a low-side transistor M.sub.L. When the control signal CTRL.sub.# is a first level (e.g., a high voltage), the high-side transistor M.sub.H is conducted and the low-side transistor M.sub.L is disconnected, and a high-level voltage V.sub.DD is generated in the output terminal Po.sub.#. When the control signal CTRL.sub.# is a second level (e.g., a low voltage), the high-side transistor M.sub.H is disconnected and the low-side transistor M.sub.L is conducted, and a low-level voltage 0V is generated in the output terminal Po.sub.#.

[0067] The driver circuit 200B includes a plurality of level shifters LS.sub.1 to LS.sub.N, a signal processing portion 220, and an interface circuit 230. The interface circuit 230 receives a synchronization signal (a control signal) from a timing controller 320B. The signal processing portion 220 is a logic circuit, and generates control signals CTRL.sub.1 to CTRL.sub.N based on the synchronization signal received by the interface circuit 230. Each level shifter LS.sub.# receives the control signal CTRL.sub.# of the corresponding channel, converts the control signal CTRL.sub.# to an appropriate voltage level, and drives the corresponding inverter INV.sub.#.

[0068] The driver circuit 200B includes a clamp circuit 260_# connected to the output node of each driver Dr (the inverter INV).

Embodiment 1.3

[0069] FIG. 9 shows a circuit diagram of a specific exemplary structure of the driver circuit (embodiment 1.3, denoted as 200C) according to embodiment 1. The driver circuit 200C enables the output terminal Po of each channel to generate a multi-value driving signal.

[0070] For example, the driver circuit 200C is a source driver, and the driver circuit 200C and a load circuit 310C serving as a display panel jointly form a display system 300C.

[0071] The driver Dr.sub.# of each channel includes an amplifier (a buffer) AMP.sub.# capable of outputting any voltage level and a digital-to-analog converter (DAC) DAC.sub.#. The DAC DAC.sub.# converts a digital control signal (brightness data) CTRL.sub.# to an analog control signal, and provides the analog control signal to the amplifier AMP.sub.#. The output level of each amplifier AMP.sub.# (where #=1 to N) is controlled by a corresponding control signal CTRL.sub.#.

[0072] The driver circuit 200C includes a plurality of level shifters LS.sub.1 to LS.sub.N, a signal processing portion 220, and an interface circuit 230. The interface circuit 230 receives image data from the timing controller 320B. The signal processing portion 220 is a logic circuit, and generates, based on image signals received by the interface circuit 230, control signals CTRL.sub.1 to CTRL.sub.N indicating brightness of individual pixels. Each level shifter LS.sub.# receives the control signal CTRL.sub.# of the corresponding channel, converts the control signal CTRL.sub.# to an appropriate voltage level, and provides the voltage level to the corresponding DAC DAC.sub.#.

[0073] The driver 200C includes clamp circuits 260_# connected to the output nodes of the drivers Dr (the amplifiers AMP).

Embodiment 2

[0074] FIG. 10 shows a circuit diagram of a driver circuit 202 according to embodiment 2. The fundamental structure of the driver circuit 202 is the same as that of the driver circuit in FIG. 4. The driver circuit 202 further includes a plurality of bypass circuits 290_1 to 290_N.

[0075] The plurality of bypass circuits 290_1 to 290_N correspond to a plurality of drivers Dr.sub.1 to Dr.sub.N. Each bypass circuit 290_# includes a capacitor C.sub.# connected to an output node (or an input node) of the corresponding driver Dr.sub.#. The bypass circuit 290_# releases high-frequency noise inputted by the corresponding output terminal Po.sub.# to a power line or a ground line. Therefore, the capacitance of the capacitor C.sub.# only needs to be set as being low enough impedance in the frequency band of the high-frequency noise.

[0076] For example, the bypass circuit 290_# includes: an upper-side capacitor C.sub.# H, disposed between the output node of the driver Dr.sub.# and the power line; and a lower-side capacitor C.sub.# L, disposed between the output node of the driver Dr.sub.# and the ground line.

[0077] The above is the structure of the driver circuit 202. Actions of the driver circuit 202 are to be described below. FIG. 11 shows a diagram of actions of the driver circuit 202 in FIG. 10. In FIG. 11, two channels CH.sub.i and CH.sub.i+1 that are adjacent are depicted, and the two channels CH.sub.i and CH.sub.i+1 are coupled by a capacitor Cp.

[0078] When the voltage Vo.sub.i of the lines of the channel CH.sub.i is transferred, the high-frequency component therein invades the line of the other channel CH.sub.i+1 through the capacitor Cp, resulting in a main factor causing malfunction or quality degradation. The bypass circuit 290_(i+1) is capable of releasing the high-frequency noise invaded through the capacitor Cp to the power line or the ground line. Therefore, the change in the potential Vo.sub.i+1 of the other channel CH.sub.i+1 can be suppressed.

[0079] In embodiment 2, the structure of the driver Dr is the same as those in the description associated with embodiments 1.1 to 1.3, and can be implemented by various forms.

Embodiment 2.1

[0080] FIG. 12 shows a circuit diagram of a specific exemplary structure of the driver circuit (embodiment 2.1, denoted as 202A) according to embodiment 2. The driver circuit 202A is the same as that in embodiment 1.1 (FIG. 6) and is a switch-type driver capable of enabling the output terminal Po of any channel to generate the input voltage Vcom provided to the input terminal Pi. The driver Dr of each channel includes an analog switch SWA, and the state of each analog switch SWA.sub.# (where #=1 to N) is controlled by a corresponding control signal CTRL.sub.#.

[0081] In addition to the driver circuit 200A in FIG. 6, the driver circuit 202A further includes bypass circuits 290_1 to 290_N, and 292_1 to 292_N. The bypass circuit 290_# is disposed on an output side of the analog switch SWA.sub.#, and the bypass circuit 292_# is disposed on an input side of the analog switch SWA.sub.#.

[0082] In a situation where the driver Dr includes the analog switch SWA, the effects of noise suppression can be further enhanced by disposing the bypass circuit 292_# on the input side.

[0083] FIGS. 13(a) to (c) show circuit diagrams of exemplary structures of the analog switch SWA and the bypass circuits 290 and 292. The capacitor C.sub.# forming the bypass circuits 290 and 292 can include a gate capacitor of a metal-oxide-semiconductor (MOS) transistor. More specifically, the back gate, drain and source of a MOS transistor are connected to a ground line (or a power line), and the gate is connected to the input or the output of the analog switch SWA.

[0084] Further, the structure of the capacitor C.sub.# of the bypass circuits 290 and 292 is not limited, and a metal-insulator-metal (MIM) structure can also be used.

Embodiment 2.2

[0085] FIG. 14 shows a circuit diagram of a specific exemplary structure of the driver circuit (embodiment 2.2, denoted as 202B) according to embodiment 2. The driver circuit 202B is the same as that in embodiment 1.2 (FIG. 8), and is a binary driver that selectively outputs two values including a high-level voltage and a low-level voltage to the output terminal Po of each channel.

[0086] The driver Dr of each channel includes an inverter INV capable of outputting two values including a high-level voltage and a low-level voltage. The state of each inverter INV.sub.# (where #=1 to N) is controlled according to a corresponding control signal CTRL.sub.#.

[0087] In addition to the driver circuit 200B in FIG. 8, the driver circuit 202B further includes bypass circuits 290_1 to 290_N. The bypass circuit 290_# includes a capacitor connected to an output node of the inverter INV.sub.#.

Embodiment 2.3

[0088] FIG. 15 shows a circuit diagram of a specific exemplary structure of the driver circuit (embodiment 2.3, denoted as 202C) according to embodiment 2. The driver circuit 202C enables the output terminal Po of each channel to generate multi-value driving signals.

[0089] The driver Dr.sub.# of each channel includes an amplifier (a buffer) AMP.sub.# capable of outputting any voltage level, and a digital-to-analog converter (DAC) DAC.sub.#. The DAC DAC.sub.# converts a digital control signal (brightness data) CTRL.sub.# to an analog control signal, and provides the analog signal to the amplifier AMP.sub.#. The output level of each amplifier AMP.sub.# (where #=1 to N) is controlled by a corresponding control signal CTRL.sub.#.

[0090] In addition to the driver circuit 200C in FIG. 9, the driver circuit 202C further includes bypass circuits 290_1 to 290_N. The bypass circuit 290_# includes a capacitor connected to an output node of the amplifier AMP.sub.#.

(Layout)

[0091] FIG. 16 shows a layout diagram of the driver circuit 202A in FIG. 12. The driver circuit 202A is accommodated in a package having a first direction (x direction) as lengthwise and a second direction (y direction) as widthwise. The plurality of output terminals Po.sub.1 to PO.sub.N are disposed and aligned along an edge E1 extending in the first direction. The protection circuit 250_i is closed to corresponding output terminal Po.sub.i disposed in an input/output (I/O) region on the outer periphery of the chip. The clamp circuit 260_i, the bypass circuit 290_i, the driver Dr.sub.i (the analog switch SWA.sub.i), the bypass circuit 292_i, the clamp circuit 280_i and the level shifter LS corresponding to one output terminal Po.sub.i are disposed and aligned in the second direction.

[0092] The driver circuit 200A in FIG. 6 is designed such that the layout of the bypass circuits 290_1 to 290_N and 292_1 to 292_N in FIG. 16 can be omitted.

[0093] FIG. 17 shows a layout diagram of the driver circuit 202B in FIG. 14. The driver circuit 202B is accommodated in a package having a first direction (x direction) as lengthwise and a second direction (y direction) as widthwise. The plurality of output terminals Po.sub.1 to PO.sub.N are disposed and aligned along an edge E1 extending in the first direction. The protection circuit 250_i is closed to corresponding output terminal Po.sub.i disposed in an I/O region on the outer periphery of the chip. The clamp circuit 260_i, the bypass circuit 290_i, the driver Dr.sub.i (the inverter INV.sub.i) and the level shifter LS.sub.i corresponding to one output terminal Po.sub.i are disposed and aligned in the second direction.

[0094] The driver circuit 200B in FIG. 8 is designed such that the layout of the bypass circuits 290_1 to 290_N in FIG. 17 can be omitted.

[0095] FIG. 18 shows a layout diagram of the driver circuit 202C in FIG. 15. The driver circuit 202C is accommodated in a package having a first direction (x direction) as lengthwise and a second direction (y direction) as widthwise. The plurality of output terminals Po.sub.1 to PO.sub.N are disposed and aligned along an edge E1 extending in the first direction. The protection circuit 250_i is closed to corresponding output terminal Po.sub.i disposed in an I/O region on the outer periphery of the chip. The clamp circuit 260_i, the bypass circuit 290_i, the driver Dr.sub.i (the amplifier AMP.sub.i and the DAC DAC.sub.i) and the level shifter LS.sub.i corresponding to one output terminal Po.sub.i are disposed and aligned in the second direction.

[0096] The driver circuit 200C in FIG. 9 is designed such that the layout of the bypass circuits 290_1 to 290_N in FIG. 18 can be omitted.

[0097] The present invention is described by way of the embodiments above. A person skilled in the art should understand that these embodiments are illustrative examples, and any combination of the constituents or processing steps can exist in numerous variations, which are also encompassed within the scope of the present invention. Some of the variations are described below.

[0098] The second diodes SD used in the clamp circuits 260 and 280 are not limited to being Schottky diodes, and other devices having a forward voltage Vf smaller than those of first diodes forming the protection circuits 250 and 270 can be used.

[0099] In embodiment 1, the structure of the clamp circuit 260 (280) is described. In embodiment 2, the structures of the clamp circuit 260 (280) and the bypass circuit 290 (292) are described. However, the present invention is not limited to the description above. For example, a structure merely having the bypass circuit 290 (292) as an implementation form of the present invention is also considered effective.

[0100] The present invention is described by way of the embodiments above. It should be noted that, the non-limiting embodiments merely express principles and applications of the present invention. Without departing from the conceptual range of the present invention as defined in the claims, numerous variations and configurations can be made to the embodiments.