Thermoelectric cooling packages and thermal management methods thereof

Abstract

A method for managing a temperature of a device includes determining a temperature of a circuit or a package including the circuit, and selectively operating a thermoelectric semiconductor based on the determined temperature to adjust the temperature of the circuit or the package.

Claims

1. A method for managing a temperature of a device, the method comprising: determining a temperature of a package including a circuit; and selectively operating a thermoelectric semiconductor of the device based on the determined temperature to manage the temperature of the package, wherein the selectively operating comprises: not operating the thermoelectric semiconductor and maintaining a frequency of the circuit, based on the determined temperature being below a first temperature, not operating the thermoelectric semiconductor and decreasing the frequency of the circuit, based on the determined temperature being equal to or above the first temperature and below a second temperature, and operating the thermoelectric semiconductor and decreasing the frequency of the circuit, based on the determined temperature being equal to or above the second temperature and below a third temperature.

2. The method of claim 1, wherein the circuit includes at least one from among a logic chip and a memory unit, wherein the determining the temperature comprises determining a first measured temperature of the package, and wherein the operating the thermoelectric semiconductor further comprises, based on the first measured temperature of the package being greater than or equal to the second temperature, selectively supplying a voltage to the thermoelectric semiconductor to transfer heat generated by the package away from the package, and the method further comprising: determining a second measured temperature of the package; and stopping the operating the thermoelectric semiconductor based on the second measured temperature being below the second temperature.

3. The method of claim 1, wherein the circuit includes at least one from among a logic chip and a memory unit, the determining the temperature comprises sensing the temperature of the package, the first temperature corresponds to a minimum temperature, the second temperature corresponds to an intermediate temperature, and the third temperature corresponds to a maximum temperature.

4. The method of claim 1, wherein the device includes: a first board including a first area and a second area not overlapping the first area; and a second board, wherein the thermoelectric semiconductor is disposed between the first board and the second board at the first area of the first board configured to supply a voltage to the thermoelectric semiconductor, the package is disposed at the second area of the first board, and the first area and the second area are separated by a gap formed in the first board.

5. The method of claim 1, wherein the circuit includes a first chip and the package is a first package including a first package substrate, the first chip is mounted on the first package substrate, and is a logic chip, a second package is disposed on the first package and includes a second package substrate, and a second chip mounted on the second package substrate, the second chip being a memory chip, the thermoelectric semiconductor is embedded within the first package substrate, and includes p-type semiconductors and n-type semiconductors alternately embedded in the first package substrate and connected in series by a plurality of metal layers, a first voltage is applied to a bottom surface of one of the p-type semiconductors that is located at a first end of the thermoelectric semiconductor, and a second voltage is applied to a bottom surface of one of the n-type semiconductors that is located at a second end of the thermoelectric semiconductor.

6. The method of claim 1, wherein the circuit includes a first chip and the package is a first package including a first package substrate, the first chip is mounted on the first package substrate and is a logic chip including a temperature sensor, a second package is disposed on the first package and includes a second package substrate, and a second chip mounted on the second package substrate, the second chip being a memory device, the thermoelectric semiconductor is embedded within the first package substrate, and includes p-type semiconductors and n-type semiconductors alternately embedded in the first package substrate and connected in series by a plurality of metal layers, a first voltage is applied to a bottom surface of one of the p-type semiconductors that is located at a first end of the thermoelectric semiconductor, a second voltage is applied to a bottom surface of one of the n-type semiconductors that is located at a second end of the thermoelectric semiconductor, and the temperature sensor detects the temperature of the logic chip, and adjusts at least one from among the first voltage and the second voltage based on the detected temperature.

7. The method of claim 1, wherein the circuit includes a first chip and a second chip, the package includes a package substrate, the first chip is mounted on the package substrate and is a logic chip including a temperature sensor, the second chip is disposed over the first chip and coupled to the first chip, the second chip being a memory device, the thermoelectric semiconductor is embedded within the package substrate, and includes a plurality of p-type semiconductors and a plurality of n-type semiconductors alternately embedded within the package substrate and connected in series with a plurality of metal layers, and a first voltage is applied to a surface of one of the plurality of p-type semiconductors that is located at a first end of the thermoelectric semiconductor and a second voltage is applied to a surface of one of the plurality of n-type semiconductors that is located at a second end of the thermoelectric semiconductor.

8. The method of claim 1, wherein the operating the thermoelectric semiconductor further comprises: repetitively switching on and off a voltage supplied to the thermoelectric semiconductor.

9. A method for managing a temperature of a device, the method comprising: determining a temperature of a thermoelectric cooling package including a thermoelectric cooler and a circuit, the circuit being at least one from among a logic chip and a memory unit, the thermoelectric cooling package configured to operate in one of a plurality of performance modes comprising a hi ah performance mode an intermediate performance mode, and a low performance mode; determining, as the one of the plurality of performance modes of the thermoelectric cooling package, the high performance mode in which the circuit operates at a high clock speed; and selectively operating the thermoelectric cooler based on the determined high performance mode and based on the determined temperature to manage the temperature of the thermoelectric cooling package, wherein the selectively operating comprises one from among: based on the determined temperature being lower than a first temperature, not operating the thermoelectric cooler and operating the circuit, at the high clock speed, based on the determined temperature being higher than or equal to the first temperature and lower than a second temperature, not operating the thermoelectric cooler and operating in the intermediate performance mode by operating the circuit at an intermediate clock speed lower than the high clock speed, to lower the temperature of the thermoelectric cooling package, and based on the determined temperature being higher than or equal to the second temperature, transiently operating the thermoelectric cooler by repetitively turning on and turning off the thermoelectric cooler and operating in the low performance mode by operating the circuit at a low dock speed lower than the intermediate dock speed, to lower the temperature of the thermoelectric cooling package.

10. The method of claim 9, wherein the transiently operation the thermoelectric cooler further comprises: providing a voltage on signal and a voltage off signal to the thermoelectric cooler.

11. A method for managing a temperature of a device, the method comprising: determining a temperature of a package including a circuit, the circuit being a logic chip operable at one from among a first performance level and a second performance level lower than the first performance level; and selectively operating the package based on the determined temperature to manage the temperature of the package, wherein the selectively operating comprises selectively operating a thermoelectric semiconductor of the device by repetitively turning on and turning off the thermoelectric semiconductor to transfer heat out from the package, to adjust the temperature of the package to a certain level, and wherein the repetitively turning on and turning off the thermoelectric semiconductor comprises providing a voltage on signal and a voltage off signal, respectively, to the thermoelectric semiconductor, wherein the selectively operating further comprises, at the first performance level, operating the logic chip fixedly at a first clock speed, and repetitively turning on and turning, off the thermoelectric semiconductor by repetitively providing the voltage on signal and the voltage off signal, respectively, to the thermoelectric semiconductor, and at the second performance level, operating the logic chip alternatingly at the first clock speed and a second clock speed lower than the first clock speed and one irons among providing the voltage off signal to the thermoelectric semiconductor and providing the voltage on si anal and the voltage off signal to the thermoelectric semiconductor.

12. The method of claim 11, wherein the operating the logic chip at the second performance level comprises providing the voltage on signal and the voltage off signal by: providing the voltage on signal to the thermoelectric semiconductor based on the logic chip operating at the second clock speed; and providing the voltage off signal to the thermoelectric semiconductor based on the logic chip operating at the first clock speed.

13. The method of claim 11, wherein the logic chip is operable at a plurality of clock speeds comprising a maximum clock speed, a minimum clock speed, and an intermediate clock speed between the maximum clock speed and the minimum clock speed, the first clock speed corresponds to the maximum dock speed, the second dock speed corresponds to the minimum dock speed, and the operating the logic chip at the second performance level further comprises operating the logic chip alternatingly at the maximum clock speed, the minimum clock speed, and the intermediate clock speed, and providing the voltage on signal and the voltage off signal by supplying the voltage on signal to the thermoelectric semiconductor based on the logic chip operating at the minimum clock speed.

14. The method of claim 11, wherein the operating the logic chip at the second performance level further comprises providing the voltage on signal to the thermoelectric semiconductor based on a clock speed of the logic chip changing from the first clock speed to the second clock speed.

15. The method of claim 11, wherein the operating the logic chip at the second performance level further comprises providing the cottage on signal and the cottage off signal to the thermoelectric semiconductor by repetitively providing the cottage on signal synchronously with the operating the logic chip at the first clock speed and the second clock speed, respectively.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The inventive concept will become more apparent in view of the attached drawings and accompanying detailed description.

(2) FIG. 1 is a plan view illustrating a thermoelectric cooler according to exemplary embodiments of the inventive concept;

(3) FIG. 2A is a perspective view illustrating a thermoelectric couple of a thermoelectric cooler according to exemplary embodiments of the inventive concept;

(4) FIG. 2B is a perspective view illustrating a modified exemplary embodiment of FIG. 2A;

(5) FIGS. 3A through 3D are cross sectional views illustrating cooling actions of thermoelectric coolers according to exemplary embodiments of the inventive concept;

(6) FIGS. 4A through 4C are plan views illustrating examples of arrangement of a thermoelectric cooler according to exemplary embodiments of the inventive concept;

(7) FIG. 5A is a cross sectional view illustrating a thermoelectric cooling package according to exemplary embodiments of the inventive concept;

(8) FIG. 5B is a cross sectional view illustrating a cool action of a thermoelectric cooler in a thermoelectric cooling package according to exemplary embodiments of the inventive concept;

(9) FIGS. 5C and 5F are graphs illustrating a temperature variation of a thermoelectric cooling package according to exemplary embodiments of the inventive concept;

(10) FIGS. 5D and 5G are graphs illustrating variations of a clock frequency and voltage supplied to a thermoelectric cooler of a thermoelectric cooling package according to exemplary embodiments of the inventive concept;

(11) FIG. 5E is a flow chart illustrating a method of a feedback temperature control method of a thermoelectric cooling package according to exemplary embodiments of the inventive concept;

(12) FIGS. 5H to 5O are graphs illustrating variations of a clock frequency and voltage supplied to a thermoelectric cooler of a thermoelectric cooling package according to exemplary embodiments of the inventive concept;

(13) FIGS. 5P and 5Q are flow charts illustrating examples of dynamic temperature management according to exemplary embodiments of the inventive concept;

(14) FIGS. 6A and 6B are cross sectional views illustrating examples of applications of a thermoelectric cooling package according to exemplary embodiments of the inventive concept;

(15) FIG. 6C is a cross sectional view illustrating an equivalent thermal circuit of an exemplary application of a thermoelectric cooling package according to exemplary embodiments of the inventive concept;

(16) FIGS. 7A through 7D are cross sectional views illustrating modified exemplary embodiments of a thermoelectric cooling package according to exemplary embodiments of the inventive concept;

(17) FIG. 8A is a schematic block diagram illustrating an example of memory cards including a thermoelectric cooling package according to exemplary embodiments of the inventive concept; and

(18) FIG. 8B is a schematic block diagram illustrating an example of information processing systems including a thermoelectric cooling package according to exemplary embodiments of the inventive concept.

DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS

(19) The inventive concept will now be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the inventive concept are shown. The advantages and features of the inventive concept and methods of achieving them will be apparent from the following exemplary embodiments that will be described in more detail with reference to the accompanying drawings. It should be noted, however, that the inventive concept is not limited to the following exemplary embodiments, and may be implemented in various forms. Accordingly, the exemplary embodiments are provided only to disclose the inventive concept and let those skilled in the art know the category of the inventive concept. In the drawings, exemplary embodiments of the inventive concept are not limited to the specific examples provided herein and are exaggerated for clarity.

(20) The terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to limit the invention. As used herein, the singular terms a, an and the are intended to include the plural forms as well, unless the context clearly indicates otherwise. As used herein, the term and/or includes any and all combinations of one or more of the associated listed items. It will be understood that when an element is referred to as being connected or coupled to another element, it may be directly connected or coupled to the other element or intervening elements may be present.

(21) Similarly, it will be understood that when an element such as a layer, region or substrate is referred to as being on another element, it can be directly on the other element or intervening elements may be present. In contrast, the term directly means that there are no intervening elements. It will be further understood that the terms comprises, comprising,, includes and/or including, when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

(22) Additionally, the exemplary embodiment in the detailed description will be described with sectional views as ideal exemplary views of the inventive concept. Accordingly, shapes of the exemplary views may be modified according to manufacturing techniques and/or allowable errors. Therefore, the exemplary embodiments of the inventive concept are not limited to the specific shape illustrated in the exemplary views, but may include other shapes that may be created according to manufacturing processes. Areas exemplified in the drawings have general properties, and are used to illustrate specific shapes of elements. Thus, this should not be construed as limited to the scope of the inventive concept.

(23) It will be also understood that although the terms first, second, third etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, a first element in some exemplary embodiments could be termed a second element in other exemplary embodiments without departing from the teachings of the present invention. Exemplary embodiments of aspects of the present inventive concept explained and illustrated herein include their complementary counterparts. The same reference numerals or the same reference designators denote the same elements throughout the specification.

(24) Moreover, exemplary embodiments are described herein with reference to cross-sectional illustrations and/or plane illustrations that are idealized exemplary illustrations. Accordingly, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etching region illustrated as a rectangle will, typically, have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.

(25) [Exemplary Embodiment of Thermoelectric Cooler]

(26) FIG. 1 is a plan view illustrating a thermoelectric cooler according to exemplary embodiments of the inventive concept.

(27) Referring to FIG. 1, a thermoelectric cooler (hereinafter, referred to as TEC) 10 may be disposed on a substrate 20 on which a semiconductor device is mounted. The substrate 20 may be a printed circuit board, a computer main board, a mobile set board, or a memory module substrate that may provide a mounting portion 22 on which a semiconductor device such as a semiconductor chip or a semiconductor package is mounted. The TEC 10 may include at least one thermoelectric couple 12 which performs a cooling action by the Peltier effect. The at least one thermoelectric couple 12 may be disposed at or toward a side edge of the substrate 20. The thermoelectric couple 12 may include a pair of thermoelectric materials, for example, where one of the pair is made of a metal or a material that is different from the metal or the material used to make the other of the pair, or P-type and N-type semiconductors. The TEC 10 according to the present exemplary embodiment may include a thermoelectric semiconductor which has a more excellent cooling efficiency and faster operation speed than metal. For example, the TEC 10 may include the thermoelectric couple 12 having a P-type semiconductor 12p and an N-type semiconductor 12n. The TEC may include a plurality of the thermoelectric couples 12. The thermoelectric semiconductor may include BiTe, PbTe, FeSi, and/or SiGe.

(28) [Exemplary Embodiment of Thermoelectric Couple]

(29) FIG. 2A is a perspective view illustrating a thermoelectric couple of a thermoelectric cooler according to exemplary embodiments of the inventive concept. FIG. 2B is a perspective view illustrating a modified exemplary embodiment of FIG. 2A.

(30) Referring to FIG. 2A, the P-type semiconductor 12p and the N-type semiconductor 12n may arranged along an X direction to constitute one thermoelectric couple 12, and plural thermoelectric couples 12000 may constitute plural TECs. The plural thermoelectric couples 12000 are arranged along a Y direction. Since the TEC 10 includes the plural thermoelectric couples 12000, the TEC 10 may have improved heat exchange performance and capacity. The P-type semiconductor and the N-type semiconductor of adjacent thermoelectric couples of the plural thermoelectric couples 12000 in the Y direction may be conversely located. Thus, the P-type semiconductors and N-type semiconductors may be alternatingly arranged in the Y direction. The P-type semiconductor 12p and the N-type semiconductor 12n constituting one thermoelectric couple 12 may be connected to each other through a first metal layer 14. The P-type semiconductor 12p included in the thermoelectric couple 12 may be connected to the N-type semiconductor included in another of the plural thermoelectric couples 12000, adjacent to the thermoelectric couple 12 through a second metal layer 16. A voltage may be applied through the second metal layer connected to the first P-type semiconductor of the first thermoelectric couple of the plural thermoelectric couples 12000 and the second metal layer connected to the last N-type semiconductor of the last thermoelectric couple of the plural thermoelectric couples 12000. A moving direction of the heat passing through the TEC 10 may be varied according to polarity of the applied voltage as described with reference to FIGS. 3A through 3D.

(31) Referring to FIG. 2B, the P-type semiconductor 12p and the N-type semiconductor 12n adjacent to each other in the Y direction may constitute one thermoelectric couple 12, and the plural thermoelectric couples 12000 may be arranged along the Y direction to constitute the TEC 10. The P-type semiconductor and the N-type semiconductors of adjacent thermoelectric couples of the plural thermoelectric couples 12000 in the X direction may be conversely located. Thus, the P-type semiconductors and the N-type semiconductors may be alternatingly arranged along the Y direction. In another exemplary embodiment, X direction may be changed into the Y direction, and vice versa.

(32) The TEC 10 may be disposed on the substrate 20 in the state that the second metal layers are adjacent to the substrate 20 as illustrated in FIGS. 3A and 3B. Alternatively, the TEC 10 may be disposed on the substrate 20 in a manner so that the first metal layers 14 are adjacent to the substrate 20 as illustrated in FIGS. 3C and 3D. The TEC 10 may have a single layered structure as the present exemplary embodiment. Alternatively, the thermoelectric couples 12 may be stacked with a thermal conductive insulator (e.g. polyimide, silicon-boron nitride, or aluminum oxide ceramic) therebetween, so that the TEC 10 may have a multi-layered structure.

(33) [Operational Exemplary Embodiment of Thermoelectric Cooler]

(34) FIGS. 3A through 3D are cross sectional views illustrating cooling actions in thermoelectric coolers according to exemplary embodiments of the inventive concept. FIGS. 3A through 3D are cross sectional views taken along an X direction of FIG. 1. Arrows illustrated in drawings represent a main flow of heat.

(35) As illustrated in FIGS. 3A and 3B, when the TEC 10 is disposed on the substrate 20 in the manner so that the second metal layers 16 are adjacent to the substrate 20, the heat may be moved upwardly or downwardly along the TEC 10 according to the polarity of the applied voltage. For example, as illustrated in FIG. 3A, if a positive voltage is applied to the P-type semiconductor 12p and a negative voltage is applied to the N-type semiconductor 12n through the second metal layer 16, holes in the P-type semiconductor 12p may move toward a cathode (i.e. toward the first metal layer 14) and electrons in the N-type semiconductor 12n may move toward an anode (i.e. toward the first metal layer 14). The heat may be transferred from a bottom to a top of the TEC 10 by the flow of the electrons and the holes, thereby having heat absorption below the TEC 10 and heat radiation above the TEC 10. Alternatively, as illustrated in FIG. 3B, if a negative voltage is applied to the P-type semiconductor 12p and a positive voltage is applied to the N-type semiconductor 12n through the second metal layer 16, holes in the P-type semiconductor 12p may move toward a cathode (i.e. toward the second metal layer 16 being in contact with the P-type semiconductor 12p) and electrons in the N-type semiconductor 12n may move toward an anode (i.e. toward the second metal layer 16 being in contact with the N-type semiconductor 12n). The heat may be transferred from the top to the bottom of the TEC 10 by the flow of the electrons and the holes, thereby having heat absorption above the TEC 10 and heat radiation below the TEC 10. Metal vias 24 may be further provided to be connected to the second metal layers 16. The metal vias 24 may penetrate the substrate 20. The metal vias 24 may be used as heat transmission paths to improve heat absorption/radiation effects. The metal vias 24 may also used as voltage supply paths.

(36) As illustrated in FIGS. 3C and 3D, the TEC 10 may be disposed on the substrate so that the first metal layers 14 are adjacent to the substrate 20. As illustrated in FIG. 3C, if a negative voltage is applied to the P-type semiconductor 12p and a positive voltage is applied to the N-type semiconductor 12n, the heat may be downwardly transferred along the TEC 10 to generate the heat absorption above the TEC 10 and the heat radiation below the TEC 10. Conversely, as illustrated in FIG. 3D, if a positive voltage is applied to the P-type semiconductor 12p and a negative voltage is applied to the N-type semiconductor 12n, the heat may be upwardly transferred along the TEC 10 to have heat radiation above the TEC 10 and heat absorption below the TEC 10. A heat via 25 may further be provided to be connected to the first metal layer 14 and to penetrate the substrate 20. Thus, the heat absorption/radiation effects may be improved. In some exemplary embodiments, a size of the heat via 25 may be equal to or greater than a size of the first metal layer 14, thereby maximizing heat transmission amount of the heat transmitted down the TEC 10.

(37) [Example of Arrangement of Thermoelectric Cooler]

(38) FIGS. 4A through 4C are plan views illustrating examples of arrangement of a thermoelectric cooler according to exemplary embodiments of the inventive concept.

(39) Referring to FIG. 4A, the TEC 10 may be disposed on the substrate 20 at both sides of the mounting portion 22. For example, a first TEC 10a may be disposed on or toward one side edge of the substrate 20 and a second TEC 10b may be disposed on or toward another side edge of the substrate opposite to the one side edge. At least one of the first TEC 10a and the second TEC 10b may be illustrated in FIG. 2A or FIG. 2B. As illustrated in FIG. 3A, the second metal layer 16 of the at least one of the first TEC 10a and the second TEC 10b may be adjacent to the substrate 20. Alternatively, as illustrated in FIG. 3C, the first metal layer 14 of the at least one of the first TEC 10a and the second TEC 10b may be adjacent to the substrate 20. The first TEC 10a may be operated in conjunction with the second TEC 10b. Alternatively, the first TEC 10a may be operated independently of the second TEC 10b. For example, one of the first and second TECs 10a and 10b may be selectively operated.

(40) Referring to FIG. 4B, a number of TECs may extend along or be disposed about an edge of the substrate 20. The TECs may include the P-type semiconductors and the N-type semiconductors which are alternatingly arranged in or along the edge of the substrate 20. The TECs may have a loop shape surrounding the mounting portion 22. The P-type semiconductors and the N-type semiconductors may be arranged along the edge of the substrate 20 to constitute one row or a plurality of rows (e.g. two rows).

(41) Referring to FIG. 4C, the TEC 10 may include a plurality of TECs 10a, 10b, 10c, and 10d which are arranged along the edge of the substrate 20 to surround the mounting portion 22. For example, a first TEC 10a may be disposed on a left side edge of the substrate 20, and second, third and fourth TECs 10b, 10c, and 10d may be disposed on other side edges of the substrate 20 in a clockwise direction. The first to fourth TECs 10a, 10b, 10c, and 10d may be operated simultaneously or individually.

(42) The TEC 10 described with reference to the above drawings may be combined with a semiconductor chip or a semiconductor package mounted on the mounting portion 22 to constitute a thermoelectric cooling package. Alternatively, the TEC 10 may be embedded in a semiconductor chip or a semiconductor package to constitute a thermoelectric cooling package. Various exemplary embodiments of the thermoelectric cooling package will be described hereinafter.

(43) [Exemplary Embodiment of Thermoelectric Cooling Package]

(44) FIG. 5A is a cross sectional view illustrating a thermoelectric cooling package according to exemplary embodiments of the inventive concept. FIG. 5B is a cross sectional view illustrating a cool action of a thermoelectric cooler in a thermoelectric cooling package according to exemplary embodiments of the inventive concept.

(45) Referring to FIG. 5A, a thermoelectric cooling package 1 may include the substrate 20 (hereinafter, referred to as first package substrate) on which the TEC 10 is disposed, a logic chip 32 mounted on the first package substrate 20, and a plurality of memory chips 42 mounted on a second package substrate 40. Thus, the thermoelectric cooling package 1 may include a structure including a package-on-package 80 (hereinafter, referred to as TOP) combined with the TEC 10. The thermoelectric cooling package 1 may further include a heat sink 70 to effectively discharge heat.

(46) The logic chip 32 may be mounted on a top surface of the first package substrate 20 in a face down state or a face up state. The logic chip 32 may be electrically connected to the first package substrate 20 through bumps 34. The logic chip 32 may be molded by a first molding layer 36. By insulating adhesion layers 43, the memory chips 42 may adhered to each other and adhered to a top surface of the second package substrate 40. The memory chips 42 may be electrically connected to the second package substrate 40 through bonding wires 44. The memory chips 42 may be molded by a second molding layer 46. The first package substrate 20 and the second package substrate 40 may be electrically connected to each other through solder balls 38. At least one first external terminal 39 may adhered to a bottom surface of the first package substrate 20. The at least one first external terminal 39 may connect the thermoelectric cooling package 1 to an external device (e.g. a reference numeral 90 of FIG. 5B). The POP 80 structure may be replaced with another type of package or another type of semiconductor chip such as a package-in-package (PIP), a system-in-package (SIP), a system-on-chip (SOC), a chip-on-board (COB), a multi-chip package (MCP) or a board-on-chip (BOC). For example, a CPU or application processor (AP) may be coupled to the TEC 10 to constitute the thermoelectric cooling package 1.

(47) The TEC 10 may include the P-type semiconductor 12p and the N-type semiconductor 12n which are combined with each other by the first metal layer 14. Each of the P-type semiconductor 12p and the N-type semiconductor 12n may be connected to the second metal layer 16. The TEC 10 may occupy or may be disposed along a side edge of the first package substrate 20 in so that the second metal layers 16 are adjacent to the first package substrate 20 and the first metal layer 14 is connected to the heat sink 70. Metal vias 24 may be provided to the first package substrate 20 to be connected to the second metal layers 16, and second external terminals 29 may adhered to the bottom surface of the first package substrate 20 to be connected to the metal vias 24.

(48) The heat sink 70 may be disposed on the TEC 10 to further extend onto the second molding layer 46. A thermal interface layer (TIM) 60 may be provided between the second mold layer 46 and the heat sink 70. The thermoelectric cooling package 1 may further include a temperature sensor 50 sensing a temperature of thermoelectric cooling package 1. The temperature sensor 50 may be embedded within the logic chip 32 or the first package substrate 20. In the thermoelectric cooling package 1, since a heat source may mainly be the POP 80, a temperature of the POP 80 may represent the temperature of the thermoelectric cooling package 1. Accordingly, the temperature of the POP 80 will be regarded as the temperature of the thermoelectric cooling package 1 unless stated otherwise, hereinafter.

(49) Referring to FIG. 5B, the thermoelectric cooling package 1 may be electrically connected to a board 90 through the external terminals 29 and 39. The board 90 may include a memory module board, a mobile set board, and/or a computer main board. The thermoelectric cooling package 1 may be operated by a signal applied through the board 90. Heat may be generated from mainly the POP 80 according to the operation of the thermoelectric cooling package 1. The heat generated from the POP 80 may be discharged through the heat sink 70 and the TEC 10 may be operated for more effectively discharging heat.

(50) In some exemplary embodiments, the TEC 10 may be operated by applying a positive voltage to the P-type semiconductor 12p and applying a negative voltage to the N-type semiconductor 12n. The voltages may be directly applied to the second metal layers 160 or be applied to the second metal layers 160 through the second external terminals 39 and the metal vias 24. Under the condition of applying the voltages, the heat radiation may be generated above the TEC 10 and the heat absorption may be generated below the TEC 10. Thus, the heat generated from the POP 80 may be transferred into the TEC 10 along the first package substrate 20, and then the heat may be upwardly transferred along the TEC 10 to be discharged through the heat sink 70. The heat may not only be moved to the heat sink 70 through the TEC 10, but be directly moved to the heat sink 70 to be released. In other exemplary embodiments, a negative voltage may be applied to the P-type semiconductor 12p and a positive voltage may be applied to the N-type semiconductor 12n, so that the heat absorption may above the TEC 10 and the heat radiation may be generated below the TEC 10. In this case, the heat may be downwardly moved along the TEC 10 to be discharged through the metal vias 24 and the board 90.

(51) Cooling the POP 80 using the TEC 10 may be continuously performed during the operation of the POP 80 or be transiently performed at need, i.e., transiently performed based on need. In other words, the POP may be selectively operated depending on need. The continuous operation of the TEC 10 may render the TEC 10 itself as heat source to drop cooling capacity and/or may induce a deformation of or thermal stress in the TEC 10 due to temperature difference between top and bottom ends thereof. According to exemplary embodiment, the TEC 10 may be performed transiently to solve the problems described above. Alternatively, a clock speed of the logic chip 32 may be reduced to cool the POP 80. Thus, dynamic thermal management (DTM) of the thermoelectric cooling package 1 may adopt a hardware method using the TEC 10 and a software method using the control of the clock speed.

(52) The DTM of the thermoelectric cooling package 1 may be performed using the software method of reducing the clock speed of the logic chip 32 when the temperature of the POP 80 increases and increasing the clock speed of the logic chip 32 when the temperature of the POP 80 decreases. In this case, the clock speed (clock frequency) of the logic chip 32 may be changed to decrease performance of the thermoelectric cooling package 1. Accordingly, the DTM according to the present exemplary embodiment may adopt the hardware method, or a mixed method of the software method and the hardware method.

(53) [Example of DTM]

(54) FIGS. 5C and 5F are graphs illustrating a temperature variation of a thermoelectric cooling package according to exemplary embodiments of the inventive concept. FIGS. 5D and 5G are graphs illustrating variations of a clock frequency and voltage supplied to a thermoelectric cooler of a thermoelectric cooling package according to exemplary embodiments of the inventive concept. FIG. 5E is a flow chart illustrating a method of a feedback temperature control method of a thermoelectric cooling package according to exemplary embodiments of the inventive concept.

(55) Referring to FIGS. 5B through 5D, when the temperature of the POP 80 is increased by the use of the thermoelectric cooling package 1, the dynamic thermal management may be realized by the hardware method which includes operating the TEC 10 by supplying voltages to reduce the temperature of the POP 80 (FIG. 5C). In this case, the clock speed of the logic chip 32 may not be changed to maintain the performance of the thermoelectric cooling package 1 (FIG. 5D). As described above, when the hardware method is adopted, the TEC 10 may receive a transient voltage supply for transient operation.

(56) In some exemplary embodiments, as illustrated in FIG. 5E, the temperature of the POP 80 measured by the temperature sensor 50 may be compared with a target temperature (or a target temperature range) (S10). If the measured temperature is higher than the target temperature (or the target temperature range), the TEC 10 receives the voltage supply (S20) to operate the TEC 10. If the measured temperature is lower than the target temperature (or the measured temperature is within or lower than the target temperature range), the operation of the TEC 10 is stopped by stopping the voltage supply (S30). Thus, the temperature of the POP 80 may be changed to be within the permissible range (S40). The transient operation of the TEC 10 described above may be performed once, or several times as illustrated in FIG. 5C. As a result, the temperature of the POP 80 may be changed at a temperature equal to or lower than the target temperature. The target temperature means a permissible maximum temperature at which the thermoelectric cooling package 1 is not overheated. The target temperature range means a temperature range within which it is possible to operate the thermoelectric cooling package 1 normally. In other exemplary embodiments, the TEC 10 may be continuously operated to suppress a temperature increase of the POP 80. As described above, the DTM may adopt the hardware method and the TEC 10 may be transiently or continuously operated.

(57) Referring to FIGS. 5F and 5G, the software method and the hardware method may be mixed to perform the DTM. For example, when a high performance of the POP 80 is not required, the clock speed of the logic chip 32 is reduced to lower the temperature of the POP 80 without operating the TEC 10 (A). When the high performance of the POP 80 is required, the TEC 10 may receive a transient voltage supply for transient operation, to reduce the temperature of the POP 80 without the reduction of the clock speed (B).

(58) [Other Examples of DTM]

(59) FIGS. 5H to 5O are graphs illustrating variations of a clock frequency and voltage supplied to a thermoelectric cooler of a thermoelectric cooling package according to exemplary embodiments of the inventive concept.

(60) Referring to FIG. 5H, the software method and the hardware method may be performed simultaneously. For example, the clock speed of the logic chip 32 may be reduced and the TEC 10 may be operated at the same time, thereby rapidly reducing the temperature of the POP 80. The reduction of the clock speed and the operation of the TEC 10 may be transiently performed.

(61) Referring to FIG. 5I, the clock speed of the logic chip 32 may be reduced from a maximum to a minimum or a medium to decrease the temperature of the POP 80. When the clock speed of the logic chip 32 is reduced to a medium, the temperature of the POP 80 may be within the permissible range. Therefore, the TEC 10 may receive a transient voltage supply for transient operation, to decrease the temperature of the POP 80 in case that the clock speed of the logic chip 32 may be reduced to a minimum.

(62) Referring to FIG. 5J, the clock speed of the logic chip 32 may be transiently reduced to from a maximum to a minimum or a medium during the operations of the logic chip 80 without much decrease in performance of the POP 80. If the temperature of the POP 80 is not within the permissible range, voltage may be additionally supplied to the TEC 10 for transient operation of the TEC 10. This supplementary operation of the TEC 10 may decrease the temperature of the POP 80 without additional decrease of the clock speed thereof. Alternatively, the TEC 10 may also receive a transient voltage supply for transient operation, even though the clock speed of the logic chip 32 is reduced to a medium.

(63) Referring to FIG. 5K, the clock speed of the logic chip 32 may be reduced concurrently with the transient operation of the TEC 10, which decreases the temperature of the POP 80. In this case, a supply time of voltage to the TEC 10 may be longer than a duration time of the low clock speed of the logic chip 30. According to exemplary embodiment, the performance of the thermoelectric package 1 may be maintained with minimum fluctuation of the clock speed of the logic chip 32.

(64) Referring to FIG. 5L, the POP 80 may be cooled by transient operation of the TEC 10 without intentional reduction of the clock speed of the logic chip 32. In an exemplary embodiment, there may be a single TEC 10 or may be a plurality of TECs. For example, the clock speed of the logic chip 32 may be kept at a high state (C) and then changed up and down (D). In the fluctuation state D of the clock speed, the TEC 10 may receive a transient voltage supply for transient operation, to decrease the temperature of the POP 80 when the clock speed is kept high. In the high state C of the clock speed, the TEC 10 may be transiently operated (I) or not operated (D). For example, the TEC 10 may be transiently operated if the temperature of the POP 80 increases to be greater than the permissible range. Alternatively, the TEC 10 may be not operated if the temperature of the POP 80 is within the permissible range.

(65) Referring to FIG. 5M, the high clock speed of the logic chip 32 may be synchronous with the voltage supply to the TEC 10 to cool the POP 80 without intentional drop of the clock speed thereof. As an exemplary embodiment, a transient voltage may be supplied to the TEC 10 when the clock speed of the logic chip 32 is high, and the voltage supplied to the TEC 10 may be removed or no voltage may be supplied to the TEC 10 when the clock speed of the logic chip 32 is low. Alternatively, if the temperature of the POP 80 is within the permissible range, the voltage supplied to the TEC 10 may be removed or no voltage may be supplied to the TEC 10 even though the clock speed of the logic chip 32 is high.

(66) According to FIG. 5N, the POP 80 may be cooled by clock speed drop of the logic chip 32 and the transient operation of the TEC 10. The TEC 10 may be supplied with different magnitudes of voltage. For example, the magnitude of voltage when the clock speed is decreased to a medium may be smaller than that of voltage when the clock speed is lowered to a minimum. When the clock speed of the logic chip 32 is decreased to a first medium (mid1), the TEC 10 may be supplied with a first voltage value (on1). When the clock speed of the logic chip 32 is lowered to a second medium (mid2) smaller than the first medium (mid1), the TEC 10 may be supplied with a second voltage value (on2) greater than the first voltage value (on1). Both of the first voltage value (on1) and the second voltage value (on2) may be smaller than a voltage value (on) supplied to the TEC 10 when the clock speed of the logic chip 32 is decreased to minimum. As such, the magnitude of voltage may be inversely proportional to the clock speed.

(67) According to FIG. 5O, the POP 80 may be cooled by the transient operation of the TEC 10 without the intentional drop of the clock speed of the logic chip 32. The TEC 10 may be supplied with different magnitudes of voltage. For example, the magnitude of voltage when the clock speed is decreased to a medium may be smaller than that of voltage when the clock speed is increased to a maximum. When the clock speed of the logic chip 32 is decreased to a first medium (mid1), the TEC 10 may be supplied with a first voltage value (on1). When the clock speed of the logic chip 32 is lowered to a second medium (mid2) smaller than the first medium (mid1), the TEC 10 may be supplied with a second voltage value (on2) smaller than the first voltage value (on1). Both of the first voltage value (on1) and the second voltage value (on2) may be smaller than a voltage value (on) supplied to the TEC 10 when the clock speed of the logic chip 32 is increased to a maximum. As such, the magnitude of voltage may be proportional to the clock speed.

(68) The exemplary embodiments of DTM may be implement in the thermoelectric package 1. Alternatively, the exemplary embodiments of DTM may be adopted to electronic devices such as mobile phones and display apparatus, e.g., LCD, PDP, OLED, AMOLED, etc., which are coupled with the thermoelectric package 1. In other exemplary embodiments, the DTM may be applicable to control temperature of diverse controllers including temperature controllers.

(69) [Example of DTM Algorithm]

(70) FIG. 5P is a flow chart illustrating examples of DTM according to exemplary embodiments of the inventive concept.

(71) Referring to FIG. 5P, the thermoelectric cooling package 1 may be thermally managed with multi-stage temperature control as follows. According to exemplary embodiments of the inventive concept, a minimum temperature Tmin may be a temperature of the thermoelectric cooling package 1 corresponding to the minimum clock speed of the logic chip 32. Similarly, a maximum temperature Tmax and a medium temperature Tmid may be temperatures of the thermoelectric cooling package 1 corresponding to the maximum and medium clock speeds of the logic chip 32, respectively.

(72) At an operation S110, the thermoelectric cooling package 1 may be operated during the maximum performance level of the logic chip 32. For example, the thermoelectric cooling package 1 may be operated with the maximum clock speed of the logic chip 32.

(73) At an operation S120, a temperature of the thermoelectric cooling package 1 may be first measured in a first temperature sensing. The temperature of the thermoelectric cooling package 1 may be measured through the temperature sensor 50. After the operation S120, an operation S130 may be performed or an operation S125, and the feedback temperature control described in FIG. 5E, may further be performed before the operation S130.

(74) At the operation S130, operation conditions of the thermoelectric cooling package 1 may be maintained when the temperature T of the thermoelectric cooling package 1 is less than the Tmin. Alternatively, the thermoelectric cooling package 1 may be cooled through both the transient operation of the TEC 10 and the reduction of the clock speed of the logic chip 32 when the T is greater than the Tmin. The operation S130 may be divided into operations S131 to S134 described below.

(75) At the operation S131, the TEC 10 may not be operated and the clock speed of the logic chip 32 may not be changed when the T is less than the Tmin. In this case, the thermoelectric cooling package 1 may be operated during the maximum performance level of the logic chip 32 like in the operation S110.

(76) At the operation S132, the thermoelectric cooling package 1 may be cooled through the transient operation of the TEC 10 when the T is in the range from the Tmin to the Tmid. According to some exemplary embodiments, the clock speed of the logic chip 32 may be maintained so that thermoelectric cooling package 1 may be operated during the maximum performance level of the logic chip 32 at the operation S132.

(77) At the operation S133, the TEC 10 may be transiently operated and the clock speed of the logic chip 32 may be reduced when the T is in the range from the Tmid to the Tmax.

(78) At the operation S134, the TEC 10 may be transiently operated and the clock speed of the logic chip 32 may be reduced when the T is greater than the Tmax.

(79) At an operation S140, there may be temperature measurement of the thermoelectric cooling package 1 in a second temperature sensing, which is passed through the operations S132, S133 and S134. After the operation S140, an operation S150 may be performed or an operation S145, the feedback temperature control described in FIG. 5E, may further be performed before the operation S150.

(80) At the operation S150, the thermoelectric cooling package 1 may be returned to the operation S110 when the T is less than the Tmin. Alternatively, the thermoelectric cooling package 1 may be cooled through both the transient operation of the TEC 10 and the drop of the clock speed of the logic chip 32 when the T is higher than the Tmin. The operation S150 may be divided into operations S151 to S154 described below.

(81) At the operation S151, the voltage may no longer be applied to the TEC 10 when the T is less than the Tmin. In this case, the maximum clock speed of the logic chip 32 may be maintained such that the thermoelectric cooling package 1 may be operated during the maximum performance level of the logic chip, like in the operation S110. Meanwhile, the clock speed of the logic chip 32 may be increased to the maximum and then the thermoelectric cooling package 1 may be operated in full speed when the clock speed of the logic chip 32 is lower than the maximum.

(82) At the operation S152, the thermoelectric cooling package 1 may be cooled through the transient operation of the TEC 10 when the T is in the range from the Tmin to the Tmid. According to some embodiments, the clock speed of the logic chip 32 may be maintained.

(83) At the operation S153, the TEC 10 may be transiently operated and the clock speed of the logic chip 32 may be drop when the T is in the range from the Tmid to the Tmax.

(84) At the operation S154, the voltage applied to the thermoelectric cooling package 1 may be cut off when the T is greater than the Tmax.

(85) According to some exemplary embodiments, the Tmid may not be defined. In this case, one of the operations S132 and S133 may be excluded and one of the operations S152 and S153 may be excluded. For example, the operation S130 may include the operations S131, S133 and S134 except the operation S132 and the operation S150 may include the operations S151, S153 and S154 without the operation S153. As another example, the operation S130 may include the operations S131, S132 and S134 except the operation S133 and the operation S150 may include the operations S151, S152 and S154 without the operation S152.

(86) [Another Example of DTM Algorithm]

(87) FIG. 5Q is a flow charts illustrating examples of dynamic temperature management according to exemplary embodiments of the inventive concept.

(88) Referring to FIG. 5Q, if the temperature of the thermoelectric cooling package 1 during the operation of the logic chip 32 at full maximum speed, increases to a range from the Tmin to the Tmid, the clock speed of the logic chip 32 may be decreased (S132a). If the temperature T of the thermoelectric cooling package 1 thermally managed in the operation S130 is deposed between the Tmin and the Tmid, the clock speed of the logic chip 32 may be decreased (S152a). According to some exemplary embodiments, the thermoelectric cooling package 1 may be cooled through the decrease of the clock speed of the logic chip 32 without the operation of the TEC 10 at the operations S132a and S152a. The description of features that are the same as or similar to those in FIG. 5P may apply to this exemplary embodiment of FIG. 5Q.

(89) [Applications of Thermoelectric Cooling Package]

(90) FIGS. 6A and 6B are cross sectional views illustrating examples of applications of a thermoelectric cooling package according to exemplary embodiments of the inventive concept. FIG. 6C is a cross sectional view illustrating an equivalent thermal circuit of an exemplary application of a thermoelectric cooling package according to exemplary embodiments of the inventive concept.

(91) Referring to FIG. 6A, the thermoelectric cooling package 1 may be used in a handheld mobile electronic device such as a mobile phone, a portable multimedia player (PMP) and/or a portable tablet. For example, the thermoelectric cooling package 1 may be mounted on a mobile set board 90 to be installed between an upper casing 102 and a lower casing 104. When the POP 80 may be operated for performing various functions of the mobile phone, the POP 80 may be operated. The logic chip 32 may include an application processor (AP) which is capable of operating for driving the thermoelectric cooling package 1, and at least one of the memories 142 may include a DRAM as a working memory of the logic chip 32. When the thermoelectric cooling package 1 is operated, the heat generated from the POP 80 may be mainly transmitted to the upper casing 102 so that the upper casing 102 may become hotter than a reference temperature or target temperature. Since the mobile phone is grasped by a user, the reference temperature may mean a maximum temperature (e.g. about 45 C.) at which the user can comfortably endure when the user grasps the mobile phone. The reference temperature may be measured by the temperature sensor 50. For example, when the temperature measured by the temperature sensor 50 may be equal to or higher than a predetermined value, it may be predicted that the temperature of the upper casing 102 will be equal or higher than the reference temperature. Alternatively, the temperature of the upper casing 102 may be measured by a temperature sensor 106 adhered to the upper casing 102, and/or the temperature of the lower casing 104 may be measured by a temperature sensor 108 adhered to the lower casing 104. The reference temperature may be directly measured by at least one of the sensors 50, 106 and 108. Alternatively, the reference temperature may be set based on some criteria described later with reference to FIG. 6C.

(92) If the temperature of the upper casing 102 is equal to or higher than the reference temperature, a negative voltage may be applied to the P-type semiconductor 12p and a positive voltage may be applied to the N-type semiconductor 12n. The TEC 10 may be transiently or continuously operated the voltages are supplied. Thus, the heat may downwardly flow along the TEC 10, so the temperature of the upper casing 102 may become lower than the reference temperature. The heat may be more effectively transmitted to the TEC 10 from the upper casing 102 by the heat sink 70.

(93) As other examples, the reference temperature may be a mixed temperature of the POP 80 and the upper casing 102. According to exemplary embodiments included this application, the reference temperature or temperature measuring area may be not restricted to a specific point.

(94) The first package substrate 20 may include a first portion on which the logic chip 32 is mounted, and a second portion on which the TEC 10 is mounted. A boundary between the first portion and the second portion of the first package substrate 20 may be cut so that there is a gap 26 and so that the first package substrate 20 may be divided into two portions. The gap 26 may block a heat flow toward the POP 80 through the first package substrate 20. Alternatively, the first package substrate 20 may not be divided to two portions. In this case, the heat downwardly flowing along the TEC 10 may be transmitted to the mobile set board 95 mainly through the metal vias 24, thereby minimizing the heat flow toward the POP 80.

(95) Referring to FIG. 6B, the thermoelectric cooling package 1 may be combined with a liquid crystal display 110. The liquid crystal display 110 may include a liquid crystal display portion 112 and a backlight unit 114, and the thermoelectric cooling package 1 may be installed on a back side of the liquid crystal display 110. When the thermoelectric cooling package 1 absorbs heat from the liquid crystal display 110, a negative voltage may be applied to the P-type semiconductor 12p and a positive voltage may be applied to the N-type semiconductor 12n, thereby transiently or continuously operating the TEC 10. Thus, the heat generated from the liquid crystal display 110 may be transmitted to mainly a board 90 through the TEC 10. The temperature of the liquid crystal display 110 may be measured by the temperature sensor 50 included in the thermoelectric package 1 or a temperature sensor 107 disposed in the liquid crystal display 10. The temperature sensor 107 may be embedded or attached to the liquid crystal display 10. The first package substrate 20 may or may not include the gap 26. The present exemplary embodiment is not limited to the liquid crystal display 110. The present embodiment may apply to other flat panel displays such as a plasma display panel (PDP), an active matrix organic light emitting diode (AMOLED), and/or a passive matrix organic light emitting diode (PMOLED).

(96) Referring to FIG. 6C, assuming that the thermoelectric cooling package 1 mounted on the mobile set board 90 is disposed between the upper casing 102 and the lower casing 104. In some exemplary embodiments, the logic chip 32 may include the temperature sensor 50 and the casings 102 and 104 may not include temperature sensors.

(97) The temperature sensor 50 may measure an internal temperature T.sub.J of the logic chip 32. A surface temperature T.sub.B of the upper casing 102 and/or a surface temperature T.sub.C of the lower casing 104 may be calculated by a thermal circuit modeling. For example, a relationship of the surface temperature T.sub.B of the upper casing 102 and the surface temperature T.sub.J of the lower casing 104 may be given by an Equation 1 below.
T.sub.J=T.sub.B+R.sub.JBP.sub.JB[Eq. 1]

(98) wherein the R.sub.JB (Watt) is a thermal resistance between the temperature sensor 52 and the surface of the upper casing 102, and the P.sub.JB ( C./Watt) is a dissipation heat to the surface of the upper casing 102.

(99) A relationship of the surface temperature T.sub.C of the lower casing 104 and the surface temperature T.sub.J of the lower casing 104 may be represented by an Equation 2 below.
T.sub.J=T.sub.C+R.sub.JCP.sub.JC[Eq. 2]

(100) wherein the R.sub.JC is a thermal resistance between the temperature sensor 52 and the surface of the lower casing 104, and the P.sub.JC is a dissipation heat to the surface of the lower casing 104.

(101) Considering the Equations 1 and 2, it may be possible to measure temperatures of various portions as well as the logic chip 32 through the heat transfer modeling. In other words, it may be easily set up reference temperatures of diverse sections in electronic devices. For example, if the upper casing 102 is replaced by a display of the mobile phone, a surface temperature of the display may be measured.

(102) The thermoelectric cooling package 1 may be operated in multiple performance modes according to various reference temperatures. As one example, the thermoelectric cooling package 1 may be operated in maximum performance mode where the clock speed of the logic chip 32 is set to the maximum, in minimum performance mode where the clock speed of the logic chip 32 is set to the minimum, or in medium performance mode where the clock speed of the logic chip 32 is set to the medium.

(103) In some exemplary embodiments, it is assumed that the thermoelectric cooling package 1 operates in the maximum performance mode. If the temperature of thermoelectric cooling package 1 is lower than a first reference temperature T1, the clock speed of the logic chip 32 may be maintained in the maximum state. Whereas, if the thermoelectric cooling package 1 is heated and its temperature is increased greater than the T1, the thermoelectric cooling package 1 may be operated in the medium performance mode changed from the maximum performance mode.

(104) When the thermoelectric cooling package 1 is operated in the medium performance mode and its temperature is lower than a stable temperature Ts (<T1), the thermoelectric cooling package 1 may operated in the maximum performance mode changed from the medium performance mode. Alternatively, when the temperature of thermoelectric cooling package 1 is in the range from the Ts to a second reference temperature T2 (>T1), the operation state of the thermoelectric cooling package 1 may maintained so that the medium performance mode may continue. If the thermoelectric cooling package 1 is heated and then its temperature is increased greater than the T2, the thermoelectric cooling package 1 may operated in the minimum performance mode changed from the medium performance mode.

(105) In case that the thermoelectric cooling package 1 is operated in the minimum performance mode and its temperature is lower than the Ts, the thermoelectric cooling package 1 may operated in the maximum performance mode changed from the minimum performance mode. Alternatively, if the temperature of thermoelectric cooling package 1 is in the range from the Ts to T2, the thermoelectric cooling package 1 may operated in the medium performance mode changed from the minimum performance mode. If when the temperature of thermoelectric cooling package 1 is in the range from the T2 to a third reference temperature T3 (>T2) which corresponds to the maximum permissible temperature T.sub.JMAX of the logic chip 32, the operation state of the thermoelectric cooling package 1 may maintained so that the minimum performance mode may go on. If the thermoelectric cooling package 1 is heated and its temperature increased more than the T3, the power applied to the thermoelectric cooling package 1 may be released.

(106) The reference temperatures Ts, T1, T2 and T3 may be given by following Equations 3 to 6.
T.sub.ST.sub.B+R.sub.JBP.sub.JB or T.sub.C+R.sub.JCP.sub.JC[Eq. 3]
T1T.sub.B+R.sub.JBP.sub.JB or T.sub.C+R.sub.JCP.sub.JC[Eq. 4]
T2T.sub.JMAX[Eq. 5]
T3T.sub.JMAX[Eq. 6]

(107) Alternatively, if the thermoelectric cooling package 1 operates in the maximum performance mode and then its temperature is increased above the T1, the thermoelectric cooling package 1 may be cooled below the T1 due to the transient operation of the TEC 10. In this case, the maximum performance mode of the thermoelectric cooling package 1 may be maintained. Similarly, if the thermoelectric cooling package 1 operating in the medium performance mode is heated and then its temperature is increased between the Ts and T2 or above than the T2, the thermoelectric cooling package 1 may be cooled due to the transient operation of the TEC 10. Therefore, the thermoelectric cooling package 1 may be maintained in the medium performance mode or maximum performance mode. According to the exemplary embodiment, even though the thermoelectric cooling package 1 may be heated above the T3, there may not be needed to stop the supply of the power to the TEC 10 because the thermoelectric cooling package 1 may be cooled below the T3 due to the transient operation of the TEC 10.

(108) The descriptions of features that are the same as or similar to those in FIG. 6C may apply to exemplary embodiments described in this application. For example, the target temperature of FIG. 5E may be given by one of the Equations 1 to 6, e.g., the Equation 1 or 2.

(109) The thermoelectric cooling package may mean the thermoelectric cooling package 1 including the TEC 10 and the POP 80 in a broad sense and any electronic or electric apparatus including the thermoelectric cooling package 1 such as the mobile phone illustrated in FIG. 6A or the display depicted in FIG. 6B in a narrow sense. Therefore, the thermal management described in this application may mean that a thermal management of the thermoelectric cooling package 1 itself or a thermal management of the electronic apparatus.

(110) [Modified Exemplary Embodiments of Thermoelectric Cooling Package]

(111) FIGS. 7A through 7D are cross sectional views illustrating modified embodiments of a thermoelectric cooling package according to exemplary embodiments of the inventive concept.

(112) Referring to FIG. 7A, a thermoelectric cooling package 2 may include a plurality of TECs combined with the POP 80. For example, a first TEC 10a and a second TEC 10b may be disposed at about the both side edges of the first package substrate 20, respectively. A positive voltage may be applied to a P-type semiconductor 12pa of the first TEC 10a and a negative voltage may be applied to an N-type semiconductor 12na of the first TEC 10a, thereby discharging the heat generated from the POP 80. Likewise, a positive voltage may be applied to a P-type semiconductor 12pb of the second TEC 10b and a negative voltage may be applied to an N-type semiconductor 12nb of the second TEC 10b, thereby discharging the heat generated from the POP 80. Thus, the temperature of the POP 80 may be maintained under the target temperature or within the target temperature range. The first TEC 10a may be operated simultaneously with the second TEC 10b or be operated independently of the second TEC 10b.

(113) Referring to FIG. 7B, a thermoelectric cooling package 3 may include a first TEC 10a disposed on the first package substrate 20 and a second TEC 10b disposed on the second package substrate 40. The first TEC 10a may be disposed on a left side edge of the first package substrate 20 to mainly discharge the heat generated from the logic chip 32. The second TEC 10b may be disposed at about a right side edge of the second package substrate 40 to mainly discharge the heat generated from the memory chips 42. The second package substrate 40 may further include metal vias 47 connected to the second TEC 10b. Solder balls 49 electrically connected to the metal vias 47 may further be provided between the first package substrate 20 and the second package substrate 40. The metal vias 47 and the solder balls 49 may be used as transmission paths of the voltages applied to the second TEC 10b.

(114) Referring to FIG. 7C, a thermoelectric cooling package 4 may include the TEC 10 which is not close to the POP 80. For example, the POP 80 may be disposed on the board 90 and the TEC 10 may be disposed outside the POP 80 on the board 90. Accordingly, it may be possible to remove or minimize a phenomenon transmitting the heat upwardly or downwardly flowing through the TEC 10 or generated from the TEC 10 itself to the POP 80. The thermoelectric cooling package 4 may include the heat sink 70 commonly connected to the TEC 10 and the POP 80. The heat generated from the POP 80 may be discharged through the heat sink 70 or be transmitted to the board 90. The heat transmitted to the board 90 may be moved to the heat sink 70 through the TEC 10 to be released. The board 90 may further include metal vias 94 connected to the second metal layers 16. The metal vias 94 may perform functions as voltage applying terminals and/or thermal vias.

(115) Referring to FIG. 7D, a thermoelectric cooling package 5 may include a first TEC 10a embedded in the POP 80. The first TEC 10a may be electrically insulated from the memory chips 42 disposed thereunder. When the thermoelectric cooling package 5 is connected to a casing 120, the first TEC 10a may be connected to the casing 120. The first TEC 10a may be electrically connected to the second package substrate 40 to be applied with voltages. If a positive voltage is applied to a P-type semiconductor 12pa of the first TEC 10a and a negative voltage is applied to an N-type semiconductor 12na of the first TEC 10a, the first TEC 10a may absorb heat from the memory chips 42 to transfer the heat to the casing 120. The thermoelectric cooling package 5 may further include a second TEC 10b embedded in the first package substrate 20. The second TEC 10b may be applied with voltages through the first package substrate 20. If a negative voltage is applied to a P-type semiconductor 12pb of the second TEC 10b and a positive voltage is applied to an N-type semiconductor 12nb of the second TEC 10b, the second TEC 10b may absorb heat from the logic chip 32 to discharge the heat through the board 90.

(116) [Examples of Electronic Systems]

(117) FIG. 8A is a schematic block diagram illustrating an example of memory cards including a thermoelectric cooling package according to exemplary embodiments of the inventive concept. FIG. 8B is a schematic block diagram illustrating an example of information processing systems including a thermoelectric cooling package according to exemplary embodiments of the inventive concept.

(118) Referring to FIG. 8A, a semiconductor memory module 1210 including at least one of the semiconductor packages 1 to 5 according to the exemplary embodiments described above may be applied to a memory card 1200. In an embodiment, the memory card 1200 may include a memory controller 1220 that controls data communication between a host 1230 and the semiconductor memory module 1210. A SRAM device 1221 may be used as an operation memory of a central processing unit (CPU) 1222. A host interface unit 1223 may be configured to include a data communication protocol of the host 1230 connected to the memory card 1200. An error check and correction (ECC) block 1224 may detect and correct errors of data which are read out from the semiconductor memory module 1210. A memory interface unit 1225 may be interfaced with the semiconductor memory module 1210. The central processing unit (CPU) 1222 may control overall operations of the memory controller 1220. The at least one of the semiconductor packages 1 to 5 according to the exemplary embodiments may be included in the SRAM device 1221, the ECC block 1224 and/or the CPU 1222. A main controller 1240 may control the operations described above. The main controller 1240 may include the at least one of the semiconductor packages 1 to 5 according to the exemplary embodiments. Alternatively, the main controller 1240 may control the SRAM device 1221, the ECC block 1224 and/or the CPU 1222 using the DTM methods as depicted in FIGS. 5C to 5O.

(119) Referring to FIG. 8B, an information processing system 1300 may include a memory system 1310 having at least one of the semiconductor packages 1 to 5 according to the above embodiments of the inventive concept. The information processing system 1300 may include a mobile system, a computer or the like. In an embodiment, the information processing system 1300 may include the memory system 1310, a modulator-demodulator (MODEM) 1320, a central processing unit (CPU) 1330, a random access memory (RAM) device 1340 and a user interface unit 1350 that communicate with each other through a data bus 1360. The memory system 1310 may include a memory module 1311 and a memory controller 1312. The memory system 1310 may have substantially the same configuration as the memory card 1200 of FIG. 8A. The memory system 1310 may store data processed by the CPU 1330 or data transmitted from an external system. The information processing system 1300 may be applied to a memory card, a solid state disk, a camera image sensor or an application chipset. In some embodiments, the memory system 1310 may be realized as a solid state drive (SSD). In this case, the information processing system 1300 may stably and reliably store massive data into the memory system 1310.

(120) According to the inventive concept, since the thermoelectric cooler is used, the semiconductor chip or the semiconductor package may be fast cooled. Additionally, since the change of the clock speed of the semiconductor chip may not be required, the semiconductor chip may maintain the high performance thereof.

(121) While the inventive concept has been described with reference to example embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the inventive concept. Therefore, it should be understood that the above embodiments are not limiting, but illustrative. Thus, the scope of the inventive concept is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing description.