A METHOD AND APPARATUS FOR HIGH-SPEED CHARGE-COUPLED CMOS TDI IMAGING

Abstract

A method and apparatus (e.g. circuitry) provide high-speed charge-coupled CMOS TDI imaging based on the parallel readout operation of multiple TDI stages. A plurality (N) of output registers are reset and precharged globally in parallel ready to take charge transferred from the same number (N) of the TDI pixel registers. Each of the signal charges at respective output registers is converted to a signal voltage in parallel. Each of the analog signal voltages is then converted to a digital value in parallel by each of the number of the ADCs. The AD conversion is also performed in parallel while the next N number of the TDI registers is processed. The N output registers are linked to receive the charges from a beginning of the registers along to an end. Converting the respective signal voltages is performed by S/H capacitor array circuitry in a ping-pong fashion using CDS voltages.

Claims

1. A method comprising: performing a readout of a plurality of Time Delay and Integration (TDI) pixel registers to receive respective signal charges to a plurality of output registers; performing a parallel conversion of the plurality of output registers by: converting the respective signal charges in parallel to respective signal voltages; and converting the respective signal voltages in parallel to respective digital values.

2. The method of claim 1 comprising resetting the plurality of output registers to receive the respective signal charges.

3. The method of claim 2, wherein resetting the plurality of output registers comprises emptying the plurality of output registers to a reset drain voltage through reset gates in parallel.

4. The method of claim 1, wherein individual ones of the plurality of output registers are linked, one to the next, from a beginning to an end and wherein performing a readout comprises transferring the respective signal charges to be received at a beginning for further transfer within the plurality of output registers.

5. The method of claim 1, wherein to perform the read out comprises receiving the respective signal charges at respective potential wells underneath respective floating gates that comprise the respective output registers.

6. The method of claim 5, wherein each of the respective floating gates is coupled to respective source followers (SF) to provide the respective signal voltages for conversion to the respective digital values.

7. The method of claim 1, wherein converting the respective signal voltages comprises: providing in parallel respective correlated double sampled (CDS) voltages to respective column-parallel analog to digital converters (ADCs) to produce the respective digital values.

8. (canceled)

9. The method of claim 1, wherein converting the respective signal voltages in parallel to respective digital values is performed at a present time further in parallel with a performing of a readout of a next in time plurality of respective signal charges to the plurality of output registers.

10. The method of claim 1, wherein performing the readout of the plurality of TDI registers to receive the respective signal charges is performed at a present time and further in parallel with a converting of respective earlier in time signal voltages to respective earlier in time digital values.

11. The method of claim 1, wherein the method is performed by a high-speed complementary metal-oxide-semiconductor (CMOS) TDI image sensor comprising a plurality of charge-coupled device (CCD) pixels arranged in a form of a matrix, a column slice thereof comprising the plurality of TDI pixel registers and the plurality of output registers.

12. The method of claim 1, wherein: first output registers are coupled at one end of the TDI pixel registers; second output registers are coupled at another end of the TDI pixel registers; and the method is performed using one of the first output registers and the second output registers as the plurality of output registers in response to a direction of scanning.

13. An apparatus comprising: a plurality of output registers coupled to receive respective signal charges readout from a plurality of Time Delay and Integration (TDI) pixel registers; wherein: each of the plurality of output registers is configured with circuitry providing parallel reset functionality, parallel charge sensing functionality and charge transfer functionality; and each of the plurality of output registers is coupled to column-parallel analog to digital converters (ADCs) to produce respective digital values for each of respective signal charges.

14. The apparatus of claim 13, wherein each of the output registers is coupled to the ADCs via respective sample and hold (S/H) capacitors for correlated double sampled (CDS) operation.

15. The apparatus of claim 13, wherein the parallel charge sensing functionality for each of the plurality of output registers converts the respective signal charges stored to a group of potential wells to respective signal voltages for the column-parallel ADCs.

16. The apparatus of claim 13, wherein the apparatus is configured to readout next in time respective signal charges to the output registers while the column-parallel ADCs convert the respective signal charges from a present time.

17. (canceled)

18. The apparatus of claim 14, wherein the respective S/H capacitor arrays collectively operate to: sample in parallel respective reference voltages at a present time to the respective first reference capacitors of the respective S/H capacitor arrays; sample in parallel the respective earlier in time signal voltages to respective signal capacitors; and provide in parallel respective CDS voltages from the respective earlier in time reference voltages sampled at respective second reference capacitors and the respective earlier in time signal voltages sampled at the signal capacitors to respective column-parallel ADCs to produce the respective earlier in time digital values.

19. The apparatus of claim 18, wherein the respective S/H capacitor arrays collectively further operate to: in further parallel, receive the next in time respective reference voltages to the respective second reference capacitors and the present signal voltages to the respective signal capacitors; and provide in parallel respective CDS voltages from the respective present reference voltages sampled at the respective first reference capacitors and the respective present signal voltages sampled at the signal capacitors to respective column-parallel ADCs to produce the respective present digital values.

20. The apparatus of claim 13 comprising a CMOS TDI image sensor wherein a plurality of CCD pixels is arranged in a form of a matrix, wherein a column slice thereof comprises the plurality of TDI pixel registers coupled to the plurality of output registers.

21. The apparatus of claim 13 comprising a CMOS TDI image sensor wherein a plurality of CCD pixels is arranged in a form of a matrix, wherein a column slice thereof comprises the plurality of TDI pixel registers coupled to i) first output registers at a first end of the plurality of TDI pixel registers and ii) second output registers at a second end of the plurality of TDI pixel registers for bidirectional operation wherein one of the first output registers and the second output registers selectively defining the plurality of output registers in response to a direction of scanning.

22. (canceled)

23. The apparatus of claim 13 comprising a CMOS TDI image sensor and wherein the apparatus is monolithically integrated on a single substrate.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0024] FIG. 1 is a block diagram showing a column slice of a high-speed charge-coupled CMOS TDI imager pixel matrix.

[0025] FIG. 2 is a block diagram of output registers, in accordance with an embodiment, comprising a floating gate configuration.

[0026] FIG. 3 is a block diagram showing a global reset of floating gates of FIG. 2, in accordance with an embodiment.

[0027] FIG. 4 is a block diagram showing an embodiment of an S/H capacitor circuit and a column-parallel ADC providing parallel conversion functionality.

[0028] FIG. 5 is a block diagram showing operational timing in accordance with an embodiment.

[0029] FIGS. 6A and 6B are block diagrams showing a column slice of a high-speed charge-coupled CMOS TDI imager pixel matrix configured for bidirectional operations in accordance with respective embodiments.

DESCRIPTION

[0030] FIG. 1 shows a block diagram of a (partial) high-speed charge-coupled CMOS TDI imager pixel array 100, in accordance with an embodiment. Pixel array 100 is partial in that shown is a column slice 102 thereof, the pixel array 100 comprising additional columns. Column slice 102 comprises a plurality (M) of TDI registers 104 (e.g. pixel registers) comprising individual TDI (pixel) registers (e.g. 104.sub.1, 104.sub.2, . . . 104.sub.N, . . . and 104.sub.M), a plurality of N TDI registers 106 comprising a subset of the TDI registers 104.sub.1, 104.sub.2, . . . and 104.sub.N, where N is less than or equal to M, and a plurality of N output registers 108 comprising individual output registers (e.g. 108.sub.1, 108.sub.2, . . . and 108.sub.N).

[0031] The plurality M of TDI registers 104 is coupled to a plurality of N output registers 108 to receive signal charges from the plurality N of TDI registers 106. The output registers 108 each have global signal reset functionality 300 and N parallel conversion functionality 400 as further described in FIGS. 3 and 4. In order to place all reset functionality, charge-transfer functionality and charge sensing functionality in one place, the output registers 108 support nondestructive readout with reset capability. The individual output registers are linked, one to the next, from a beginning to an end such that when performing a readout, the respective signal charges are transferred to be received at a beginning for further transfer within the plurality of output registers (e.g. along to the end to fill the registers).

[0032] In accordance with an embodiment, and in contrast to the traditional readout operation earlier described, high-speed, multiple TDI stages-based parallel operation is achieved as follows.

[0033] The plurality (N) of output registers 108 is reset globally in parallel (e.g. in accordance with an embodiment, via functionality 300) and ready to take a charge transferred from the plurality (N) of TDI pixel registers 106.

[0034] The charges accumulated in the plurality (N) of TDI registers 106 (e.g. out of the total plurality (M) of TDI registers 104) is transferred along the linked N output registers 108 from the beginning all the way to the end of the N output registers 108.

[0035] Each of the signal charges at each of the N output registers 108 is converted to a signal voltage in parallel (e.g. in accordance with an embodiment, via functionality 400).

[0036] Further via functionality 400, each of the analog signal voltages is then converted to a digital value in parallel by each of N number of ADCs. In accordance with an embodiment, the A/D conversion is also performed in parallel while next respective signal charges from N number of the TDI registers is processed. Each of the output registers is coupled to the parallel ADCs via respective S/H capacitor arrays for CDS operation. Each of the S/H capacitor arrays comprise two reference capacitors for ping-pong style S/H operation and a signal capacitor.

[0037] In accordance with respective embodiments, to incorporate all the functionalities there is provided a Floating Gate (FG) configuration 200 of output registers and the global reset functionality 300 as shown in FIGS. 2 and 3, respectively.

[0038] In an embodiment, respective output registers 108.sub.1, 108.sub.2, . . . 108.sub.N-1, and 108.sub.N are shown as comprising respective group of three-phase (e.g. .sub.1, .sub.2 and .sub.3) charge transfer gates (e.g. 203.sub.1, 203.sub.2, . . . 203.sub.N-1, and 203.sub.N and collectively 203) and a respective floating gate (e.g. 202.sub.1, 202.sub.2, . . . 202.sub.N-1, and 202.sub.N). Each respective group is linked to an adjacent group, one to the next, such that when performing a readout, respective signal charges from the plurality (N) of TDI registers 106 are transferred from the beginning 108.sub.N to the end 108.sub.1 of the plurality (N) of output registers 108.

[0039] FIG. 2 shows a channel potential diagram and corresponding charge transfer. Each of floating gates 202.sub.1, 202.sub.2, . . . 202.sub.N-1, and 202.sub.N (collectively, a plurality of (N) floating gates 202) is coupled to a reference voltage (Vref) 204 via respective precharge (PRC) gates (e.g. 206.sub.1, 206.sub.2, . . . 206.sub.N-1, and 206.sub.N). Each of the PRC gates 206.sub.1, 206.sub.2, . . . 206.sub.N-1, and 202.sub.N is driven by a PRC 206.

[0040] A drain voltage (VDD) 210 is coupled to respective source followers (e.g. 212.sub.1, 212.sub.2, . . . 212.sub.N-1, and 212.sub.N). Each of the source followers 212.sub.1, 212.sub.2, . . . 212.sub.N-1, and 212.sub.N is coupled to a respective floating gate 202.sub.1, 202.sub.2, . . . 202.sub.N-1, and 202.sub.N and Vref 204 (via the respective PRC gates 206.sub.1, 206.sub.2, . . . 206.sub.N-1, and 202.sub.N). Though not shown in FIG. 2 but shown in FIG. 4, each of the source followers 212.sub.1, 212.sub.2, . . . 212.sub.N-1, and 212.sub.N is also coupled to a respective S/H capacitor array circuit (e.g. via 214.sub.1, 214.sub.2, . . . 214.sub.N-1, and 214.sub.N) for CDS operation via a respective select (SEL) switch (e.g. 420.sub.N).

[0041] FIG. 3 is a block diagram showing the global reset functionality 300 for two floating gates 202.sub.N-1 and 202.sub.N of FIG. 2, in accordance with an embodiment, and where only two of the floating gates 202 are shown for simplicity. A reset signal 302 is coupled to reset gates 302.sub.N-1 and 302.sub.n between reset drain (VDD) 210 and each floating gate 202.sub.N-1 and 202.sub.N. Each floating gate 202.sub.N-1 and 202.sub.n is also shown coupled to the respective source follower 212.sub.N-1 and 212.sub.N.

[0042] In FIG. 4, there is shown a portion of the n parallel conversion functionality 400, in accordance with an embodiment for a representative nth floating gate 202.sub.N. FIG. 4 shows detail for one output register of the N output registers 108, namely output register 108.sub.N. S/H capacitor array circuit 402.sub.n (within the dotted outline) and the comparator 404.sub.N of a n.sup.th column-parallel ADC are connected to the nth output register 108.sub.N comprising floating gate 202.sub.N. For simplicity, components within S/H capacitor array circuit 402.sub.N are labeled without subscripts but it will be understood that each respective array circuit has respective components for the parallel operation. Each S/H capacitor array circuit of the N arrays comprises two reference capacitors for ping-pong style S/H operation and a signal capacitor. The N instances of the S/H capacitor array circuitry perform operations to: sample in parallel respective reference voltages at a present time to the respective first reference capacitors of the respective S/H capacitor arrays; sample in parallel the respective earlier in time signal voltages to respective signal capacitors; and provide in parallel respective CDS voltages from the respective earlier in time reference voltages sampled at respective second reference capacitors and the respective earlier in time signal voltages sampled at the signal capacitors to respective ADCs to produce the respective earlier in time digital values as further described.

[0043] Operation of FIG. 4 is also understood with reference to FIG. 5 showing operational timing 500 in accordance with an embodiment. FIG. 5 shows processing periods 502 and 504 to process present N TDI rows and next N TDI rows (for two successive readouts and AD conversions, each of which overlaps in time, converting a previous readout while performing a present readout). A single line period (i.e. TDI scan rate) of a processing period (e.g. 502) is shown at 506. FIG. 5 also shows AD conversion windows 508 and 510 for the previous N TDI rows and the present N TDI rows.

[0044] The even dashed vertical line 512 represents the time when the Vref 204 of a present time is sampled at a first reference capacitor Cref1 410. The double dot and dashed vertical line at 514 represents the time when the signal voltage (Vsig) of a previous time is sampled at a signal capacitor Csig 418 ready for CDS operation. The double dot and dashed vertical line 516 represents the time when Vref 210 of a next time is sampled at Cref2 412. The even dashed vertical line 518 represents the time when the Vsig of the present time is sampled at Csig 418 for CDS operation. The even dashed arrow 522 from 512 to the even dashed vertical line at 518 represents a CDS interval for the present time, which AD conversion 510 takes place in a next time period. The double dot and dashed arrow 520 ending at 514 represents a CDS interval for the previous time, which AD conversion 508 takes place in the present time. The double dot and dashed arrow 524 starting at 516 represents a CDS interval for the next time, which AD conversion takes place in a further next time period (not shown).

[0045] With reference again to FIG. 4, when both S/H switches (a sample and hold signal (SHS) switch 406 and a sample and hold reset (SHR) switch 408) are closed, Vref 210 is sampled to Cref1 410 when a first S/H switch (SH1 switch 412) is closed and a second S/H switch (SH2 switch 414) is open.

[0046] Then both the SHR switch 408 and the SH1 switch 412 are open to hold the Vref 210 at Cref1 410. At the same time, the SH2 switch 414 is closed for CDS operation with the Vsig sampled at Csig 418, which signal charges were transferred from a previous readout of the nth TDI register (i.e. in a previous processing period). Then the SHS switch 406 is open for the next cycle.

[0047] The AD conversion of the signal voltages for the previous N number of the TDI registers (via the N respective S/H capacitor arrays and ADCs) takes place while the signal charges stored in the present N number of the TDI registers 104 are transferred to the n number of the output registers 108. This completes one cycle 502 of the operational timing 500 provided in FIG. 5.

[0048] For the next cycle 504, when both SHS switch 406 and SHR switch 408 are closed again, the Vref 210 is sampled to Cref2 416 when SH2 switch 414 is closed and SH1 switch 412 is open. Then both the SHR switch 408 and the SH2 switch 414 are open to hold the Vref at Cref2. At the same time, the SH1 switch 412 is closed to sample the signal charges at Cref1 410, which were transferred from the present N number of the TDI registers. Then the SHS switch 406 is open to hold the signal voltage at Csig 418.

[0049] The AD conversion of the signal voltages for the present N number of the TDI registers takes place while the signal charges stored in the next N number of the TDI registers are transferred to the N number of the output registers.

[0050] Detailed operation, in accordance with the embodiments of FIGS. 1-5, is as follows. Previous signal charge stored under the (N) floating gates 202 of the (N) output registers 108 are emptied to VDD 210 through respective RSTs (e.g. the n.sup.th such RST being 302.sub.N). This operation is performed globally in parallel as illustrated in FIG. 3.

[0051] The channel potential of the floating gates 202 is set by a Vref 204 via respective PRC gates (e.g. the nth such gate being 206.sub.N to set potential wells 202.sub.N) and ready to receive signal charges from the (N) TDI pixel registers 106 (the nth such register being 104.sub.N). The Vref 204 is sampled and held in an each of the S/H capacitor array circuits (e.g. within nth such S/H capacitor array circuit being 402.sub.N).

[0052] The signal charges accumulated in the plurality (N) of the TDI registers 106 are transferred all the way to the end of the plurality (N) of floating gates 202 by three-phase charge transfer gates 203 of the output registers 108.

[0053] Each of the signal charges stored under each of the floating gates is converted to a signal voltage and is outputted via a SF in parallel. The signal voltage also is sampled to each of the S/H capacitors in parallel.

[0054] Each of the analog signal voltages is then converted to a digital value by each of the n ADCs in parallel, the nth such ADC being 404.sub.N. The AD conversion is also performed in parallel (e.g. simultaneously or at the same time) while the next in time N number of the TDI registers 104 (i.e. a next in time plurality (N) of signal charges) is transferred to the output registers 108. That is, for a first plurality (N) of respective signal charges transferred out at a present time (e.g. at a time T.sub.0), after conversion to respective present voltage signals, as those respective present voltage signals are converted to present digital values, a second plurality (N) of respective next signal charges are readout at a next time immediately after the present time (e.g. at a T.sub.1) from the plurality of (N) TDI registers 104 to the plurality (N) of output registers 108. Similarly, when the first plurality (N) of respective signal charges are readout at the present time T.sub.0, a plurality (N) of respective earlier signal charges, readout at an earlier time immediately prior to T.sub.0 (e.g. at T.sub.1) is, after conversion to respective earlier voltage signals, converted to respective earlier digital values.

[0055] FIGS. 6A and 6B are block diagrams showing a high-speed charge-coupled CMOS TDI imager 600A and 600B configured for bidirectional operations in accordance with respective embodiments. Bidirectional operations are responsive to a direction of scanning (e.g. forward and reverse) performed by the CMOS TDI imager. In a first bidirectional embodiment, there is shown a CCD pixel array 601, marked by a broken dot dashed box, comprising a plurality of TDI pixel registers 602 having coupled at respective ends thereof a top (first) plurality of output registers 604 and a bottom (second) plurality of output registers 606.

[0056] The respective output registers 604 and 606 are connected to respective pluralities of S/H capacitor array circuits 608 and 610 and the array circuits 608 and 610 are coupled respective pluralities of column-parallel ADCs 612 and 614 respectively.

[0057] FIG. 6A shows a representative column slice 616 of CMOS TDI imager 600A, marked by an even dashed line. The column slice 616 comprises a column subset of the TDI pixel registers 602, a column subset of each of the output registers 604 and 606, a column subset of each of the S/H capacitor array circuits 608 and 610 and a column subset of each of the column-parallel ADCs 612 and 614. The column subset of the TDI pixel registers 602 is equivalent to the plurality of M TDI pixel registers 104. The column subsets of each of the output registers 604 and 606 is equivalent to the plurality of N output registers 108.

[0058] In a second bidirectional embodiment 600B, the respective output registers 604 and 606 at respective ends of TDI pixel registers 602 are multiplexed to S/H capacitor arrays 608 and column-parallel ADCs 612 located at one end of the TDI pixel registers 602.

[0059] It will be understood that FIGS. 6A and 6B are simplified and may be implemented using the structures of FIGS. 2-4, with suitable adaptation.

[0060] In an embodiment, during operation of the embodiments 600A or 600B, the methods as described herein are performed in a bidirectional manner, using one or the other of the first output registers and the second output registers (as the plurality of output registers) when performing the readout of a plurality of TDI pixel registers to the plurality of output registers and performing the parallel conversion of the plurality of output registers. In an embodiment, the selection of one or the other is responsive to a direction of scanning (e.g. performed by the CMOS TDI imager 600A or 600B). In an embodiment (e.g. 600A), output registers 604, S/H capacitor array circuits 608 and column-parallel ADCs 612 are used for a forward scanning direction and output registers 606, S/H capacitor array circuits 610 and column-parallel ADCs 614 are used for a reverse scanning direction. In an embodiment (e.g. 600B), output registers 604 and output registers 606 are multiplexed to S/H capacitor array circuits 610 and column-parallel ADCs 612 for a forward scanning direction and a reverse scanning direction, respectively.

[0061] Practical implementation may include any or all of the features described herein. These and other aspects, features and various combinations may be expressed as methods, apparatus, systems, means for performing functions, program products, and in other ways, combining the features described herein. A number of embodiments have been described. Nevertheless, it will be understood that various modifications can be made without departing from the spirit and scope of the processes and techniques described herein. In addition, other steps can be provided, or steps can be eliminated, from the described process, and other components can be added to, or removed from, the described systems. Accordingly, other embodiments are within the scope of the following claims.

[0062] Throughout the description and claims of this specification, the word comprise, contain and variations of them mean including but not limited to and they are not intended to (and do not) exclude other components, integers or steps. Throughout this specification, the singular encompasses the plural unless the context requires otherwise. In particular, where the indefinite article is used, the specification is to be understood as contemplating plurality as well as singularity, unless the context requires otherwise.

[0063] Features, integers, characteristics, or groups described in conjunction with a particular aspect, embodiment or example of the invention are to be understood to be applicable to any other aspect, embodiment or example unless incompatible therewith. All of the features disclosed herein (including any accompanying claims, abstract and drawings), and/or all of the steps of any method or process so disclosed, may be combined in any combination, except combinations where at least some of such features and/or steps are mutually exclusive. The invention is not restricted to the details of any foregoing examples or embodiments. The invention extends to any novel one, or any novel combination, of the features disclosed in this specification (including any accompanying claims, abstract and drawings) or to any novel one, or any novel combination, of the steps of any method or process disclosed.