EQUALIZER CIRCUIT IN AN ENVELOPE TRACKING INTEGRATED CIRCUIT

Abstract

An equalizer circuit in an envelope tracking (ET) integrated circuit (ETIC) is disclosed. The ETIC (26) is configured to generate an ET voltage based on a target voltage (VTGT) for amplifying a radio frequency (RF) signal(s). Since the ETIC has inherent impedance and group delay that can cause distortion in the ET voltage, an equalizer circuit (24) is provided in the ETIC to equalize the target voltage prior to generating the ET voltage. Specifically, the equalizer circuit generates an equalized target voltage to offset the inherent impedance and a modified target voltage to mitigate the group delay. Accordingly, the equalizer circuit can output a processed target voltage, which can include the equalized target voltage and/or the modified target voltage, for generating the ET voltage. As a result, it is possible to reduce distortion resulted from the inherent impedance and group delay, especially when the RF signal(s) is modulated in a wide modulation bandwidth.

Claims

1. An equalizer circuit comprising: a voltage input that receives a target voltage; an impedance equalizer circuit configured to equalize the target voltage based on a predefined transfer function to generate an equalized target voltage; a target voltage processing circuit configured to modify the target voltage to generate a modified target voltage having a reduced dynamic range lower than the target voltage; an output circuit (38) configured to: receive the equalized target voltage and the modified target voltage and output a processed target voltage comprising both the equalized target voltage and the modified target voltage when the target voltage is associated with a higher modulation bandwidth; and receive only the equalized target voltage and generate the processed target voltage comprising only the equalized target voltage when the target voltage is associated with a lower modulation bandwidth lower than the higher modulation bandwidth; and a voltage output coupled to the output circuit and outputting the processed target voltage.

2. The equalizer circuit of claim 1, wherein the predefined transfer function comprises a second-order complex-zero term and a real-zero term.

3. (canceled)

4. The equalizer circuit of claim 1, further comprising: a switch coupled between the voltage input and the target voltage processing circuit; and a control circuit configured to: close the switch to thereby couple the target voltage processing circuit to the voltage input in response to the target voltage indicating a higher modulation bandwidth; and open the switch to thereby decouple the target voltage processing circuit from the voltage input in response to the target voltage indicating a lower modulation bandwidth.

5. The equalizer circuit of claim 4, wherein the output circuit is further configured to cause the voltage output to output the processed target voltage comprising the equalized target voltage and the modified target voltage in response to the switch being closed.

6. The equalizer circuit of claim 4, wherein the output circuit is further configured to cause the voltage output to output the processed target voltage comprising only the equalized target voltage in response to the switch being opened.

7. The equalizer circuit of claim 1, wherein the target voltage processing circuit comprises: a low-slope lookup table (LUT) configured to correlate the target voltage with the modified target voltage; and a processing circuit configured to modify the target voltage based on the low-slope LUT to generate the modified target voltage.

8. The equalizer circuit of claim 7, wherein the target voltage processing circuit further comprises an analog frequency equalizer configured to equalize the modified target voltage.

9. The equalizer circuit of claim 7, wherein the target voltage processing circuit further comprises an analog frequency equalizer configured to equalize the target voltage.

10. The equalizer circuit of claim 1, wherein the impedance equalizer circuit is further configured to equalize the target voltage based on the predefined transfer function and the modified target voltage to generate the equalized target voltage.

11. An envelope tracking (ET) integrated circuit (ETIC) comprising: an equalizer circuit comprising: a voltage input that receives a target voltage; an impedance equalizer circuit configured to equalize the target voltage based on a predefined transfer function to generate an equalized target voltage; a target voltage processing circuit configured to modify the target voltage to generate a modified target voltage having a reduced dynamic range lower than the target voltage; an output circuit configured to: receive the equalized target voltage and the modified target voltage and output a processed target voltage comprising both the equalized target voltage and the modified target voltage when the target voltage is associated with a higher modulation bandwidth; and receive only the equalized target voltage and generate the processed target voltage comprising only the equalized target voltage when the target voltage is associated with a lower modulation bandwidth lower than the higher modulation bandwidth; and a voltage output coupled to the output circuit and outputs the processed target voltage; and an ET voltage circuit coupled to the voltage output and configured to generate an ET voltage based on the processed target voltage.

12. The ETIC of claim 11, further comprising an isogain lookup table (LUT) coupled to the voltage input and configured to generate the target voltage based on a power envelope of a radio frequency (RF) signal.

13. (canceled)

14. The ETIC of claim 11, wherein the equalizer circuit further comprises: a switch coupled between the voltage input and the target voltage processing circuit; and a control circuit configured to: close the switch to thereby couple the target voltage processing circuit to the voltage input in response to the target voltage indicating a higher modulation bandwidth; and open the switch to thereby decouple the target voltage processing circuit from the voltage input in response to the target voltage indicating a lower modulation bandwidth.

15. The ETIC of claim 14, wherein the output circuit is further configured to cause the voltage output to output the processed target voltage comprising the equalized target voltage and the modified target voltage in response to the switch being closed.

16. The ETIC of claim 14, wherein the output circuit is further configured to cause the voltage output to output the processed target voltage comprising only the equalized target voltage in response to the switch being opened.

17. The ETIC of claim 11, wherein the target voltage processing circuit comprises: a low-slope lookup table (LUT) configured to correlate the target voltage with the modified target voltage; and a processing circuit configured to modify the target voltage based on the low-slope LUT to generate the modified target voltage.

18. The ETIC of claim 17, wherein the target voltage processing circuit further comprises an analog frequency equalizer configured to equalize the modified target voltage.

19. The ETIC of claim 17, wherein the target voltage processing circuit further comprises an analog frequency equalizer configured to equalize the target voltage.

20. The ETIC of claim 11, wherein the impedance equalizer circuit is further configured to equalize the target voltage based on the predefined transfer function and the modified target voltage to generate the equalized target voltage.

Description

BRIEF DESCRIPTION OF THE DRAWING FIGURES

[0011] The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

[0012] FIG. 1A is a schematic diagram of an exemplary conventional envelope tracking (ET) power amplifier apparatus configured to generate an ET voltage;

[0013] FIG. 1B is a schematic diagram of an exemplary equivalent circuit for illustrating various impedances and/or inductances in the conventional power amplifier apparatus of FIG. 1 that can distort the ET voltage;

[0014] FIG. 2 is a schematic diagram of an exemplary equalizer circuit provided in an ET integrated circuit (ETIC) and configured according to embodiments of the present disclosure to reduce potential voltage disturbance in an ET voltage;

[0015] FIG. 3 is a schematic diagram providing an exemplary illustration of a target voltage processing circuit that can be provided in the equalizer circuit of FIG. 2; and

[0016] FIG. 4 is a schematic diagram of an exemplary ETIC configured according to another embodiment of the present disclosure.

DETAILED DESCRIPTION

[0017] The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

[0018] It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term and/or includes any and all combinations of one or more of the associated listed items.

[0019] It will be understood that when an element such as a layer, region, or substrate is referred to as being on or extending onto another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being directly on or extending directly onto another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being over or extending over another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being directly over or extending directly over another element, there are no intervening elements present. It will also be understood that when an element is referred to as being connected or coupled to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being directly connected or directly coupled to another element, there are no intervening elements present.

[0020] Relative terms such as below or above or upper or lower or horizontal or vertical may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

[0021] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms a, an, and the are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms comprises, comprising, includes, and/or including when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

[0022] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0023] Embodiments are described herein with reference to an equalizer circuit in an envelope tracking (ET) integrated circuit (ETIC). The ETIC is configured to generate an ET voltage based on a target voltage for amplifying a radio frequency (RF) signal(s). Given that the ETIC has inherent impedance and group delay that can cause distortion in the ET voltage, an equalizer circuit is provided in the ETIC to equalize the target voltage prior to generating the ET voltage. Specifically, the equalizer circuit generates an equalized target voltage to offset the inherent impedance and a modified target voltage to mitigate the group delay. Accordingly, the equalizer circuit can output a processed target voltage, which can include the equalized target voltage and/or the modified target voltage, for generating the ET voltage. As a result, it is possible to reduce distortion resulted from the inherent impedance and group delay, especially when the RF signal(s) is modulated in a wide modulation bandwidth (e.g., >200 MHz).

[0024] Before discussing the equalizer circuit and the ETIC according to the present disclosure, starting at FIG. 2, an overview of a conventional ET power management apparatus that can experience ET voltage distortion is first provided with reference to FIGS. 1A and 1B.

[0025] FIG. 1A is a schematic diagram of an exemplary conventional power management apparatus 10 configured to generate an ET voltage V.sub.CC. The conventional power management apparatus 10 includes a transceiver circuit 12, an ETIC 14, a power amplifier circuit 16, and a signal line(s) 18 that couples the ETIC 14 to the power amplifier circuit 16.

[0026] The transceiver circuit 12 is configured to generate and provide an RF signal 20, which is associated with a time-variant power envelope P.sub.ENV, to the power amplifier circuit 16. The transceiver circuit 12 is also configured to generate a target voltage V.sub.TGT in accordance with (a.k.a. tracks) the time-variant power envelope P.sub.ENV. The ETIC 14 is configured to generate the ET voltage V.sub.CC based on the target voltage V.sub.TGT and the power amplifier circuit 16 is configured to amplify the RF signal 20 based on the ET voltage V.sub.CC.

[0027] Those skilled in the art will appreciate that the power amplifier circuit 16 may operate with improved efficiency and linearity when the ET voltage V.sub.CC accurately tracks the power envelope P.sub.ENV of the RF signal 20. This is achieved when the ET voltage V.sub.CC is temporally aligned with the target voltage V.sub.TGT. However, temporal alignment between the ET voltage V.sub.CC and the target voltage V.sub.TGT may be complicated by various impedances, inductances, and group delays presenting in the conventional power management apparatus 10.

[0028] To illustrate the various impedances and/or inductances, FIG. 1B is a schematic diagram of an exemplary equivalent circuit 22 for illustrating the various impedances and inductances in the conventional power management apparatus 10 of FIG. 1A that can distort the ET voltage V.sub.CC. Common elements between FIGS. 1A and 1B are shown therein with common element numbers and will not be re-described herein.

[0029] In the equivalent circuit 22, the ETIC 14 has an inherent impedance that can be modeled by an equivalent inductance L.sub.ETIC and the signal line(s) 20 has an inherent trance inductance that can be modeled by an equivalent trance inductance L.sub.TRACE. Accordingly, the equivalent circuit 22 would have a total equivalent inductance L.sub.E that equals a sum of the equivalent inductance L.sub.ETIC and the equivalent trance inductance L.sub.TRACE (L.sub.E=L.sub.ETIC+L.sub.TRACE).

[0030] The power amplifier circuit 16 can be modeled as a current source with a modulated current I.sub.CC(s) and have a total equivalent capacitance C.sub.PA. Accordingly, an equivalent source impedance Z.sub.SOURCE(S) presented to the current source can be determined as in equation (Eq. 1) below.

[00001]$\begin{array}{cc}{Z}_{\mathrm{SOURCE}}\left(s\right)=\frac{s*L_E}{1+L_E*C_{\mathrm{PA}}*s^2}& \left(\mathrm{Eq}.1\right)\end{array}$

[0031] In the equation (Eq. 1), s represents the s-transform notation, which can be expressed as s=j2f. The modulated current I.sub.CC(s) is somewhat proportional to the target voltage V.sub.TGT and can be expressed as in the equation (Eq. 2) below.

[00002]$\begin{array}{cc}{I}_{\mathrm{CC}}\left(s\right)=\frac{V_{\mathrm{TGT}}\left(s\right)}{Z_{\mathrm{ICC}}\left(s\right)*e^{\left(-s*D\right)}}& \left(\mathrm{Eq}.2\right)\end{array}$

[0032] In the equation (Eq. 2) above, Z.sub.ICC(s) represents an impedance at a collector (not shown) of the power amplifier circuit 16 and D represents a group delay between the V.sub.TGT and the time-variant power envelope P.sub.EVN at an output stage (not shown) of the power amplifier circuit 16. Notably, the modulated current I.sub.CC can create a voltage disturbance, which is approximately equal to Z.sub.SOURCE(S)*I.sub.CC(s), across the collector of the power amplifier circuit 16. The voltage disturbance can cause a misalignment between the ET voltage V.sub.CC and the power envelope P.sub.ENV at the power amplifier circuit 16. Consequently, the power amplifier circuit 16 can cause a distortion (e.g., amplitude clipping) in the RF signal 20. Hence, it is desirable to reduce the voltage disturbance resulted from the equivalent trance inductance L.sub.TRACE and the group delay D in the conventional power management apparatus 10.

[0033] In this regard, FIG. 2 is a schematic diagram of an exemplary equalizer circuit 24 provided in an ETIC 26 and configured according to embodiments of the present disclosure to reduce potential voltage disturbance, as described in FIG. 1B, in an ET voltage V.sub.CC. The ETIC 26 is configured to generate the ET voltage V.sub.CC based on a target voltage V.sub.TGT, which can be a differential target voltage, as an example. Given that the ETIC 26 has inherent impedance (e.g., L.sub.ETIC) and group delay (e.g., D) that can cause distortion in the ET voltage V.sub.CC, the equalizer circuit 24 is employed to equalize the target voltage V.sub.TGT prior to generating the ET voltage V.sub.CC.

[0034] In an embodiment, the equalizer circuit 24 receives the target voltage V.sub.TGT at a voltage input V.sub.IN and generates a processed target voltage V.sub.TGT-E at a voltage output V.sub.OUT based on the target voltage V.sub.TGT. Specifically, the equalizer circuit 24 generates an equalized target voltage V.sub.TGT-A to offset the inherent impedance (e.g., L.sub.ETIC) and a modified target voltage V.sub.TGT-B to mitigate the group delay (e.g., D). Accordingly, the equalizer circuit can output the processed target voltage V.sub.TGT-E at the voltage output V.sub.OUT for generating the ET voltage V.sub.CC. As discussed below, the processed target voltage V.sub.TGT-E includes at least one of the equalized target voltage V.sub.TGT-A and the modified target voltage V.sub.TGT-B.

[0035] In one non-limiting example, the equalizer circuit 24 can be controlled to generate the processed target voltage V.sub.TGT-E to include both the equalized target voltage V.sub.TGT-A and the modified target voltage V.sub.TGT-B when the target voltage V.sub.TGT is associated with a higher modulation bandwidth (e.g., >60 MHz). In another non-limiting example, the equalizer circuit 24 can be controlled to generate the processed target voltage V.sub.TGT-E to include only the equalized target voltage V.sub.TGT-A when the target voltage V.sub.TGT is associated with a lower modulation bandwidth (e.g., 60 MHz). Thus, by generating the ET voltage V.sub.CC based on the processed target voltage V.sub.TGT-E, it is possible to reduce the voltage distortion resulted from the inherent impedance and group delay across a wide modulation bandwidth.

[0036] The equalizer circuit 24 can be configured to include an impedance equalizer circuit 28 and a target voltage processing circuit 30. The impedance equalizer circuit 28 is configured to equalize the target voltage V.sub.TGT based on a predefined transfer function to thereby generate the equalized target voltage V.sub.TGT-A. In a non-limiting example, the predefined transfer function includes a second-order complex-zero term, which can offset a second-order complex-pole term caused by the equivalent trance inductance L.sub.TRACE in FIG. 1B, and a real-zero term, which can offset a real-pole term caused by the equivalent inductance L.sub.ETIC in FIG. 1B. For a more detailed description of the impedance equalizer circuit 28, please refer to U.S. patent application Ser. No. 17/412,823, entitled EQUALIZER CIRCUIT AND RELATED POWER MANAGEMENT CIRCUIT.

[0037] The target voltage processing circuit 30 is configured to modify the target voltage V.sub.TGT to generate the modified target voltage V.sub.TGT-B. In a non-limiting example, the modified target voltage V.sub.TGT-B has a reduced dynamic range lower than the target voltage V.sub.TGT. Herein, a dynamic range of voltage refers to a maximum level (peak) minus a minimum level (bottom) of the voltage. By reducing the dynamic range of the modified target voltage V.sub.TGT-B, it is possible to reduce delay sensitivity of the ET voltage V.sub.CC to thereby mitigate the group delay (e.g., D). For a detailed description on how the reduced dynamic range can help mitigate the group delay, please refer to U.S. Pat. No. 10,911,001 B2, issued Feb. 2, 2021, and entitled ENVELOPE TRACKING AMPLIFIER CIRCUIT.

[0038] In this regard, FIG. 3 is a schematic diagram providing an exemplary illustration of the target voltage processing circuit 30 in accordance with an embodiment of the present disclosure. Common elements between FIGS. 2 and 3 are shown therein with common element numbers and will not be re-described herein.

[0039] The target voltage processing circuit 30 can include a processing circuit 32 and a low-slope lookup table (LUT) 34. In a non-limiting example, the low-slope LUT 34 can correlate the target voltage V.sub.TGT, which has a higher dynamic range, with the modified target voltage V.sub.TGT-B that has a lower dynamic range. Accordingly, the processing circuit 32 can modify the target voltage V.sub.TGT based on the low-slope LUT 34 to generate the modified target voltage V.sub.TGT-B having the reduced dynamic range lower than the target voltage V.sub.TGT.

[0040] The target voltage processing circuit 30 may include an analog frequency equalizer 36. In one embodiment, the analog frequency equalizer 36 may be provided in series and after the processing circuit 32. In this regard, the analog frequency equalizer 36 can flatten a frequency response of the modified target voltage V.sub.TGT-B. In another embodiment, the analog frequency equalizer 36 may be provided in series and before the processing circuit 32. In this regard, the analog frequency equalizer 36 can flatten frequency response of the target voltage V.sub.TGT.

[0041] With reference back to FIG. 2, the equalizer circuit 24 can further include an output circuit 38 coupled to the impedance equalizer circuit 28, the target voltage processing circuit 30, and the voltage output V.sub.OUT. The output circuit 38 is configured to cause the voltage output V.sub.OUT to output the processed target voltage V.sub.TGT-E at the voltage output V.sub.OUT.

[0042] The equalizer circuit 24 may also include a switch 40 and a control circuit 42. The switch 40 is coupled between the voltage input V.sub.IN and the target voltage processing circuit 30. The control circuit 42, which can be a field-programmable gate array (FPGA), as an example, can control the switch 40 to couple or decouple the voltage input V.sub.IN to or from the target voltage processing circuit 30.

[0043] In a non-limiting example, the control circuit 42 may receive the target voltage V.sub.TGT that can indicate a modulation bandwidth. If the modulation bandwidth is higher than, for example, 60 MHz, the control circuit 42 can close the switch 40 to thereby couple the target voltage processing circuit 30 to the voltage input V.sub.IN to receive the target voltage V.sub.TGT. Accordingly, the equalizer circuit 24 will output the processed target voltage V.sub.TGT-E that includes both the equalized target voltage V.sub.TGT-A and the modified target voltage V.sub.TGT-B.

[0044] In contrast, if the modulation bandwidth is lower than or equal to, for example, 60 MHz, the control circuit 42 can open the switch 40 to thereby decouple the target voltage processing circuit 30 from the voltage input V.sub.IN. As such, the target voltage processing circuit 30 is bypassed. Accordingly, the equalizer circuit 24 will output the processed target voltage V.sub.TGT-E that includes only the equalized target voltage V.sub.TGT-A.

[0045] The ETIC 26 can include an ET voltage circuit 44 that is coupled to the voltage output V.sub.OUT. In this regard, the ET voltage circuit 44 is configured to generate the ET voltage V.sub.CC based on the processed target voltage V.sub.TGT-E.

[0046] In one embodiment, the equalizer circuit 24 can be configured to receive the target voltage V.sub.TGT from a transceiver circuit 46 coupled externally to the ETIC 26. In another embodiment, the ETIC 26 may also be configured to generate the target voltage V.sub.TGT internally. In this regard, FIG. 4 is a schematic diagram of an exemplary ETIC 48 configured according to another embodiment of the present disclosure. Common elements between FIGS. 2 and 4 are shown therein with common element numbers and will not be re-described herein.

[0047] In a non-limiting example, the ETIC 48 includes an isogain LUT 50. The isogain LUT 50 can include a high-slope LUT (not shown) that correlates signal amplitudes defined by a power envelope of an RF signal (not shown), such as the power envelope P.sub.ENV in FIG. 1A, with the target voltage V.sub.TGT. The isogain LUT 50 may be coupled to the voltage input V.sub.IN and configured to generate the target voltage V.sub.TGT based on the power envelope of the RF signal. Herein, the high-slope LUT has a steeper slope, which corresponds to a higher dynamic range, than the low-slope LUT 34. As a result, the isogain LUT 50 can generate the target voltage V.sub.TGT with a higher dynamic range than the modified target voltage V.sub.TGT-B.

[0048] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.