DC OFFSET COMPENSATION IN MODULAR MULTILEVEL CONVERTER

Abstract

In a method of compensating for a DC offset of a high-voltage AC output from a Modular Multilevel Converter (MMC) including at least one phase leg, the MMC is connected to a three-phase high-voltage AC grid via a grid transformer. The method includes, in at least one DC offset correcting device, measuring the DC offset by in each of the at least one DC offset correcting device: obtaining a high-voltage AC signal in the MMC, removing high-voltage AC components from the obtained high-voltage AC signal by means of a passive higher-order filter to obtained an analogue filtered signal, converting the analogue filtered signal to a digital signal by means of an analogue-to-digital converter, removing remaining AC components from the digital signal by means of a digital filter to obtain the DC offset, and in a controller comparing the obtained offset with a reference value and forming a control signal based on said comparing. The method also includes transmitting the control signal from each of the at least one DC offset correcting device to a control device of the MMC. The method also includes, the control device mapping the control signal(s) from the at least one DC offset correcting device to the at least one phase leg. The method also includes, based on the mapping, the control device sending switching commands to the semiconductor switches of MMC cells in each of the at least one phase leg to compensate for the DC offset.

Claims

1.-12. (canceled)

13. A method of compensating for a DC offset of a high-voltage AC output from a Modular Multilevel Converter, MMC, comprising at least one phase leg of at least one AC phase, wherein each of the at least one phase leg comprises a plurality of cascaded converter cells, each cell comprising a plurality of semiconductor switches and an energy storage forming an intermediate DC circuit in the cell, wherein the MMC is connected to a three-phase high-voltage AC grid via a grid transformer, the method comprising: in at least one DC offset correcting device of the MMC, measuring the DC offset by, in each of the at least one DC offset correcting device: obtaining a high-voltage AC signal in the MMC; removing high-voltage AC components from the obtained high-voltage AC signal by means of a passive higher-order filter to obtained an analogue filtered signal; converting the analogue filtered signal to a digital signal by means of an analogue-to-digital converter; removing remaining AC components from the digital signal by means of a digital filter, whereby the AC components are sufficiently suppressed to allow obtaining of the DC offset; and in a controller, comparing the obtained offset with a reference value and forming a control signal based on said comparing; transmitting the control signal from each of the at least one DC offset correcting device to a control device of the MMC; the control device mapping the control signal(s) from the at least one DC offset correcting device to the at least one phase leg; and based on the mapping, the control device sending switching commands to the semiconductor switches of the cells in each of the at least one phase leg to compensate for the DC offset.

14. The method of claim 13, wherein the high-voltage AC grid is a three-phase grid and wherein the MMC is also connected to a second high-voltage AC grid via a second grid transformer and/or a line reactor.

15. The method of claim 14, wherein the second high-voltage AC grid is a single-phase grid, whereby the MMC has a double-wye topology.

16. The method of claim 13, wherein the high-voltage AC signal is obtained from an output terminal of the MMC.

17. The method of claim 16, wherein a first of the at least one DC offset correcting device is connected to the three-phase output terminals of the MMC to the first grid transformer.

18. The method of claim 13, wherein the high-voltage AC signal is obtained across a phase leg of the MMC.

19. The method of claim 18, wherein, for each of the phase legs of the MMC, one of the at least one DC offset correcting device is connected across said phase leg.

20. The method of claim 13, wherein each of the at least one DC offset correcting device is powered internally in the MMC via a power supply.

21. The method of claim 20, wherein the power supply comprises an AC-to-DC converter connected to an output terminal of the MMC via a buck transformer.

22. The method of claim 20, wherein the power supply comprises a DC-to-DC converter connected to the intermediate DC circuit of a cell of the MMC.

23. The method of claim 13, wherein the control signal is transmitted via optical cable(s).

24. A Modular Multilevel Converter, MMC, comprising at least one phase leg of at least one AC phase, wherein each of the at least one phase leg comprises a plurality of cascaded converter cells, each cell comprising a plurality of semiconductor switches and an energy storage forming an intermediate DC circuit in the cell, wherein the MMC is connected to a three-phase high-voltage AC grid via a grid transformer, the MMC comprising: at least one DC offset correcting device configured for measuring the DC offset by, in each of the at least one DC offset correcting device: obtaining a high-voltage AC signal in the MMC; removing high-voltage AC components from the obtained high-voltage AC signal by means of a passive higher-order filter to obtained an analogue filtered signal; converting the analogue filtered signal to a digital signal by means of an analogue-to-digital converter; removing remaining AC components from the digital signal by means of a digital filter, whereby the AC components are sufficiently suppressed to allow obtaining of the DC offset; in a controller, comparing the obtained offset with a reference value and forming a control signal based on said comparing; and transmitting the control signal from each of the at least one DC offset correcting device to a control device of the MMC; and a control device configured for mapping the control signal(s) from the at least one DC offset correcting device to the at least one phase leg, and based on the mapping, sending switching commands to the semiconductor switches of the cells in each of the at least one phase leg to compensate for the DC offset.

25. The method of claim 14, wherein the high-voltage AC signal is obtained from an output terminal of the MMC.

26. The method of claim 15, wherein the high-voltage AC signal is obtained from an output terminal of the MMC.

27. The method of claim 14, wherein the high-voltage AC signal is obtained across a phase leg of the MMC.

28. The method of claim 15, wherein the high-voltage AC signal is obtained across a phase leg of the MMC.

29. The method of claim 14, wherein each of the at least one DC offset correcting device is powered internally in the MMC via a power supply.

30. The method of claim 15, wherein each of the at least one DC offset correcting device is powered internally in the MMC via a power supply.

31. The method of claim 16, wherein each of the at least one DC offset correcting device is powered internally in the MMC via a power supply.

32. The method of claim 17, wherein each of the at least one DC offset correcting device is powered internally in the MMC via a power supply.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Embodiments will be described, by way of example, with reference to the accompanying drawings, in which:

[0013] FIG. 1 is a schematic functional block diagram of an embodiment of DC offset correcting devices communicating with a control of an MMC, in accordance with the present invention.

[0014] FIG. 2a is a schematic block diagram of an embodiment of an MMC comprising DC offset correcting devices, in accordance with the present invention.

[0015] FIG. 2b is a schematic functional block diagram of an embodiment of DC offset correcting devices communicating with a control of the MMC of FIG. 2a, in accordance with the present invention.

[0016] FIG. 3a is a schematic block diagram of another embodiment of an MMC comprising DC offset correcting devices, in accordance with the present invention.

[0017] FIG. 3b is a schematic functional block diagram of an embodiment of DC offset correcting devices communicating with a control of the MMC of FIG. 3a, in accordance with the present invention.

[0018] FIG. 3c is a schematic functional block diagram of another embodiment of DC offset correcting devices communicating with a control of the MMC of FIG. 3a, in accordance with the present invention.

DETAILED DESCRIPTION

[0019] Embodiments will now be described more fully hereinafter with reference to the accompanying drawings, in which certain embodiments are shown. However, other embodiments in many different forms are possible within the scope of the present disclosure. Rather, the following embodiments are provided by way of example so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Like numbers refer to like elements throughout the description.

[0020] Embodiments of the present invention may be used for any type of MMC, having any topology. Herein, a double-why (Y), also called double-star, topology is used as an example, for an MMC between a three-phase AC grid and a single-phase AC grid. Other examples of MMC topologies with which embodiments of the present invention may be used comprise delta-connected MMC and (single) wye-connected MMC.

[0021] An MMC conventionally comprises, depending on suitable topology, any number of at least one phase-leg comprising a plurality of series connected (also called cascaded or chain-linked) converter cells. Each converter cell comprises a plurality of semiconductor switches forming e.g. a full-bridge (also called H-bridge) topology for a bipolar cell or a half-bridge topology for a unipolar cell. Each converter cell also comprises an energy storage forming part of what is herein referred to as an intermediate DC circuit. The energy storage may e.g. comprise a battery or, preferably, a capacitor arrangement comprising any number of at least one capacitor. AC voltages herein are given conventionally as the root-mean-square voltages, which could also be denoted V.sub.rms or V.sub.AC.

[0022] Reference is made to FIG. 1 showing a general outline of a DC offset correcting arrangement comprising a plurality of DC offset correcting devices 10.sub.1 to 10.sub.n. An objective of the invention is to provide a solution for suppressing the DC component in the HV output of MMC applications. This is done by measuring DC offset voltages somewhere in the MMC by using a suitable number of DC offset correcting devices 10 (depending on applications), process measured DC offset and apply the outputs of the DC offset correcting devices to the converter phase legs. The method and devices for realising the method should preferably be as simple as possible, be reliable to operate, require minimum external components (such as voltage divider resistors, high voltage cables, insulators, power supply, etc.), to be cheap to implement.

[0023] Each DC offset correcting device 10 comprises measurement input terminals for obtaining high-voltages, i.e. HV AC signals, from somewhere in the MMC. The HV AC signal has a voltage (V.sub.rms) of above 3.6 kV, e.g. of at least 4 kV or at least 10 kV, up to 36 kV, such as within a range of 4-36 kV. The HV AC signals are processed by means of passive higher-order filter(s) ii to remove HV AC components. That the filters are passive implies that they are essentially free from offset. The passive filter may e.g. be a low-pass filter designed to damp components of the HV AC signal above a predetermined cut-off frequency. The passive filter 11 may e.g. be designed in the form of a cascade of resistive and capacitive (RC) elements, e.g. a three-stage cascade of RC elements for a third order low-pass filter.

[0024] In high-voltage applications, the passive filter(s) ii are not enough to sufficiently remove the AC component of the HV AC signal and obtain the DC offset component of the HV AC signal. Thus, after having applied the passive filter 11, the signal (which is analogue) is converted to a digital signal by means of an analogue-to-digital converter (ADC) and processed by means of digital filter(s) 12. Thus, the AC component is sufficiently suppressed to allow sufficiently precise measurement of the DC offset by means of a controller 13. The controller 13 can then compare the measured DC offset with a reference value for said offset, typically zero, and outputs a control signal based on the difference between the measured DC offset and the reference to the control arrangement 20 of the MMC. The controller 13 may e.g. be a P (proportional) controller, and an I (integral) controller or a PI (proportional-integral) controller. Since the DC offset correcting devices 10 may typically be at a different electrical potential than the MMC control 20, the control signalling there between may preferably be performed optically, via optical cables/fibres 21.

[0025] The MMC control 20 controls the semiconductor switches of the MMC taking into account the control signals received from the DC offset correcting devices 10, by mapping and applying to the phase-legs of the MMC. This controlling may be done by means of the MMC control 20 being connected to the respective driving circuits of the semiconductor switches of the converter cells of each phase-leg of the MMC. The DC offset may e.g. be corrected by delaying the commands for switching on and off in accordance with the voltage control signals from the DC offset correcting devices 10. If, for example, a positive DC offset is measured, the switches for switching on the positive half wave may be delayed until, as measured over one period, it is no longer possible to determine any DC offset. In the case of a negative DC offset, it is the commands for switching on the negative half wave which may be delayed.

[0026] FIG. 2a illustrates an embodiment of an MMC 1 having a double-wye topology of three phases 8 comprising phase-legs 9. Each of the phases 8.sub.A, 8.sub.B and 8.sub.C comprises an upper phase-leg 9.sub.U and a lower phase-leg 9.sub.L, making a total of six phase-legs 9 in the MMC. Each phase leg 9 comprises a plurality of N cascaded converter cells 2, as well as a phase-leg reactor (schematically illustrated as a coils in the figure). The MMC 1 is connected between two HV AC grids via respective power transformers 3, a first grid transformer 3a connected to a first HV AC grid on its primary side and to the MMC 1 on its secondary side, and a second grid transformer 3b connected to a second HV AC grid on its primary side and to the MMC 1 on its secondary side. The first HV AC grid is in the example of FIG. 2a a three-phase grid, e.g. a utility grid (e.g. having a fundamental frequency of 50 Hz). The first HV AC grid may have a voltage above 36 kV, such as above 100 kV or above 200 kV, e.g. 220 kV. The second HV AC grid is in the example of FIG. 2a a single-phase grid, e.g. a rail grid (e.g. having a fundamental frequency of 16.7 Hz or 50/3 Hz). The second HV AC grid may have a voltage above 36 kV, such as above 100 kV, e.g. 132 kV, or above 200 kV. As mentioned above, the respective voltages on the secondary sides of the transformers 3a and 3b, i.e. the output voltages of the MMC 1, are above 3.6 kV, e.g. of at least 4 kV or at least 10 kV, up to 36 kV. It should be noted that the respective voltages on the secondary sides of the transformers 3a and 3b (i.e. the MMC output voltages towards the first and second HV AC grids, respectively) do not have to be the same, although they may be the same in some applications. Since the HV phase legs 9 are typically positioned in a valve house, the phase-legs may be connected to the outside of the valve house via bushings 7 through a wall of the valve house.

[0027] In the embodiment of FIG. 2a, DC offset correcting devices 10 are connected to the respective output terminals of the MMC 1, one to the three-phase output terminals and one to the single-phase output terminals, via bushings 7 and voltage divider resistors 6, allowing the DC offset correcting devices 10 to obtain its respective HV AC signal from said output terminals. The DC offset correcting devices 10 are powered internally in the MMC via AC-to-DC converters 4 and transformers 5 (e.g. buck transformers), transforming the HV of a respective output terminal to low voltage (LV), e.g. a few hundred volts, such as within the range of 200-500 V, for powering the DC offset correcting device 10. All low voltage equipment may be mounted on an isolated platform and enough required insulation distance is given between the low voltage components and the high voltage equipment.

[0028] In the embodiment illustrated in FIG. 2a, a first side of the MMC 1 is connected to a three-phase utility grid via a first grid transformer 3a and a second side of the MMC is connected to a single-phase grid via a second grid transformer 3b. However, many other options for the second side of the MMC 1 may be relevant within the present invention. For instance, the second side of the MMC may be connected to a single-phase HV grid via a line reactor, instead of via a transformer 3b, in which case no DC offset correcting device 10 may be needed at the second side of the MMC. In another example, the second side of the MMC may not be connected to a grid at all, the MMC only being connected to the three-phase HV grid at its first side. In yet another example, the second side of the MMC 1 may be connected to a second three-phase HV grid, typically via a second transformer 3b, whereby the MMC 1 is connected between two different three-phase grids (or possibly between two different points in the same three-phase grid). Of course, the topology of the MMC 1 is adapted accordingly, the double-wye topology used as an example in the figures typically being used when the MMC is connected between a three-phase grid and a single-phase grid.

[0029] FIG. 2b illustrates an embodiment of a DC offset correcting arrangement which may be used in the MMC example of FIG. 2a. Two DC offset correcting devices 10 are used in the arrangement, one is on the secondary side of the three phase transformer 3a and the other one on the secondary side of the single phase transformer 3b. The first DC correcting device 10, is here the one connected in FIG. 2a to the three-phase output terminals, and the second DC correcting device 102 is here the one connected in FIG. 2a to the single-phase output terminals.

[0030] The DC offset (mV) is filtered out from the high voltage AC (up to 36 kV) by means of the passive filters 11 and the digital filters 12, as discussed above.

[0031] The balanced voltages between upper and lower phase-legs 9.sub.U and 9.sub.L, as well as the adjacent phase-legs together with the current controllers implemented in the MMC control 20 of the system make the DC component on the secondary side of the transformers extra low, but it may still be large enough to saturate the grid transformers 3.

[0032] It may be advantageous to measure the HV AC signals of the MMC output terminals since the signals will have the grid fundamental frequency (e.g. 50 Hz) and a minor DC offset. To filter out the DC, only one AC frequency must then be damped, giving a simpler filter design. In the example application in a double-Y topology as shown in FIG. 2b, two different passive filters 11a and 11b are designed to damp the utility grid frequency (typically 50 Hz), and the railway grid frequency (typically 16.7 Hz) is dampened in a separate DC offset correcting device.

[0033] The outputs of the controllers 13 may be transmitted via optical fibres 21 to other MMC controls 20. There, first, the outputs of the DC offset correcting devices 10 will be mapped to the phase legs 9. For instance, in the example of double-wye topology, the three outputs of the DC offset correcting devices 10 are mapped to six phase legs. The mapping is done so that the compensating DC component applied to phase legs will not be eliminated by other controller of the MMC. Second, the compensating DC component applying to the phase legs may be in a form of DC offset adding to the phase leg set points or its equivalents including modifying the firing pulses.

[0034] On each DC offset correcting device 10, there may be two independent measurement channels. For the three phase side, both channels are used to measure two signals (one is measured between phase 8.sub.A and phase 8.sub.C and the other is measured between phase 8.sub.B and phase 8.sub.C). Thus, there are shown two passive filters 11a and 11b, and two controllers 13a and 13b for the three-phase correcting device lot. For the single phase side, only one signal may be measured. Thus, only one channel is used. The other channel may also there but not used and not shown in the figures.

[0035] FIG. 3a illustrates an embodiment of an MMC 1 in which a DC offset correcting device is connected across each phase-leg 9, instead of to the output terminals as in the embodiment of FIG. 2a.

[0036] As for the embodiment of FIG. 2a, FIG. 3a illustrates an embodiment of an MMC 1 having a double-wye topology of three phases 8 comprising phase-legs 9. Each of the phases 8.sub.A, 8.sub.B and 8.sub.C comprises an upper phase-leg 9.sub.U and a lower phase-leg 9.sub.L, making a total of six phase-legs 9 in the MMC. Each phase leg 9 comprises a plurality of N cascaded converter cells 2, as well as a phase-leg reactor (schematically illustrated as a coils in the figure). The MMC 1 is connected between two HV AC grids via respective power transformers 3, a first grid transformer 3a connected to a first HV AC grid on its primary side and to the MMC 1 on its secondary side, and a second grid transformer 3b connected to a second HV AC grid on its primary side and to the MMC 1 on its secondary side. The first HV AC grid is in the example of FIG. 2a a three-phase grid, e.g. a utility grid (e.g. having a fundamental frequency of 50 Hz). The first HV AC grid may have a voltage above 36 kV, such as above 100 kV or above 200 kV, e.g. 220 kV. The second HV AC grid is in the example of FIG. 2a a single-phase grid, e.g. a rail grid (e.g. having a fundamental frequency of 16.7 Hz or 50/3 Hz). The second HV AC grid may have a voltage above 36 kV, such as above 100 kV, e.g. 132 kV, or above 200 kV. As mentioned above, the respective voltages on the secondary sides of the transformers 3a and 3b, i.e. the output voltages of the MMC 1, are above 3.6 kV, e.g. of at least 4 kV or at least 10 kV, up to 36 kV. It should be noted that the respective voltages on the secondary sides of the transformers 3a and 3b (i.e. the MMC output voltages towards the first and second HV AC grids, respectively) do not have to be the same, although they may be the same in some applications. Since the HV phase legs 9 are typically positioned in a valve house, the phase-legs may be connected to the outside of the valve house via bushings 7 through a wall of the valve house.

[0037] In the embodiment of FIG. 3a, DC offset correcting devices 10 are connected across each phase-leg 9 of the MMC 1, in this example resulting in a total of six DC offset correcting devices 10, via bushings 7 and voltage divider resistors 6, allowing the DC offset correcting devices 10 to obtain its respective HV AC signal from across said phase-legs. The DC offset correcting devices 10 are also in this case powered internally in the MMC, but may here be powered via DC-to-DC converters 4 connected to an intermediate DC circuit of a converter cell 2, without necessarily needing any transformers 5 (e.g. buck transformers), for powering the DC offset correcting device 10. All low voltage equipment may be mounted on an isolated platform and enough required insulation distance is given between the low voltage components and the high voltage equipment.

[0038] When measuring across the converter phase-legs, in contrast to measuring at the output terminals, the measurement input terminals of the DC offset correcting devices to are connected across the converter phase legs 9, to the phase-leg terminals. This solution provides the opportunity of using the power supplies of the converter cells. Therefore, they don't require buck type transformers 5 and AC/DC converter with high insulation. However, they may need an extra low power DC/DC power supply to isolate the ground potentials between the semiconductors gate units of the cell switches and the DC offset correcting device ground. Another point is in this embodiment there may be no need for long high voltage cables since the voltage divider resistors 6 will be distributed with the phase-legs.

[0039] The offset correcting devices to for the upper and lower phase legs 9.sub.U and 9.sub.L may be physically integrated with each other to one device with two measurement channels, as shown in FIG. 3c, or be two separate devices as shown in FIG. 3b. For the former, the DC offset devices may in this case have redundant power supplies.

[0040] Similar to the embodiment of FIGS. 2a and 2b, the DC offset component (mV) must be filtered out from the high voltage AC component (up to 36 kV). The DC component to be measured is expected to be larger than in the embodiment of FIGS. 2a and 2b. However, what is more challenging is that in this case signals to the DC offset correcting devices to may contain more than one fundamental frequency. Compared to the embodiment of FIGS. 2a and 2b, this may be a disadvantage (the filter design may be more challenging). In the example application in double-Y topology as shown in 3a, both the fundamental frequency from the three-phase utility grid (typically 50 Hz) and the single-phase railway grid (typically 16.7 Hz) will appear in the measurements of the DC offset correcting devices 10 and both frequency components must be damped to an acceptable level with the filters 11 and 12.

[0041] The outputs of the controllers 13 may be transmitted via optical fibres 21 to the MMC control 20. There, first, the outputs of the DC offset correcting devices 10 will be mapped to the phase legs 9. In the example application in double-Y MMC topology, six outputs of the DC offset correcting devices will be mapped to six phase-legs. This is to some extend more straight-forward than that in the embodiment of FIGS. 2a and 2b, because in the embodiment of FIGS. 3a-c each phase-leg 9 has a dedicated DC offset correcting device 10. However, care is taken in the mapping mechanism so that the compensating DC component applied to phase legs will not be eliminated by other controller in the MMC. Similarly, the compensating DC component applied to the phase legs may be in a form of DC offset adding to the phase leg set points or its equivalents including modifying the firing pulses.

[0042] Embodiments of the present invention may be used with any MMC topology. However, in some embodiments of the present invention, the HV AC grid is a three-phase (e.g. utility) grid. Additionally or alternatively, in some embodiments, the MMC is also connected to a second HV AC grid via a second grid transformer 3b and/or via a line reactor. In some embodiments, the second HV AC grid is a single-phase grid (e.g. a rail grid), whereby the MMC may have a double-wye topology. In other embodiments, the second HV AC grid is a second three-phase (e.g. utility) grid.

[0043] In some embodiments of the present invention, the high-voltage AC signal is obtained from an output terminal of the MMC 1. In some embodiments, a first of the DC offset correcting devices 10 is connected to the three-phase output terminals of the MMC to the first grid transformer 3a. If the MMC is connected to a single-phase HV AC grid, a second of the DC offset correcting devices 10 may be connected to the single-phase output terminals of the MMC to the second grid transformer 3b or line reactor.

[0044] In some other embodiments, the high-voltage AC signal is obtained across a phase leg 9 of the MMC 1. In some embodiments, for each of the phase legs 9 of the MMC, one of the at least one DC offset correcting devices to is connected across said phase leg.

[0045] In some embodiments of the present invention, each of the at least one DC offset correcting device 10 is powered internally in the MMC 1 via a power supply. The power supply may comprise an AC-to-DC converter connected to an output terminal of the MMC 1 via a buck transformer 5, or a DC-to-DC converter connected to the intermediate DC circuit of a converter cell 2 of the MMC 1.

[0046] In some embodiments of the present invention, the control signal is transmitted from each DC offset correcting device 10 to the MMC control device 20 via optical cable(s) 21.

[0047] The present disclosure has mainly been described above with reference to a few embodiments. However, as is readily appreciated by a person skilled in the art, other embodiments than the ones disclosed above are equally possible within the scope of the present disclosure, as defined by the appended claims.