Power amplification module

Abstract

Provided is a power amplification module that includes: a first transistor, a first signal being inputted to a base thereof; a second transistor, the first signal being inputted to a base thereof and a collector thereof being connected to a collector of the first transistor; a first resistor, a first bias current being supplied to one end thereof and another end thereof being connected to the base of the first transistor; a second resistor, one end thereof being connected to the one end of the first resistor and another end thereof being connected to the base of the second transistor; and a third resistor, a second bias current being supplied to one end thereof and another end thereof being connected to the base of the second transistor.

Claims

1. A power amplification module comprising: a first transistor, a first signal being inputted to a base of the first transistor; a second transistor, the first signal being inputted to a base of the second transistor and a collector of the second transistor being connected to a collector of the first transistor; a third transistor, the first signal being inputted to a base of the third transistor, and a collector of the third transistor being connected to the collector of the second transistor; a first resistor, a first bias current being supplied to a first end of the first resistor and a second end of the first resistor being connected to the base of the first transistor; a second resistor, a first end of the second resistor being connected to the first end of the first resistor, and a second end of the second resistor being connected to the base of the second transistor; and a third resistor, a second bias current being supplied to a first end of the third resistor and a second end of the third resistor being connected to the base of the third transistor, wherein: when the power amplification module operates in a first mode, the first bias current is supplied to the base of the first transistor via the first resistor and to the base of the second transistor via the second resistor, and the second bias current is supplied to the base of the third transistor via the third resistor, when the power amplification module operates in a second mode the first bias current is supplied to the base of the first transistor via the first resistor and to the base of the second transistor via the second resistor, and the second bias current is supplied to the base of the third transistor via the third resistor, and when the power amplification module operates in the second mode, the second bias current has a value that is non-zero and that is less than a value of the first bias current.

2. The Power amplification module according to claim 1, further comprising: a fourth transistor, the first signal being inputted to a base of the fourth transistor and a collector of the fourth transistor being connected to the collector of the first transistor; and a fourth resistor, a first end of the fourth resistor being connected to the first end of the third resistor and a second end of the fourth resistor being connected to the base of the fourth transistor.

3. The Power amplification module according to claim 1, wherein the value of the second bias current is between 20% and 80% of the value of the first bias current.

4. The Power amplification module according to claim 2, wherein the value of the second bias current is between 20% and 80% of the value of the first bias current.

5. The Power amplification module according to claim 1, further comprising: a bias control circuit configured to control the value of the second bias current and to control the value of the first bias current, wherein the bias control circuit is a current-control-type bias control circuit.

6. The Power amplification module according to claim 2, further comprising: a bias control circuit configured to control the value of the second bias current and to control the value of the first bias current, wherein the bias control circuit is a current-control-type bias control circuit.

7. The Power amplification module according to claim 3, further comprising: a bias control circuit configured to control the value of the second bias current and to control the value of the first bias current, wherein the bias control circuit is a current-control-type bias control circuit.

8. The Power amplification module according to claim 4, further comprising: a bias control circuit configured to control the value of the second bias current and to control the value of the first bias current, wherein the bias control circuit is a current-control-type bias control circuit.

9. The Power amplification module according to claim 1, further comprising: a first bias circuit connected to the first transistor and to the second transistor; and a second bias circuit connected to the third transistor, wherein when the power amplification module operates in the second mode, the first bias circuit is configured to supply the first bias current and the second bias circuit is configured to supply the second bias current.

10. The Power amplification module according to claim 1, further comprising: a first bias circuit connected to the first transistor and to the second transistor, and configured to supply the first bias current; and a second bias circuit connected to the third transistor, and configured to supply the second bias current, wherein when the power amplification module operates in the first mode, the value of the first bias current is substantially the same as the value of the second bias circuit.

11. The Power amplification module according to claim 10, wherein: values of the first and second bias currents when the power amplification module operates in the first mode are greater than the values of the first and second bias currents when the power amplification module operates in the second mode, and the value of the first bias current when the power amplification module operates in the second mode is greater than the value of the second bias current when the power amplification module operates in the second mode.

Description

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

(1) FIG. 1 illustrates an example configuration of a transmission unit that includes a power amplification module according to an embodiment of the present disclosure;

(2) FIG. 2 illustrates an example of the configuration of a power amplification module;

(3) FIG. 3 is a diagram for explaining the operation of the power amplification module in the case of a high gain mode;

(4) FIG. 4 is a diagram for explaining the operation of the power amplification module in the case of a low gain mode;

(5) FIG. 5 illustrates an example of the relationship between the number of transistors and a change in gain; and

(6) FIG. 6 illustrates an example of the relationship between the number of transistors and the voltage standing wave ratio.

(7) FIG. 7 illustrates an example of the configuration of a power amplification module according to a second embodiment of the present disclosure.

(8) FIG. 8 illustrates a graph of changes in gain in the power amplification module of the second embodiment illustrated FIG. 7.

(9) FIG. 9 illustrates a graph of changes in VSWR in the power amplification module of the second embodiment illustrated FIG. 7.

(10) FIG. 10 illustrates an example of the configuration of a power amplification module according to a modification of the second embodiment illustrated in FIG. 7.

DETAILED DESCRIPTION OF THE DISCLOSURE

(11) Hereafter, an embodiment of the present disclosure will be described while referring to the drawings. FIG. 1 illustrates an example configuration of a transmission unit that includes a power amplification module according to an embodiment of the present disclosure. A transmission unit 100 is for example used in a mobile communication device such as a cellular phone in order to transmit various signals such as speech and data to a base station. Although such a mobile communication device would also be equipped with a reception unit for receiving signals from the base station, the description of such a reception unit is omitted here.

(12) As illustrated in FIG. 1, the transmission unit 100 includes a modulator 110, a power amplification module 120, a front end unit 130 and an antenna 140.

(13) The modulator 110 modulates an input signal on the basis of a modulation scheme such as high speed uplink packet access (HSUPA) or long term evolution (LTE) and generates a radio frequency (RF) signal for performing wireless transmission. The RF signal has a frequency of around several hundred MHz to several GHz, for example.

(14) The power amplification module 120 amplifies the power of the RF signal (RF.sub.IN) outputted from the modulator 110 up to the level that is required to transmit the RF signal to the base station, and outputs an amplified signal (RF.sub.OUT). The power amplification module 120 operates in a gain mode that corresponds to a gain mode control voltage V.sub.MODE. The gain mode may be a high gain mode or a low gain mode, for example.

(15) The front end unit 130 filters the amplified signal and switches a reception signal received from the base station. The amplified signal outputted from the front end unit 130 is transmitted to the base station via the antenna 140.

(16) FIG. 2 illustrates an example of the configuration of the power amplification module 120. The power amplification module 120 includes transistors T1, T2, T3 and T4, capacitors C1, C2, C3, C4 and C5, resistors R11, R12, R13, R14, R23 and R24, an inductor L1, bias circuits 200 and 210 and a bias control circuit 220.

(17) The transistors T1 to T4 are amplification transistors and are heterojunction bipolar transistors (HBTs), for example. The transistors T1 to T4 are connected in parallel with one another and form a single amplification circuit. Each of the transistors T1 to T4 can serve as one finger of a multi-finger transistor. The RF signal (RF.sub.IN) is inputted to the bases of the transistors T1 to T4 via the capacitors C1 to C4, respectively. In addition, a power supply voltage V.sub.CC is supplied to the collectors of the transistors T1 to T4 via the inductor L1. The transistors T1 to T4 output the amplified signal (RF.sub.OUT) of the RF signal (RF.sub.IN) from their collectors via the capacitor C5.

(18) A bias current I.sub.BIAS1 is supplied to one end of the resistor R11 and the other end of the resistor R11 is connected to the base of the transistor T1. The bias current I.sub.BIAS1 is supplied to one end of the resistor R12 and the other end of the resistor R12 is connected to the base of the transistor T2. The bias current I.sub.BIAS1 is supplied to one end of the resistor R13 and the other end of the resistor R13 is connected to the base of the transistor T3. The bias current I.sub.BIAS1 is supplied to one end of the resistor R14 and the other end of the resistor R14 is connected to the base of the transistor T4. A bias current I.sub.BIAS2 is supplied to one end of the resistor R23 and the other end of the resistor R23 is connected to the base of the transistor T3. The bias current I.sub.BIAS2 is supplied to one end of the resistor R24 and the other end of the resistor R24 is connected to the base of the transistor T4.

(19) The bias circuit 200 generates the bias current I.sub.BIAS1 on the basis of a bias control voltage V.sub.BIAS1. The bias circuit 200 includes a transistor T31, for example. The transistor T31 is an HBT, for example. The bias control voltage V.sub.BIAS1 is supplied to the base of the transistor T31, the power supply voltage V.sub.CC is supplied to the collector of the transistor T31 and the emitter of the transistor T31 is connected to one end of each of the resistors R11 to R14.

(20) The bias circuit 210 generates the bias current I.sub.BIAS2 on the basis of a bias control voltage V.sub.BIAS2. The bias circuit 210 includes a transistor T32, for example. The transistor T32 is an HBT, for example. The bias control voltage V.sub.BIAS2 is supplied to the base of the transistor T32, the power supply voltage V.sub.CC is supplied to the collector of the transistor T32 and the emitter of the transistor T32 is connected to one end of each of the resistors R23 and R24.

(21) The bias control circuit 220 controls the bias control voltages V.sub.BIAS1 and V.sub.BIAS2 on the basis of the gain mode control voltage V.sub.MODE Specifically, at the time of the high gain mode, the bias control circuit 220 makes the bias control voltage V.sub.BIAS1 be at a high level and the bias control voltage V.sub.BIAS2 be at a low level. In addition, at the time of the low gain mode, the bias control circuit 220 makes the bias control voltage V.sub.BIAS2 be at the high level and the bias control voltage V.sub.BIAS1 be at the low level. The high level is a voltage that is higher than a threshold voltage at which the transistors T31 and T32 that form the bias circuits 200 and 210 switch on and the low level is a voltage that is lower than this threshold voltage.

(22) Referring to FIGS. 3 and 4, an example of the operation of the power amplification module 120 will be described.

(23) FIG. 3 is a diagram for explaining the operation of the power amplification module 120 in the case of the high gain mode. In the case of the high gain mode, the bias control circuit 220 makes the bias control voltage V.sub.BIAS1 be at the high level and the bias control voltage V.sub.BIAS2 be at the low level. Thus, the transistor T31 of the bias circuit 200 is switched on and the transistor T32 of the bias circuit 210 is switched off. The bias current I.sub.BIAS1 is outputted from the bias circuit 200.

(24) The bias current I.sub.BIAS1 is supplied to the base of the transistor T1 via the resistor R11. Similarly, the bias current I.sub.BIAS1 is supplied to the bases of the transistors T2 to T4 via the resistors R12 to R14, respectively. Thus, the transistors T1 to T4 are switched on and the RF signal (RF.sub.IN) is amplified by the transistors T1 to T4.

(25) FIG. 4 is a diagram for explaining the operation of the power amplification module 120 in the case of the low gain mode. In the case of the low gain mode, the bias control circuit 220 makes the bias control voltage V.sub.BIAS1 be at the low level and the bias control voltage V.sub.BIAS2 be at the high level. Thus, the transistor T31 of the bias circuit 200 is switched off and the transistor T32 of the bias circuit 210 is switched on. The bias current I.sub.BIAS2 is outputted from the bias circuit 210.

(26) The bias current I.sub.BIAS2 is supplied to the base of the transistor T3 via the resistor R23. Similarly, the bias current I.sub.BIAS2 is supplied to the base of the transistor T4 via the resistor R24. Thus, the transistors T3 and T4 are switched on.

(27) The bias current I.sub.BIAS2 is supplied to the base of the transistor T1 via the resistors R23, R13 and R11. Similarly, the bias current I.sub.BIAS2 is supplied to the base of the transistor T2 via the resistors R23, R13 and R12. In addition, the bias current I.sub.BIAS2 is supplied to the base of the transistor T1 via the resistors R24, R14 and R11. In addition, the bias current I.sub.BIAS2 is supplied to the base of the transistor T2 via the resistors R24, R14 and R12. However, the amount of the current supplied to the bases of the transistors T1 and T2 is small compared with the amount of the current supplied to the transistors T3 and T4. Consequently, although the transistors T1 and T2 are not entirely switched off, the size of the emitter current per unit emitter area is small compared with that for the transistors T3 and T4. Therefore, the gain generated by the transistors T1 to T4 is smaller than that in the case of the high gain mode illustrated in FIG. 3.

(28) As described with reference to FIGS. 3 and 4, in the power amplification module 120, the transistors T1 to T4 are switched on by the bias current I.sub.BIAS1 being supplied to the bases of the transistors T1 to T4 in the case of the high gain mode. In addition, in the case of the low gain mode, the bias current I.sub.BIAS2 is supplied to the bases of the transistors T3 and T4 and the transistors T3 and T4 are switched on. Furthermore, the bias current I.sub.BIAS2 is also supplied to the bases of the transistors T1 and T2 via the resistors R13 and R14 and the transistors T1 and T2 enter a state of not being completely switched off.

(29) In the power amplification module 120, the gain can be made to change through this type of operation. In the power amplification module 120, since the transistors T1 and T2 are not completely switched off in the case of the low gain mode, the change in the input impedance can be suppressed compared with the case where the transistors T1 and T2 are completely switched off.

(30) In the power amplification module 120, the number of transistors that form the amplification circuit is four, but the number is not limited to this. Furthermore, in the power amplification module 120, the number of transistors for which the size of the supplied bias current becomes small at the time of the low gain mode is two (transistors T1 and T2), but the number is not limited to this. For example, the number of transistors for which the size of the supplied bias current becomes small at the time of the low gain mode may be three (for example, transistors T1 to T3) or one (for example, transistor T1).

(31) Referring to FIGS. 5 and 6, the characteristics of the power amplification module 120 will be described.

(32) FIG. 5 illustrates an example of the relationship between the number of transistors and the change in gain. The horizontal axis represents the number of transistors that are completely switched on and the vertical axis represents the change in gain, with a state in which the number of transistors that are directly contributing to amplification (that are completely switched on) is four serving as a reference.

(33) In FIG. 5, the solid line represents an example of the simulation results for the same configuration as that of the power amplification module 120 of this embodiment (configuration in which a current is also supplied to transistors that do not directly contribute to amplification). In addition, the broken line represents an example of the simulation results for a typical configuration in which a current is not supplied to transistors that do not directly contribute to amplification. As illustrated in FIG. 5, in the same configuration as that of the power amplification module 120, the gain can be reduced by decreasing the number of transistors that directly contribute to amplification (are completely switched on) at the time of the low gain mode.

(34) FIG. 6 illustrates an example of the relationship between the number of transistors and the voltage standing wave ratio. The horizontal axis represents the number of transistors that are completely switched on and the vertical axis represents the voltage standing wave ratio at the input of the power amplification module (input VSWR).

(35) In FIG. 6, the solid line represents an example of the simulation results for the same configuration as that of the power amplification module 120 (configuration in which a current is also supplied to transistors that do not directly contribute to amplification). In addition, the broken line represents an example of the simulation results for a typical configuration in which a current is not supplied to transistors that do not directly contribute to amplification. As illustrated in FIG. 6, in the same configuration as that of the power amplification module 120, since there are transistors that are not completely switched off at the time of the low gain mode, the change in input impedance is suppressed and as a result the degradation of the input VSWR can be suppressed.

(36) An exemplary embodiment of the present disclosure has been described above. According to the power amplification module 120, the transistors T1 and T2 are not completely switched off at the time of the low gain mode. Consequently, a change in the input impedance that occurs with a change in the gain can be suppressed in the power amplification module 120.

(37) Although the power amplification module 120 is a single-stage amplification circuit, the present disclosure can be similarly applied to an amplification circuit having two or more stages. In the case where the present disclosure is applied to an amplification circuit having two or more stages, the same configuration may be adopted in all of the stages or the same configuration may be adopted in only some of the stages.

(38) FIG. 7 illustrates a power amplifier 120B according to a second embodiment of the present disclosure. Description of points that are common to this embodiment and FIG. 2 and description of similar configurations are omitted. In the configuration illustrated in FIG. 7, only resistors R11 and R12 are connected to the emitter of the transistor T31. In other words, relative to the configuration illustrated in FIG. 2, the resistor R13 and the resistor R14 have been removed in the configuration illustrated in FIG. 7. In the case of this configuration, in a high power mode operation (a high gain mode), bias control voltages V.sub.BIAS1 and V.sub.BIAS2 are respectively supplied to the bases of the transistor T31 and the transistor T32, and bias currents I.sub.BIAS1 and I.sub.BIAS2 are supplied from the respective emitters of the transistor T31 and the transistor T32 to the bases of the transistors T1 to T4 via the resistors R11, R12, R23, and R24. In an ideal state, the bias control voltages V.sub.BIAS1 and V.sub.BIAS2 would have identical values and the bias currents I.sub.BIAS1 and I.sub.BIAS2 would also have identical values and be equal to Icurrent1. However, there will be a certain difference due to processing variations, but these parameters should still have substantially identical values. On the other hand, when operating in a low power mode (a low gain mode), the input impedances of the transistors T1 to T4 seen from RF.sub.IN change by a large amount compared with at the time of the high power mode due to the transistors T3 and T4 being completely turned off. Therefore, to prevent input of an RF signal from being obstructed to an increase in VSWR, when operating in the low power mode, a bias control voltage V.sub.BIAS1 is supplied to the base of the transistor T31 from the bias control circuit 220. A bias control voltage V.sub.BIAS2 is supplied to the base of the transistor T32 from the bias control circuit 220. A bias control voltage V.sub.BIAS2 is a lower voltage than a bias control V.sub.BIAS1. As a result, a bias current I.sub.BIAS2 (Current 3), which is smaller than the bias current I.sub.BIAS1 (Current 2) that flows to the emitter of the transistor T31, flows to the emitter of the transistor T32. Since the current I.sub.BIAS2 is smaller than the current I.sub.BIAS1, the transistor T3 and the transistor T4 can be switched to a state that is not completely switched off.

(39) As a result of being switched to this state, as illustrated in FIGS. 5 and 6, changes in VSWR can be suppressed while providing a difference in gain. In this configuration, the transistors T1 to T4 are switched on at the time of the high power mode, and in the low power mode it is necessary for the transistors T3 and T4 to be not completely switched off while the transistors T1 and T2 are switched on. The configuration illustrated in FIG. 7 involves more complex control compared with the configuration illustrated in FIG. 2. The values of the currents at the time of the high power mode and the low power mode are illustrated in Table 1, where Current 1>Current 2>Current 3.

(40) Here, in order to find the appropriate value of Current 3, a simulation was performed in order to check the changes in gain and VSWR that occur when the bias current I.sub.BIAS1 is constant and the bias current I.sub.BIAS2 is varied. The simulation was based on four drive stage transistors with two transistors driven by each of the transistor T31 and by the transistor T32.

(41) FIG. 8 illustrates a graph of changes in gain where the horizontal axis represents a ratio between the bias current I.sub.BIAS2 that flows to the emitter of the transistor T32 and the bias current I.sub.BIAS1 that flows to the emitter of the transistor T31. When the value of the bias current I.sub.BIAS2 is identical to that of the current I.sub.BIAS1 (Current 2), the gain is 16.5 dB. When the current I.sub.BIAS2 does not flow (i.e., 0.0%), the gain is 13.6 dB. It is clear that the gain changes in a substantially linear manner as the bias current I.sub.BIAS2 changes.

(42) FIG. 9 illustrates a graph of changes in VSWR where the horizontal axis represents a ratio between the bias current I.sub.BIAS2 that flows to the emitter of the transistor T32 and the bias current I.sub.BIAS1 that flows to the emitter of the transistor T31. As is clear from the figure, it is clear that VSWR is 2 in the case where the bias current I.sub.BIAS2 does not flow (i.e., 0.0%) and that the value of VSWR approaches 1.4 as the value of the bias current I.sub.BIAS2 approaches the value of the bias current I.sub.BIAS1. However, in contrast to the changes in gain illustrated in FIG. 8, VSWR does not change linearly. In particular, as the bias current I.sub.BIAS2 approaches 0, VSWR changes sharply. Therefore, from the viewpoint of changes in the VSWR characteristic and gain, the gain is less than 16.5 and VSWR is less than 1.8 in a range in which the bias current I.sub.BIAS2 is between 20% and 80% of the current I.sub.BIAS1. Therefore, when operating in the low power mode, a suitable range for Current 3 is from 20% to 80% of Current 2.

(43) TABLE-US-00001 TABLE 1 Sizes of emitter currents of transistor T31 and transistor T32 in second and third embodiments. I.sub.BIAS1 I.sub.BIAS2 High Power Current 1 Current 1 Mode (High Gain Mode) Low Power Mode Current 2 Current 3 (Low Gain Mode)

(44) FIG. 10 illustrates a power amplifier 120C according to a modification of the second embodiment illustrated in FIG. 7. The configuration illustrated in FIG. 10 differs from the configuration illustrated in FIG. 7 in that the bias control circuit 220 is replaced with a bias control circuit 220B that is a current-control-type bias control circuit that supplies currents Icontrol1 and Icontrol2 to the bases of the transistor T31 and the transistor T32. Due to this configuration, the sensitivity with which the emitter currents of the transistor T31 and the transistor T32 can be adjusted is low compared with the voltage-control-type configuration, and therefore control is easier. Therefore, it is possible to more finely control adjustment of VSWR and adjustment of gain at the time of the low power mode. The values of the bias currents I.sub.BIAS1 and I.sub.BIAS2 are hfe (current amplification factor) times as large as the values of the currents that flow to the bases of the transistors T31 and T32, and therefore there is a proportional relationship between the currents Icontrol1 and Icontrol2. Therefore, it may be said that the value of the current Icontrol2 when operating in the low power mode suitably lies between 20% and 80% of the current Icontrol1.

(45) The purpose of the embodiments described above is to enable easy understanding of the present disclosure and the embodiments are not to be interpreted as limiting the present disclosure. The present disclosure can be modified or improved without departing from the gist of the disclosure and equivalents to the present disclosure are also included in the present invention. In other words, appropriate design modifications made to the embodiments by one skilled in the art are included in the scope of the present disclosure so long as the modifications have the characteristics of the present disclosure. For example, the elements included in the embodiments and the arrangements, materials, conditions, shapes, sizes and so forth of the elements are not limited to those exemplified in the embodiments and can be appropriately changed. In addition, the elements included in the embodiments can be combined as much as technically possible and such combined elements are also included in the scope of the present disclosure so long as the combined elements have the characteristics of the present disclosure.

(46) While preferred embodiments of the disclosure have been described above, it is to be understood that variations and modifications will be apparent to those skilled in the art without departing from the scope and spirit of the disclosure. The scope of the disclosure, therefore, is to be determined solely by the following claims.