WIDE BAND BUFFER WITH DC LEVEL SHIFT AND BANDWIDTH EXTENSION FOR WIRED DATA COMMUNICATION

Abstract

A wide band communications circuit buffer can include a pair of NPN bipolar transistor emitter followers deployed as a voltage buffer and disposed at inputs before and outputs after an equalization module, and a pair of diode connected NPN transistors deployed as a level shifter and disposed following the emitter followers before an output of the wide band driver to keep an output level at the output of the wide band buffer close to a desired level. Resistors connected between emitters and a V.sub.EE terminal can be used to further adjust the DC level. An LC tank filter can be provided between emitters of the voltage buffer components and the circuit's outputs to pass and boost high frequency signals provided to next stage components. The wide band buffer is, inter alia, appropriate for use in providing a DC level shift function as used in wired data communication systems circuitry.

Claims

1. A wide band communication circuit, comprising: a pair of NPN bipolar transistor emitter followers deployed as a voltage buffer and disposed at inputs before and outputs after an equalization module; and a pair of diode connected NPN transistors deployed as a level shifter and disposed following the pair of NPN bipolar transistor emitter followers at the outputs to maintain an output level at a desired level.

2. The wide band communication circuit of claim 1, further comprising a resistor disposed between a V.sub.EE terminal and emitters of at least one of the pair of NPN bipolar transistor emitter followers and the pair of diode connected NPN transistors to enable further adjustment of the desired level.

3. The wide band communication circuit of claim 1, further comprising a LC tank filter disposed between emitters of the pair of NPN bipolar transistor emitter followers and the outputs to boost signal bandwidth for high-speed communication applications.

4. The wide band communication circuit of claim 1, wherein the desired level is settable at an input level coming into a prior stage disposed before the voltage buffer.

5. The wide band communication circuit of claim 1, wherein the desired level is settable to an input level needed by a subsequent stage disposed after the voltage buffer.

6. A wide band communication circuit, comprising: a pair of NPN bipolar transistor emitter followers deployed as a voltage buffer and disposed at inputs before and outputs after an equalization module; a pair of diode connected NPN transistors deployed as a level shifter and disposed following the pair of NPN bipolar transistor emitter followers at the outputs to maintain an output level from the outputs at a desired level; a resistor disposed between a V.sub.EE terminal and emitters of at least one of the pair of NPN bipolar transistor emitter followers and the pair of diode connected NPN transistors to enable further adjustment of the output level; and an LC tank filter disposed between emitters of the pair of NPN bipolar transistor emitter followers and the output of the wide band buffer to boost signal bandwidth from the outputs for high-speed communications applications.

7. The wide band communication circuit of claim 6, wherein the desired level is settable at an input level coming into a prior stage disposed before the inputs.

8. The wide band communication circuit of claim 6, wherein the desired level is settable to an input level needed by a subsequent stage disposed after the outputs.

9. The wide band communication circuit of claim 6, wherein a resistor is disposed between the V.sub.EE terminal and emitters of the pair of NPN bipolar transistor emitter followers and the pair of diode connected NPN transistors to enable further adjustment of the output level.

10. The wide band communication circuit of claim 9, wherein the desired level is settable at an input level coming into a prior stage disposed before the inputs.

11. The wide band communication circuit of claim 9, wherein the desired level is settable at an input level needed by a subsequent stage disposed after the outputs.

12. A wide band communication circuit, comprising: a CTLE buffer connected along a circuit input and a CTLE to set a DC level for input signals to CTLE inputs of the CTLE and isolate the circuit input from the CTLE inputs; and a TX PreDriver connected before a TX Driver after the CTLE at CTLE outputs to isolate the TX Driver from the CTLE and maintain the DC level of the input signals for a TX Driver input.

13. The wide band communication circuit of claim 12, wherein the CTLE buffer comprises bipolar transistors.

14. The wide band communication circuit of claim 12, wherein the TX Driver is a differential pair adapted to drive a termination load disposed at a TX Driver output.

15. The wide band communication circuit of claim 14, further comprising parasitic capacitors disposed at the TX Driver output in association with the termination load disposed at the TX Driver output.

16. The wide band communication circuit of claim 12, wherein the CTLE buffer is a wide band buffer adapted to provide signal buffering and level shift functions by including a pair of emitter follower transistors Q1 and Q2 at the CTLE inputs to buffer the input signals.

17. The wide band communication circuit of claim 16, further comprising a pair of bipolar transistors Q3 and Q4 to shift common mode voltage levels from outputs of the pair of emitter follower transistors Q1 and Q2 to a common mode voltage needed by a next stage component.

18. The wide band communication circuit of claim 17, further comprising at least one of an R1 disposed between a V.sub.EE terminal and a Q1 emitter, an R2 disposed between the V.sub.EE terminal and a Q2 emitter, an R3 disposed the V.sub.EE terminal and a Q3 emitter, and an R4 disposed the V.sub.EE terminal and a Q4 emitter to further adjust the common mode voltage, wherein the common mode voltage is Vout, V.sub.cm_outV.sub.cm.sub.inR.sub.1I.sub.E+R.sub.3I.sub.C, supposing V.sub.BE3=V.sub.BE1 and V.sub.BE4=V.sub.BE2 if an emitter area ratio A.sub.1/A.sub.3 and A.sub.2/A.sub.4 is equal to an emitter current ratio I.sub.E/I.sub.C.

19. The wide band communication circuit of claim 18, further comprising a pair of LC tank circuits disposed between emitters of Q1 and Q2 and the CTLE outputs to pass and boost signals to a next stage component.

20. The wide band communication circuit of claim 19, wherein the pair of LC tank circuits is adapted to block positive and negative low frequency signals, including the DC level, passing through paths Q1-R1-R3-Q3 and Q2-R2-R4-Q4, respectively.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0017] FIG. 1, labeled as prior art, depicts a wiring diagram of a generally known communication channel.

[0018] FIG. 2 depicts a wiring diagram of a linear re-driver with buffers provided in accordance with an embodiment.

[0019] FIG. 3 depicts a wide band buffer in accordance with an embodiment.

[0020] FIG. 4 depicts a chart of the AC response signals for a low speed, high speed and complete buffer in accordance with an embodiment.

[0021] FIG. 5 depicts an alternate embodiment of a bias circuit for a wide band buffer as part of a wide band communication system.

[0022] Throughout the description, similar reference numbers may be used to identify similar elements.

DETAILED DESCRIPTION

[0023] It will be readily understood that the components of the embodiments as generally described herein and illustrated in the appended Figs. could be arranged and designed in a wide variety of different configurations. Thus, the following more detailed description of various embodiments, as represented in the Figures, is not intended to limit the scope of the present disclosure, but is merely representative of various embodiments. While the various aspects of the embodiments are presented in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

[0024] The present invention may be embodied in other specific forms without departing from its spirit or essential characteristics. The described embodiments are to be considered in all respects only as illustrative and not restrictive. The scope of the embodiments is, therefore, indicated by the appended claims rather than by this detailed description. All changes which come within the meaning and range of equivalency of the claims are to be embraced within their scope.

[0025] Reference throughout this specification to features, advantages, or similar language does not imply that all of the features and advantages that may be realized with the present invention should be or are in any single embodiment. Rather, language referring to the features and advantages is understood to mean that a specific feature, advantage, or characteristic described in connection with an embodiment is included in at least one embodiment of the present invention. Thus, discussions of the features and advantages, and similar language, throughout this specification may, but do not necessarily, refer to the same embodiment.

[0026] Furthermore, the described features, advantages, and characteristics of the invention may be combined in any suitable manner in one or more embodiments. One skilled in the relevant art will recognize, in light of the description herein, that the invention can be practiced without one or more of the specific features or advantages of a particular embodiment. In other instances, additional features and advantages may be recognized in certain embodiments that may not be present in all embodiments of the invention.

[0027] Reference throughout this specification to one embodiment, an embodiment, or similar language means that a particular feature, structure, or characteristic described in connection with the indicated embodiment is included in at least one embodiment of the present invention. Thus, the phrases in one embodiment, in an embodiment, and similar language throughout this specification may, but do not necessarily, all refer to the same embodiment.

[0028] FIG. 1, labeled as prior art, illustrates a typical architecture of a high-speed wide band data communication system 100, typically provided in the form of a circuit in a microchip, incorporating buffers 101, 102, 103 therein, but preferably the buffers would be modified with features in accordance with the present embodiments. Usually such a system includes a receiver/equalizer 105, amplifier 110, such as a programmable gain amplifier (PGA), and a transmitter/driver 115. Each of these blocks can be provided as one stage or multiple stages. Without buffers included in the circuit, as shown with buffer 101 disposed (i.e., connected) before receiver/equalizer stage 105, or buffer 102 and buffer 103 as respectively shown disposed in-between amplifier 110 and transmitter/driver 115 stages, the stages may less effectively provide their intended functions (e.g., amplification and transmission) because of loading experienced from the following stage. For example, without buffers 102, in between receiver/equalizer stage 105 and amplifier 110, and buffer 103 in between amplifier 110 and transmitter/driver 115, the output common mode voltage of the previous stage may not meet the requirements of a following stage. Most times, the system may have buffers (i.e., 102, 103) connected in between each stage (i.e., 105, 110, 115) of a high-speed wide band data communication system 100 as depicted in FIG. 1. As stated in the background, however, intermediate buffers used between each stage in the past have proven to consume more power than the equalizer, amplifier and drivers themselves, which makes a better, more efficient, design of a buffer block more critical for wide band, high-speed communications systems. The present inventors now disclose such improvements for wide bandwidth communication circuitry wherefrom power consumption can be reduced leading to more efficiency.

[0029] Illustrated in FIG. 2 is a wiring diagram of a wide band communications system 200, incorporating the embodiments. A high frequency linear driver circuit such as the wide band communications system 200 illustrated in FIG. 2 can include an equalization block 201 and a transmission block 202, which can be used in, for example, USB/HDMI/DP/Thunderbolt/PCIe/CIO data communication paths. An equalization block 201 can include a CTLE 210 (continuous-time-linear-equalizer), while a transmission block 202 can include a TX driver 220 (transmitter driver) with or without a PGA, depending on the actual implementation. The TX Driver 220 can be a differential pair of transistors adapted to drive a termination load disposed at a TX Driver output. Output from the TX driver 220 typically drives about a 50-Ohm load termination 230 at its outputs, which is shown as a Transmit Termination (TXT) within the dashed box positioned after the transmission block 202. A similar 50-Ohm load 203 can also be found to affect the inputs of the equalization block 201, which is shown as a Receive Termination (RXT) within the dashed box positioned before the equalization block 201. A CTLE buffer 205 (BUF) provided as designed in accordance with the embodiments can be disposed inline before the CTLE 210 as well as for TX pre-driver 215 (PDR) disposed inline before the TX driver 220, after the CTLE 210, in the wide band communications system 200.

[0030] TX driver 220 can be provided as a simple differential pair to drive what is typically a 50-Ohm load termination (see FIG. 2, 50-Ohm load termination 230). But this can call for the differential pair transistors to be relatively large devices. Furthermore, parasitic capacitors when provided at the TX output can load CTLE 210 and impact its performance. So an improved TX pre-driver 215 is needed to operate as a redriver circuit and to isolate CTLE 210 from TX driver 220 and also drive the long routing path from CTLE 210 to TX driver 220. Buffers used in such a circuit can provide a desired DC level for TX driver input, which can be a key factor for Low Supply Voltage due to headroom challenges to achieve high linearity. High linearity is often an important specification parameter for a linear redriver. The desired DC level for TX driver input can be at the DC or common mode level of the output from a prior stage closest to the input, or at whatever input level is selected by design or is needed for the next stage in the wide band communications circuit (e.g., the desired level). Although circuit design requirements can dictate variations for what the desired level after the emitter followers may be, it can commonly be determined that the output be kept at or above the DC or input common mode level (e.g., the input) entering the wide band buffer. The desired level therefore can be settable at a level for inputs coming into a prior stage disposed before a circuit's inputs or at a level needed by a subsequent stage disposed after outputs of the circuit.

[0031] A detailed diagram for wide band communication circuit 300 including wideband buffer capabilities that can be provided in accordance with the embodiments is depicted in FIG. 3. The architecture of this wide band communication circuit 300 can be used to provide the signal buffering and level shift functions desirable for wide band communications systems, including those depending on low voltage systems. It can also be used to boost the high frequency gain of a communications circuit to expand the bandwidth of signals. It can be used to fulfill the predriver and redriver requirements described with respect to FIG. 2. Using bipolar transistors, which can be provided in BiCMOS technology, the input stage typically needs a certain DC level (e.g., set at the DC common mode voltage level, or needed by design, desired level). To achieve this, use of a buffer before CTLE 210, as shown in FIG. 2, is desirable to isolate incoming signals from inputs of the CTLE 210 and set its DC level.

[0032] As shown in the schematic diagram for the wide band communications circuit 300, each node (Positive & Negative) has two signal paths from input 301 to output 302 for a signal to pass through. A high-speed path (i.e., high frequency) is shown in a solid line, while a low speed path (low frequency) is shown as a dashed line. The wide band communications circuit 300 can include a pair of emitter followers Q1 and Q2 representing the CTLE buffer 210. They are the major devices provided to buffer signal going into the input 301. CTLE buffer 205 can serve as a wide band buffer adapted to provide signal buffering and level shift functions by including a pair of emitter follower transistors Q1 and Q2 at CTLE inputs to buffer the input signals. A pair of bipolar transistors Q3 and Q4 can be used to shift the common mode voltage levels from the output of emitter follower Q1 and Q2 to the common mode voltage that the next stage needs. R1 and R2 along with R3 and R4 can be connected in the circuit as shown to further adjust the common mode voltage of output signals from the output 302. A common mode voltage of V.sub.out, V.sub.cm_outV.sub.cm.sub.inR.sub.1I.sub.E+R.sub.3I.sub.C, is achievable supposing V.sub.BE3=V.sub.BE1 and V.sub.BE4=V.sub.BE2 , if the emitter area ratio A.sub.1/A.sub.3 and A.sub.2/A.sub.4 is equal to the emitter current ratio I.sub.E/I.sub.C. The common mode voltage that the next state might need may often be to keep the DC or common mode level of the output close to the input, or it can be to maintain whatever input common mode level is selected by design/needed for the next stage in the wide band communications circuit (e.g., the desired level). Although circuit design requirements can dictate variations for what the desired level after the emitter followers should be, it will commonly be determined that the output be kept at or above the DC or input common mode level (e.g., the input) entering the wide band buffer.

[0033] A pair of LC tank circuits 306, 307 can be included in the circuit as shown and can be used to pass and boost the high frequency signals to the next stage. LC tanks are ideally selected to be large enough to pass the signal at as low a frequency as possible while also blocking the DC voltage. The positive and negative low frequency signals blocked by the LC tanks, including the DC signal, can be passed through paths Q1-R1-R3-Q3 and Q2-R2-R4-Q4, respectively. A corner frequency between the high frequency path and the low frequency path would ideally match each other and can be adjusted carefully to have a flattest frequency response. LC tanks can also be chosen to extend the signal bandwidth, while minimizing the peaking gain so as not to impact the frequency response of the whole channel.

[0034] Referring to FIG. 4, a graph 400 is provided that depicts the AC responses of a low speed signal, a high-speed signal and a signal impacted by a complete buffer. Also depicted are high speed and low speed signal gain, and the buffered signal gain, which is the total of high speed and low speed gain. As can be seen in the graph 400, a wideband buffer response can be achieved by adding the high speed and low speed signal paths.

[0035] FIG. 5 depicts an alternate embodiment of a bias circuit 500 for a wide band buffer as part of a wide band communication system, which is configured to maintain A1/A3=A2/A4=I.sub.E/I.sub.C. There are many ways to pick the size of the bipolar and MOS transistors. One example can be to pick M1=M2=M3 and

[00001]$Q_6=\frac{A_3}{A_1}{Q}_{1.Math.b}=\frac{A_4}{A_2}{Q}_{2.Math.b}$

to maintain V.sub.BE3=V.sub.BE1 and V.sub.BE4=V.sub.BE2. Q.sub.0 is the input transistor of the current mirror. Q5, Q7, M4 and M5 can compose a base current compensation circuit to compensate the base current of the current mirror to minimize the current mismatch. Degeneration resistors can be chosen with the right ratio of the emitter area of bipolar transistor, that is

[00002]$\frac{1}{R_0}.Math.\text{:}.Math.\frac{1}{R_5}.Math.\text{:}.Math.\frac{1}{R_6}.Math.\text{:}.Math.\frac{1}{R_{1.Math..Math.b}}.Math.\text{:}.Math.\frac{1}{R_{2.Math.b}}=Q_0.Math.\text{:}.Math.Q_5.Math.\text{:}.Math.Q_6.Math.\text{:}.Math.Q_{1.Math.b}.Math.\text{:}.Math.Q_{2.Math.b}.$

[0036] Accordingly, the embodiments described herein can provide a voltage buffer for wide band high frequency signals, can separate high frequency and low frequency component paths, can boost high frequency gain by series inductor peaking, can pass a low frequency component without amplification or attenuation, can keep output common mode voltage at or near the same level as the input, can control output common mode voltage in an accurate manner, and works in voltage (e.g., 1.8V low) power supplies.

[0037] Although the operations of the method(s) herein are shown and described in a particular order, the order of the operations of each method may be altered so that certain operations may be performed in an inverse order or so that certain operations may be performed, at least in part, concurrently with other operations. In another embodiment, instructions or sub-operations of distinct operations may be implemented in an intermittent and/or alternating manner.

[0038] It can also be noted that at least some of the operations for the methods described herein may be implemented using software instructions stored on a computer useable storage medium for execution by a computer. As an example, an embodiment of a computer program product includes a computer useable storage medium to store a computer readable program.

[0039] The computer-useable or computer-readable storage medium can be an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system (or apparatus or device). Examples of non-transitory computer-useable and computer-readable storage media include a semiconductor or solid-state memory, magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disk, and an optical disk. Current examples of optical disks include a compact disk with read only memory (CD-ROM), a compact disk with read/write (CD-R/W), and a digital video disk (DVD).

[0040] Alternatively, embodiments of the invention may be implemented entirely in hardware or in an implementation containing both hardware and software elements. In embodiments that use software, the software may include but is not limited to firmware, resident software, microcode, etc.

[0041] Although specific embodiments of the invention have been described and illustrated, the invention is not to be limited to the specific forms or arrangements of parts so described and illustrated. The scope of the invention is to be defined by the claims appended hereto and their equivalents.