High efficiency current source/sink DAC

Abstract

A current source and/or current sink digital-to-analog converter (DAC) includes a DAC circuit that converts a digital code to an analog current or voltage signal, an optional transconductance circuit that converts a voltage output of the DAC circuit into a current signal, and an output circuit that amplifies a current output of the DAC circuit or optionally amplifies a current output of the transconductance circuit to set a desired high current output for application to an output of the current source and/or current sink DAC. A power supply control current may be coupled to a power supply circuit that supplies power to the output circuit of the current source and/or current sink DAC. The power supply control current adjusts the output of the power supply circuit to cause the current source and/or current sink DAC to operate at a higher power efficiency.

Claims

1. A circuit to adjust an output circuit power supply voltage to reduce power dissipation in a current source or a current sink digital-to-analog converter by tracking changes in the output voltage and a minimum dropout voltage requirement, the circuit comprising: at least one of a current source or a current sink digital-to-analog converter comprising a digital-to-analog converter circuit that converts a digital code to an analog current output; an output circuit that amplifies the analog current output of the digital-to-analog converter circuit to set a desired high current output for application to an output of the at least one current source or current sink digital-to-analog converter; and a power supply circuit that supplies power to the output circuit and a power supply control current to the at least one current source or current sink digital-to-analog converter to adjust an output of the power supply circuit in response to a variation in at least one of an output of the output circuit or a minimum dropout voltage requirement of the output circuit.

2. The circuit of claim 1, wherein the digital-to-analog converter circuit includes a digital-to-analog converter that provides an analog voltage output and a transconductance circuit, the transconductance circuit to convert the analog voltage output to the analog current output of the digital-to-analog converter circuit.

3. The circuit of claim 1, comprising: a control pin on the current source or current sink digital-to-analog converter that is connected to the power supply control current and is adapted for coupling to the power supply circuit, the power supply control current to adjust the output of the power supply circuit in response to a change in an output voltage of the at least one current source or current sink digital-to-analog converter.

4. The circuit of claim 1, the power supply control current to adjust the output of the power supply circuit in response to a change in a minimum dropout voltage requirement of the output circuit of the at least one current source or current sink digital-to-analog converter.

5. The circuit of claim 1, the power supply control current to adjust the output of the power supply circuit in response to a programmable power supply voltage such that the output of the power supply circuit is always higher than or equal to the programmed voltage.

6. The circuit of claim 1, the power supply control current to adjust the output of the power supply circuit in response to a minimum or maximum power supply voltage requirement of the output circuit of the at least one current source or current sink digital-to-analog converter.

7. The circuit of claim 1, comprising: a current control signal circuit to generate the power supply control current, the current control signal circuit comprising a smaller scale replica of the output circuit of the at least one current source or current sink digital-to-analog converter that determines the minimum dropout voltage requirement of the output circuit.

8. The circuit of claim 7, wherein the smaller scale replica of the output circuit is biased using a current generator that is programmed using the digital code of the current source or current sink digital-to-analog converter such that the smaller scale replica of the output circuit operates at a substantially same current density as the output circuit of the at least one current source or current sink digital-to-analog converter.

9. The circuit of claim 1, wherein the power supply circuit includes: a DC-DC voltage converter; a voltage setting resistor network; and a feedback pin to set an output voltage of the DC-DC voltage converter, wherein the voltage setting resistor network includes: a feedback resistor with a first terminal coupled to the output voltage of the DC-DC voltage converter and a second terminal coupled to the feedback pin, the voltage setting resistor network further comprising a termination resistor with a first terminal coupled to the feedback pin and a second terminal coupled to a substantially constant reference voltage, wherein the DC-DC voltage converter supplies power to the output circuit of a current source digital-to-analog converter, and wherein the current source digital-to-analog converter includes a control pin that is coupled to the feedback pin, the power supply control current being sunk through the control pin, and the current source digital-to-analog converter adjusting the output voltage of the DC-DC voltage converter by adjusting the power supply control current.

10. The circuit of claim 9, wherein resistance values of the feedback resistor and the termination resistor of the voltage setting resistor network of the DC-DC voltage converter are chosen such that a sum of (1) a feedback voltage of the DC-DC voltage converter and (2) a ratio of a resistance of the feedback resistor and a resistance of the termination resistor multiplied by the feedback voltage of the DC-DC voltage converter is equal to a minimum required supply voltage.

11. The circuit of claim 9, the current source digital-to-analog converter to adjust an output of the power supply circuit in response to a variation in at least one of an output of the output circuit or a minimum dropout voltage requirement of the output circuit by utilizing a power supply control loop that accepts: at a first input the output voltage of the current source digital-to-analog converter (VOUTX), at a second input a minimum required supply voltage, and at a third input a minimum dropout voltage requirement of the output circuit of the current source digital-to-analog converter (V.sub.DROPOUT(MIN)), the power supply control loop to output the power supply control current, the power supply control current having a value of zero when VOUTX is less than a difference between VDDX(MIN) and V.sub.DROPOUT(MIN) and otherwise having a value that is a function of a resistance of the feedback resistor of the voltage setting resistor network of the DC-DC converter and a difference between VOUTX and the difference between VDDX(MIN) and V.sub.DROPOUT(MIN).

12. The circuit of claim 11, comprising: the current source digital-to-analog converter comprising a plurality of output channels, two or more of the output channels sharing a power supply circuit that supplies power to the output circuit of the two or more current source digital-to-analog converter output channels, the current source digital-to-analog converter further comprising: an analog voltage comparator that determines a current source digital-to-analog converter output channel with a higher output voltage at any given time amongst the two or more of the current source digital-to-analog converter output channels sharing the power supply circuit and selects the determined output channel voltage to be processed by the power supply control loop to generate the power supply control current that is used to adjust the output voltage of the power supply circuit.

13. The circuit of claim 1, wherein the at least one of a current source or a current sink digital-to-analog converter includes a plurality of current source or a current sink digital-to-analog converters coupled to the power supply circuit in a daisy-chain configuration, and wherein only one of the plurality of current source or a current sink digital-to-analog converters is coupled to a feedback node of the power supply circuit and wherein the current source or current sink digital-to-analog converter with the highest power supply voltage requirement controls the output voltage of the power supply circuit.

14. The circuit of claim 1, comprising: a low dropout (LDO) voltage regulator between the power supply circuit and the at least one current source or current sink digital-to-analog converter, the LDO voltage regulator to filter the noise of the power supply circuit.

15. A method for adjusting an output circuit power supply voltage to reduce power dissipation in at least one of a current source or a current sink digital-to-analog converter by tracking changes in the output voltage and a minimum dropout voltage requirement, wherein the at least one of a current source or a current sink digital-to-analog converter includes a digital-to-analog converter circuit that converts a digital code to an analog current output, the method comprising: amplifying the analog current output of the digital-to-analog converter circuit to set a desired high current output for application to an output of the at least one current source or current sink digital-to-analog converter; and supplying power to an output circuit and a power supply control current to the at least one current source or current sink digital-to-analog converter to adjust an output of a power supply circuit in response to a variation in at least one of an output of the output circuit or the minimum dropout voltage requirement of the output circuit.

16. The method of claim 15, comprising: connecting a control pin on the current source or current sink digital-to-analog converter to the power supply control current, adjusting, using the power supply control current, the output of the power supply circuit in response to a change in an output voltage of the at least one current source or current sink digital-to-analog converter.

17. The method of claim 15, comprising: adjusting the output of the power supply circuit in response to a change in a minimum dropout voltage requirement of the output circuit of the at least one current source or current sink digital-to-analog converter.

18. The method of claim 15, comprising: adjusting the output of the power supply circuit in response to a minimum or maximum power supply voltage requirement of the output circuit of the at least one current source or current sink digital-to-analog converter.

19. A circuit for biasing a semiconductor optical amplifier (SOA), the circuit comprising: an optical component biased at a programmable current, the programmable current supplied by an output of at least one of a current source or current sink digital-to-analog converter, wherein the at least one current source or current sink digital-to-analog converter includes: an output circuit; and a power supply control current that is coupled to a power supply circuit that supplies power to the output circuit of the at least one current source or current sink digital-to-analog converter, the power supply control current adjusting an output of the power supply circuit in response to a variation in at least one of an output of the output circuit or a minimum dropout voltage requirement of the output circuit.

20. The circuit of claim 19, comprising: a control pin on the current source or current sink digital-to-analog converter that is connected to the power supply control current and is adapted for coupling to the power supply circuit, the power supply control current to adjust the output of the power supply circuit in response to a change in an output voltage of the current source or current sink digital-to-analog converter.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) In the drawings, which are not necessarily drawn to scale, like numerals may describe similar components in different views. Like numerals having different letter suffixes may represent different instances of similar components. The drawings illustrate generally, by way of example, but not by way of limitation, various examples discussed in the present document.

(2) FIG. 1 illustrates a programmable current source digital-to-analog converter (DAC) that converts a precision DAC voltage into a high output current

(3) FIG. 2 illustrates an application of a programmable current source DAC for semiconductor optical amplifier (SOA) biasing.

(4) FIG. 3 illustrates a high efficiency current source DAC.

(5) FIG. 4 illustrates a circuit for implementation of the power supply control current I.sub.CTRL for a current source DAC.

(6) FIG. 5 illustrates a circuit for implementation of the power supply control current I.sub.CTRL when multiple DAC channels are connected to a single supply.

(7) FIG. 6 illustrates a DC-DC voltage converter followed by a low dropout voltage regulator and a current source DAC that dynamically adjusts both the DC-DC voltage converter and the low dropout voltage regulator for higher power efficiency.

(8) FIG. 7 illustrates a high efficiency current sink DAC.

(9) FIG. 8 illustrates a circuit for implementing the power supply control current I.sub.CTRL for a current sink DAC.

(10) FIG. 9 illustrates another circuit for implementation of the power supply control current I.sub.CTRL for a current source DAC.

(11) FIG. 10 is a block diagram illustrating a daisy chain connection of three current source DACs powered from the same power supply.

(12) FIG. 11 illustrates a circuit for implementation of the power supply control current I.sub.CTRL for multiple current source DACs powered from the same power supply.

DETAILED DESCRIPTION

(13) This document describes a circuit and a method for dynamically adjusting the power supply voltage of the output circuit of a current source/sink DAC, such that the current source/sink DAC operates at a higher power efficiency compared to the case when no such dynamic adjustments are made. The power supply voltage of the output circuit may be continuously adjusted in response to the changes in the output voltage of the current source/sink DAC and also in response to changes in the minimum dropout voltage requirements of the output circuit which may be due to changes in the programmed output current, manufacturing process variations, changes in voltage levels, temperature, and changes over time such as component aging. While the implementation focuses on a DAC, the techniques described may be extended to any circuit with a similar output circuit that outputs a programmable load current.

(14) Programmable Current Source DAC

(15) FIG. 1 illustrates a programmable current source digital-to-analog converter (DAC) that converts a precision DAC voltage into a high output current that can be sourced (current out of the chip) to an external load. Programmable current source DACs of the type illustrated in FIG. 1 can be used in optical communications for optical component biasing, particularly for applications that require high output currents, such as of 300 mA or greater. Optical communication applications may require very accurate current biasing, for example, to bias a semiconductor optical amplifier (SOA) to achieve a specific optical gain or to adjust the output power of a laser diode of a laser pump used with an Erbium-Doped Fiber Amplifier (EDFA).

(16) The optical component may also include a variable optical attenuator (VOA) that is adjusted by current biasing. As illustrated in FIG. 1, a separate precision DAC core (VDD.sub.DAC) and output circuit supplies (V.sub.DDX) can also be provided such as for higher power efficiency.

(17) In FIG. 1, the programmable current source/sink DAC 100 can receive digital data (CODE) at a precision DAC 102 that may be powered by a low power voltage source (VDD.sub.DAC). This digital data (CODE) allows the current source DAC 100 to be programmable by changing the output voltage of the precision DAC 102 in response to changes in digital data (CODE). An output of the precision DAC 102 can be applied to a transconductance circuit such as of the type described in commonly owned U.S. Pat. No. 9,203,350 such as can include an N channel FET 110 in series connection with a variable resistor 120. The transconductance circuit converts the output voltage of the precision DAC 102 to a current. In FIG. 1, the drain 112 of the FET 110 can be connected to the transconductance circuit output node 114, while the source 116 of the FET 110 can be connected to a first terminal of the variable resistor 120 at a resistor node 118. A second terminal of the variable resistor 120 can be connected to a reference voltage node such as ground (GND). A gate 122 of the FET 110 can function as a control terminal for the transconductance circuit. A differential amplifier 124 can be configured such that its input signal is the output of the precision DAC 102, which can be provided to a non-inverting input 126 of the differential amplifier 124. A voltage at resistor node 118, which effectively represents the voltage across the variable resistor 120, can be connected to an inverting input 128 of the differential amplifier 124. An output 130 of the differential amplifier 124 can be provided to the gate 122 of the N channel FET 110. In this configuration, the differential amplifier 124 can form part of a negative feedback loop to linearize the operation of the transconductance circuit such as by desensitizing the overall response of the transconductance circuit to non-linearities in the response of the FET 110 by a combination of high amplifier gain and negative feedback. The transconductance of the transconductance circuit may be controlled by using a digital control signal (SPAN) such as to change the impedance between the resistor node 118 and the reference voltage node (GND). It should be noted that the transconductance circuit is an optional circuit for the current source DAC 100 and is only used when the output of the precision DAC 102 is an analog voltage signal. The transconductance circuit is not used for current source DAC 100 operation when the output of the precision DAC 102 is an analog current signal.

(18) To amplify the output current of the transconductance circuit or in the absence of the transconductance circuit to amplify the output current of the precision DAC 102 to generate a high output current for the programmable current source DAC 100 of FIG. 1, the output circuit can further include a pair of variable resistors 132 and 134, a differential amplifier 140, and a P-channel output FET 148.

(19) The variable resistor 132 can be provided between the transconductance circuit output node 114 and the output circuit power supply pin V.sub.DDX, while the variable resistor 134 can be provided between the output circuit power supply pin V.sub.DDX and node 136. As illustrated, the output circuit further includes a differential amplifier 140, and the transconductance circuit output node 114 may be connected to a non-inverting input 138 of the differential amplifier 140, while the node 136 may be connected to an inverting input 142 of the differential amplifier 140. The differential amplifier 140 provides an output 144 to a gate 146 of a P channel output FET 148 having a source 150 connected to the node 136 and a drain 152 connected to the output of the programmable current source DAC 100 (OUTX) to provide a high current output to a load. For example, OUTX may provide high amplitude bias currents (e.g., >300 mA) for a semiconductor optical amplifier. To change the current gain of the output circuit, the values of the variable resistors 132 and 134 may be controlled using a digital control signal (SPAN) that changes the respective resistances between the output circuit power supply V.sub.DDX and the respective nodes 114 and 136 at the respective inputs of the differential amplifier 140. In this configuration, the differential amplifier 140 forces equal voltage drop across resistors 132 and 134. By controlling the resistance of resistor 134 to be much less than resistor 132, high current gain from the output of the transconductance circuit to the current source DAC 100 output can be achieved, since that gain is equal to the resistance ratios of resistor 132 and resistor 134.

(20) FIG. 2 illustrates an application of a programmable current source DAC 100 such as of the type illustrated in FIG. 1 for semiconductor optical amplifier (SOA) biasing. SOAs can amplify light without converting the light to electricity. This process requires very accurate biasing for optimum performance (e.g., up to 16-Bits DAC resolution). Also, since the SOAs are typically placed in physically tiny optical modules, reducing power dissipation can be very important. In an example, the output circuit power supply V.sub.DDX can be set to V.sub.OUTX+V.sub.DROPOUT(MIN) to reduce power, where V.sub.OUTX is the voltage at the drain 152 of the current source DAC 100, and V.sub.DROPOUT(MIN) is the minimum dropout voltage required to keep the current source DAC 100 in compliance and functional. The dropout voltage is the voltage drop across the output circuit and is equal to V.sub.DDX−V.sub.OUTX. In the example of FIG. 2, V.sub.OUTX may be equal to V.sub.SOA, which is the forward voltage of the SOA 200. The V.sub.DROPOUT(MIN) requirement stems from the fact that both the resistor 134 and the P channel output FET 148 have finite DC resistance. Since the high output current of the current source DAC 100 flows through the resistor 134 and the P channel output FET 148, it causes a voltage drop across those devices due to ohm's law, which is equal to I.sub.OUT′(R.sub.DC(R 134)+R.sub.DCMIN(PFET 148)), where I.sub.OUT is the high output current of the current source DAC 100, R.sub.DC(R 134) is the DC resistance of the resistor 134, and R.sub.DCMIN(PFET 148) is the minimum DC resistance of the P channel output FET 148. Hence the dropout voltage, V.sub.DDX−V.sub.OUTX, should be greater than or equal to a minimum dropout voltage requirement of V.sub.DROPOUT(MIN), for the current source DAC 100 to be functional.

(21) In the example shown in FIG. 2, typical values of 2V for V.sub.SOA and 0.5V for V.sub.DROPOUT(MIN) are used. Accordingly, the V.sub.DDX power supply voltage may be set to V.sub.SOA+V.sub.DROPOUT(MIN)=2.5V, and the SOA is biased at 300 mA forward current. It is important to note that the power dissipation of the output circuit is equal to dropout voltage*I.sub.OUT or equivalently 0.5V.Math.0.3 A=0.15 W. Meanwhile, the power supply for the precision DAC 102 (VDD.sub.DAC) may be set to 5 V and is only supplying 1 mA of current. So, the power dissipation of the precision DAC 102 is only 5V.Math.0.001 A=0.005 W. The power efficiency for a current source DAC can be defined as,

(22) $\eta =100\times \left(1-\frac{P_{\mathrm{DAC}}}{P_{\mathrm{Total}}}\right),$
where P.sub.DAC is the power dissipation of the current source/sink DAC and P.sub.Total is the total power drawn from the power supplies and is equal to V.sub.DDX*I.sub.OUT+VDD.sub.DAC*I.sub.DAC, where I.sub.DAC is the supply current of the precision DAC 102. For the example in FIG. 2,

(23) $\eta \cong 100\times \left(1-\frac{0.15W+0.005W}{0.75W+0.005W}\right)\cong 79.5\%.$
As mentioned before, in general most of the total power may be dissipated in the output circuit. This also highlights the benefit of having separate supply pins for the precision DAC 102 and the output circuit. By having a separate output circuit power supply pin, V.sub.DDX can be set lower than VDD.sub.DAC and power dissipation can be reduced. However, it should be noted that the V.sub.DDX cannot be set arbitrarily low. The differential amplifier 140 used in the output circuit also uses V.sub.DDX as its power supply for good power supply rejection performance and for turning on and off the P channel output FET 148 without over-voltaging its gate oxide. The differential amplifiers like the one used in the output circuit require their supply voltage to be higher than a certain voltage to function properly. The differential amplifier 140 is integral to the proper functioning of the current source DAC 100. Therefore, the output circuit power supply V.sub.DDX has to be greater than a minimum voltage V.sub.DDX(MIN), for the current source to be functional.

(24) Another reason why V.sub.DDX cannot be lowered arbitrarily is the dropout voltage requirement. It can be observed for the example of FIG. 2 that the dropout voltage, V.sub.DDX−V.sub.OUTX, may be equal to the V.sub.DROPOUT(MIN) value, 2.5V−2.0V=0.5V. This is the best case scenario for power dissipation because, if V.sub.DDX was set to be lower to save power, the dropout voltage, V.sub.DDX-V.sub.OUTX, would be less than the minimum dropout voltage requirement V.sub.DROPOUT(MIN), hence the current source DAC 100 would not be functional. This example can be optimized for lower power dissipation and higher power efficiency. Combining the minimum V.sub.DDX voltage requirement and the minimum dropout voltage requirement, the power dissipation for the current source DAC 100 may be lowered significantly by having V.sub.DDX be substantially equal to the greater of V.sub.DDX(MIN) voltage and V.sub.OUTX+V.sub.DROPOUT(MIN) voltage or equivalently max {V.sub.DDX(MIN), V.sub.OUTX+V.sub.DROPOUT(MIN)}.

(25) When the example of FIG. 2 is analyzed in the presence of process, voltage, or temperature variations, problems can be observed regarding the functionality of the current source DAC 100. As an example, if the SOA 200 forward voltage were to shift 0.1V higher due to temperature, the dropout voltage would equal 2.5V−2.1V=0.4V, which is lower than the minimum dropout voltage requirement V.sub.DROPOUT(MIN), which would result in current source DAC 100 failing to provide the 300 mA bias current for the SOA 200. One solution to this problem may be to set the V.sub.DDX voltage for the worst case values of V.sub.OUTX and V.sub.DROPOUT(MIN) over process variations, voltage levels, temperature and time. For example, a worst case SOA voltage of 2.2V can be used instead of the typical value of 2V and 0.7V worst case V.sub.DROPOUT(MIN) voltage can be used instead of the typical 0.5V. In this scenario, V.sub.DDX would be set to 2.2V+0.7V=2.9V. V.sub.DDX=2.9V would guarantee under worst case conditions that the current source DAC 100 would be functional. However, the power dissipation for typical cases would increase significantly. For example, when V.sub.DDX may be set to 2.9V and the SOA voltage is at its typical value of 2.0V, the dropout voltage will be 2.9V−2.0V=0.9V and the output circuit power dissipation would be 0.9V.Math.0.3 A=0.27 W, for the 300 mA bias case. This is much higher than the earlier calculated typical power dissipation of 0.5V−0.3 A=0.15 W. The power efficiency would also be lower since

(26) $\eta \cong 100\times \left(1-\frac{0.27W+0.005W}{0.87W+0.005W}\right)\cong 68.6\%.$
Given this shortcoming of the example of FIG. 2, it is desirable to implement circuits and methods that can dynamically adjust the output circuit power supply V.sub.DDX for higher power efficiency operation in the presence of V.sub.OUTX and V.sub.DROPOUT(MIN) changes due to process, programmed DAC current, voltage, temperature and aging related variations.

(27) FIG. 3 illustrates an example of a high efficiency current source DAC 300. In FIG. 3, a high efficiency DC-DC voltage converter 305 including a buck converter chip 310 can be used to step down the VDD.sub.DAC voltage to the V.sub.DDX voltage for the circuits of FIG. 1 and FIG. 2. As in the example of FIG. 2, it can be assumed that VDD.sub.DAC is approximately 5 V while V.sub.DDX can be approximately 2.5 V. Generally, there exists a voltage setting resistor network to set the output voltage of DC-DC voltage converters. In FIG. 3, this voltage setting resistor network may be formed by feedback resistor R2 (332) and termination resistor R1 (334). Resistor R2 (332) may be connected from the output node V.sub.DDX of the DC-DC voltage converter 305 to the V.sub.FB pin 330 of the buck converter chip 310 and R1 (334) may be connected from the V.sub.FB pin 330 of the buck converter chip 310 to GND. In this configuration, V.sub.DDX may be calculated as: (1+R2/R1).Math.V.sub.FB where V.sub.FB is a buck converter chip 310 specific feedback voltage and is usually between 1.25V and 0.6V.

(28) As noted above, setting the DC-DC voltage converter 305 output for worst case values of V.sub.DROPOUT(MIN) and V.sub.OUTX may be disadvantageous, especially for power dissipation, since both V.sub.DROPOUT(MIN) and V.sub.OUTX can vary significantly, for example, as programmed DAC code, manufacturing process parameters, voltage levels, or temperature change. When V.sub.DDX is set using the voltage setting resistor network formed by R2 and R1, it may be a constant voltage that may be set for a worst case and cannot be dynamically adjusted. As mentioned before, it is desirable to further reduce the power dissipation by dynamically adjusting the V.sub.DDX voltage in response to changes in the values of V.sub.OUTX and V.sub.DROPOUT(MIN). However, this cannot be achieved by the sole use of the voltage setting resistor network as this results in a constant voltage V.sub.DDX output.

(29) To address this issue, the current source DAC 300 of FIG. 3 can be modified to include a power supply control pin, PS_CTRL 320, that can be coupled to the feedback pin (V.sub.FB) 330 of the buck converter chip 310 and the voltage setting resistor network of the DC-DC voltage converter 305. The DC-DC voltage converter 305 of FIG. 3 is shown to include a buck converter chip 310. For current source DACs, a buck/boost converter chip can also be used. For current sink DACs, an inverting converter chip or a SEPIC converter chip can be used.

(30) For the current source DAC 300 illustrated in FIG. 3, PS_CTRL may be a current sink output that adjusts V.sub.DDX such that

(31) $\mathrm{VDDX}=\left(1+\frac{R2}{R1}\right).Math.V_{\mathrm{FB}}+\mathrm{ICTRL}.Math.R2,$
where I.sub.CTRL 340 is the current flowing through the PS_CTRL pin 320 of the current source DAC 300. As mentioned before, there exists a minimum output circuit power supply voltage V.sub.DDX(MIN) for the current source DAC 300 to function properly. If the values of resistors R2 and R1 are chosen such that,

(32) $\left(1+\frac{R2}{R1}\right).Math.V_{\mathrm{FB}}=\mathrm{VDDX}\left(\mathrm{MIN}\right)$
so that V.sub.DDX=V.sub.DDX(MIN)+I.sub.CTRL.Math.R2, then the current source DAC 300 can dynamically adjust the V.sub.DDX voltage by adjusting the I.sub.CTRL current 340 for lower power dissipation and higher power efficiency as V.sub.OUTX and V.sub.DROPOUT(MIN) voltages vary due to elements such as process variation, voltage levels, temperature, and time. It is important to note that this method of adjusting the V.sub.DDX power supply voltage can work with commercially available DC-DC voltage converters and does not require any changes or customizations to the DC-DC voltage converter chips such as the buck converter chip 310 used in FIG. 3.

(33) As mentioned before, the V.sub.DDX voltage should equal max{V.sub.DDX(MIN), V.sub.OUTX+V.sub.DROPOUT(MIN)} for higher power efficiency operation. If V.sub.DDX is set to V.sub.DDX(MIN) for higher power efficiency, then the current source DAC 300 should adjust the I.sub.CTRL current 340 to be equal to zero amps. Similarly, if V.sub.DDX should equal V.sub.OUTX+V.sub.DROPOUT(MIN), the current source DAC 300 should increase I.sub.CTRL current 340 until V.sub.DDX equals V.sub.OUTX+V.sub.DROPOUT(MIN). This can be achieved by establishing a High Efficiency Power Supply Control Loop (HEPSCL), that takes as input V.sub.DDX(MIN), V.sub.OUTX, V.sub.DROPOUT(MIN) and outputs I.sub.CTRL current 340 to be used for dynamically adjusting the output circuit power supply V.sub.DDX for higher power efficiency operation compared to the case when V.sub.DDX is set as a constant voltage.

(34) If I.sub.CTRL current 340 is set according to the equations defined below, then the HEPSCL can guarantee proper current source DAC operation and higher power efficiency even under varying V.sub.OUTX and V.sub.DROPOUT(MIN) voltages due to process variation, voltage levels, temperature and time:

(35) $\mathrm{ICTRL}=\begin{array}{cc}0,& \begin{array}{c}\mathrm{for}\mathrm{VOUTX}<\mathrm{VDDX}\left(\mathrm{MIN}\right)-\\ V_{\mathrm{DROPOUT}}\left(\mathrm{MIN}\right)\end{array}\\ \frac{\begin{array}{c}\mathrm{VOUTX}-\\ \left[\mathrm{VDDX}\left(\mathrm{MIN}\right)-V_{\mathrm{DROPOUT}}\left(\mathrm{MIN}\right)\right]\end{array}}{R2},& \begin{array}{c}\mathrm{for}\mathrm{VOUTX}\ge \mathrm{VDDX}\left(\mathrm{MIN}\right)-\\ V_{\mathrm{DROPOUT}}\left(\mathrm{MIN}\right)\end{array}\end{array}$$\mathrm{then},\mathrm{VDDX}=\begin{array}{cc}\mathrm{VDDX}\left(\mathrm{MIN}\right),& \begin{array}{c}\mathrm{for}\mathrm{VOUTX}<\mathrm{VDDX}\left(\mathrm{MIN}\right)-\\ V_{\mathrm{DROPOUT}}\left(\mathrm{MIN}\right)\end{array}\\ \mathrm{VOUTX}+V_{\mathrm{DROPOUT}}\left(\mathrm{MIN}\right),& \begin{array}{c}\mathrm{for}\mathrm{VOUTX}\ge \mathrm{VDDX}\left(\mathrm{MIN}\right)-\\ V_{\mathrm{DROPOUT}}\left(\mathrm{MIN}\right)\end{array}.\end{array}$

(36) V.sub.OUTX is the voltage at the output of current source DAC 300, V.sub.DDX(MIN) is the minimum output circuit supply voltage for proper current source DAC operation, V.sub.DROPOUT(MIN) is the minimum dropout voltage (V.sub.DDX−V.sub.OUTX) required for proper current source DAC operation, and R2 is the resistance of the feedback resistor R2 332 of the voltage setting resistor network of DC-DC voltage converter 305. An important advantage of implementing I.sub.CTRL per the equations above is the fact that the HEPSCL is only utilized when a dropout condition, V.sub.OUTX≥V.sub.DDX(MIN)−V.sub.DROPOUT(MIN), is detected. If a dropout condition is not detected, I.sub.CTRL equals zero amps and HEPSCL is effectively off. This allows the HEPSCL to be implemented as an auxiliary control loop, that is only used when needed, and relaxes the speed and stability requirements for the HEPSCL, since the HEPSCL is not required to be part of the main control loop for the DC-DC voltage converter 305.

(37) Referring back to the example of FIG. 2, the power efficiency improvements may be calculated for the case where HEPSCL is used to dynamically adjust the V.sub.DDX voltage compared to setting the V.sub.DDX voltage as a constant voltage for worst case parameters. For worst case values of V.sub.OUTX=2.2V and V.sub.DROPOUT(MIN)=0.7V, power efficiency was calculated to be η≅68.6% for the typical SOA voltage and V.sub.DROPOUT(MIN) case, when V.sub.DDX was set as constant voltage and no dynamic adjustments were made. When HEPSCL is used to dynamically adjust V.sub.DDX voltage, the efficiency will still be η≅79.5% for the typical SOA voltage and V.sub.DROPOUT(MIN) case, since HEPSCL tracks the SOA voltage and V.sub.DROPOUT(MIN) and would dynamically adjust V.sub.DDX=2.5V. For the case when both SOA voltage and V.sub.DROPOUT(MIN) shift to their respective worst case values of 2.2V and 0.7V for example due to temperature change, then the HEPSCL would dynamically adjust V.sub.DDX=2.9V and the corresponding efficiency would be

(38) $\eta \cong 100\times \left(1-\frac{0.21W+0.005W}{0.87W+0.005}\right)\cong 75.4\%$
which is higher than the efficiency of 68.6% achieved when V.sub.DDX voltage is set as a constant voltage and HEPSCL is not used. Utilizing a HEPSCL not only offers higher efficiency for typical conditions, but also results in higher efficiency when V.sub.OUTX and V.sub.DROPOUT(MIN) vary to their worst case values due to possible changes in programmed DAC code, temperature, voltage levels or time.

(39) Such a circuit, to be used in a HEPSCL that takes as input V.sub.DDX(MIN), V.sub.OUTX and V.sub.DROPOUT(MIN) and outputs I.sub.CTRL current 340, can be implemented in a circuit of the type illustrated in FIG. 4 for a current source DAC 300 of the type illustrated in FIG. 3. For example, V.sub.DDX(MIN) may be a constant voltage and may be generated using a circuit such as a bandgap voltage reference. On the other hand, V.sub.DROPOUT(MIN) may be a voltage that can vary with process variations, temperature, and time and may be dynamically tracked by the HEPSCL. This can be achieved using a smaller scale replica (e.g., 1/100.sup.th) of the current source DAC 300 output circuit, specifically using smaller scale replicas of the resistor 134 and the P channel output FET 148. By placing this smaller scale replica in close physical proximity of the actual output circuit, variations due to process, temperature, physical stress and time can be tracked.

(40) As illustrated in FIG. 4, resistor R.sub.REPLICA 408 can be used as a smaller scale replica of resistor 134 of the output circuit. Similarly the P channel FET M.sub.REPLICA 410 can be used as a smaller scale replica of the P channel output FET 148 of the output circuit. A replica of the V.sub.DDX(MIN) voltage (V.sub.DDX(MIN).sub.REPLICA), which can be generated from a bandgap voltage reference, can be applied to the non-inverting input 402 of differential amplifier 404. The output 412 of the differential amplifier 404 may be connected to the inverting input 406 to form a unity gain buffer. This unity gain buffer buffers the V.sub.DDX(MIN).sub.REPLICA voltage and allows it to drive the resistor R.sub.REPLICA 408 and the P channel FET M.sub.REPLICA 410, while also allowing the V.sub.DDX(MIN).sub.REPLICA voltage to remain constant. A first terminal of resistor R.sub.REPLICA 408 can be connected to the output 412 of the unity gain buffer 404 and a second terminal of resistor R.sub.REPLICA 408 can be connected to the source node of P channel FET M.sub.REPLICA 410. The drain node of the P channel FET M.sub.REPLICA 410 can be connected to a first terminal of current source I.sub.REPLICA 413 and the second terminal of the current source I.sub.REPLICA 413 can be connected to GROUND. This series connection of the resistor R.sub.REPLICA 408, P channel FET M.sub.REPLICA 410 and the current source I.sub.REPLICA 413 is a smaller scale replica (e.g., 1/100.sup.th) of the output circuit of the current source DAC 300, formed by resistor 134 and P channel output FET 148, biased at I.sub.REPLICA current which is a scaled down version of the high output current of the current source DAC 300. The gate node of P channel FET M.sub.REPLICA 410 may be connected to the most negative voltage in the circuit, in the case of FIG. 4 the GROUND node, since the minimum DC resistance of a P channel FET can be achieved when its gate is at the lowest voltage possible. In this configuration, the voltage drop across the resistor R.sub.REPLICA 408 and the P channel FET M.sub.REPLICA 410 or equivalently the voltage difference between output 412 and node 414, can be made substantially equal to the minimum dropout voltage requirement, V.sub.DROPOUT(MIN), of the output circuit of the current source DAC 300 and can dynamically track the changes in V.sub.DROPOUT(MIN) due to programmed DAC current, process variations, temperature, and time. This can be achieved when I.sub.REPLICA 413 is programmed using the same digital data (CODE) used to program the precision DAC 102. This method of programming results in I.sub.REPLICA 413 being a scaled down version of the high output current of the current source DAC 300, such that the resistor R.sub.REPLICA 408 and P channel FET M.sub.REPLICA 410 operate at the same current density as the resistor 134 and the P channel output FET 148 of the output circuit of the current source DAC 300. This method enables HEPSCL to track instantaneous changes in the minimum dropout voltage requirement of the current source DAC 300 in the presence of programmed DAC code changes, in addition to other changes such as process variation, voltage levels, temperature and time.

(41) In the circuit of FIG. 4, the voltage at output 412 can be substantially equal to V.sub.DDX(MIN) and the voltage difference between output 412 and node 414 can be substantially equal to V.sub.DROPOUT(MIN). By Kirchhoff's voltage law, this results in voltage at node 414 to be substantially equal to V.sub.DDX(MIN)−V.sub.DROPOUT(MIN). Based on the equations for I.sub.CTRL that yield higher power efficiency operation, the voltage at node 414 may be subtracted from the output voltage V.sub.OUTX in order to generate I.sub.CTRL. This can be achieved by using the buffered subtractor circuit formed by the differential amplifiers 426, 418, and 436 and the resistors 458, 460, 462 and 464. The amplifier 426 can be connected in a unity gain buffer configuration and buffers the output voltage V.sub.OUTX of the current source DAC 300. This results in node 428 being substantially equal to V.sub.OUTX. In a similar fashion, the amplifier 418 can be connected in a unity gain buffer configuration and buffers the node 414. The node 420 thus can be substantially equal to node 414 which can be equal to V.sub.DDX(MIN)−V.sub.DROPOUT(MIN). The amplifier 436 and the resistors 458, 460, 462 and 464 form an attenuating subtractor, such that the output of amplifier 436 at node 438 can be substantially equal to

(42) $\frac{\mathrm{VOUTX}-\left[\mathrm{VDDX}\left(\mathrm{MIN}\right)-\mathrm{VDROPOUT}\left(\mathrm{MIN}\right)\right]}{M}.$
The attenuating subtractor attenuates or divides the difference by M, which lowers the voltage swing on the node 438 by the same amount. M can be an integer greater than or equal to 5 to substantially attenuate the voltage swing on the node 438. This eases the design of the amplifier 436 since its output voltage swings much less using an attenuating subtractor.

(43) The output stage of the circuit in FIG. 4 can be a transconductance stage that converts the voltage at node 438 into the current I.sub.CTRL, utilizing the amplifier 442, N channel output FET 448 and resistor 400. I.sub.CTRL equals

(44) $\frac{\mathrm{VOUTX}-\left[\mathrm{VDDX}\left(\mathrm{MIN}\right)-\mathrm{VDROPOUT}\left(\mathrm{MIN}\right)\right]}{R2}$
for higher power efficiency operation. This can be achieved by setting the resistance of resistor 400 to be equal to R2/M, since I.sub.CTRL is equal to the ratio of the voltage at node 438 to the resistance value of resistor 400.

(45) The implementation of FIG. 4 takes as inputs V.sub.DDX(MIN), V.sub.OUTX and V.sub.DROPOUT(MIN) and generates I.sub.CTRL required for higher power efficiency operation. By coupling the PS_CTRL pin 320 that I.sub.CTRL flows through to the V.sub.FB pin and the voltage setting resistor network of a buck converter chip 310 that supplies the V.sub.DDX voltage, the HEPSCL can be implemented. It should be noted that the voltages V.sub.OUTX and V.sub.DROPOUT(MIN) can be dynamically changing due to programmed DAC current, process variation, temperature, voltage levels or time, and the circuit implementation shown in FIG. 4 would allow a HEPSCL to track the changes in V.sub.OUTX and V.sub.DROPOUT(MIN) and dynamically adjust I.sub.CTRL, such that the current source DAC operates at a higher power efficiency compared to when V.sub.DDX is set as a constant voltage and no dynamic adjustment is made. It also should be noted that the implementation shown in FIG. 4 is one possible implementation of the I.sub.CTRL current transfer function. It will be apparent to those skilled in the art that different implementations can be utilized including but not limited analog current domain additions and subtractions, etc.

(46) The approach implemented in FIG. 4 may be applied in the case where 2 or more current source DAC channels share one output circuit power supply pin V.sub.DDX.

(47) FIG. 5 illustrates an example including two current source DAC 300 channels on a single V.sub.DDX supply. In this case, an analog comparator 500 may determine the higher of the output voltages V.sub.OUTX(MAX), amongst the two current source DAC 300 output voltages V.sub.OUTX(0), V.sub.OUTX(1), etc. and can force the I.sub.CTRL to track the higher V.sub.OUTX voltage by switching in the corresponding differential amplifier 426, 510, etc. using switches 520, 530. In this case, V.sub.DDX may be equal to V.sub.OUTX(MAX)+V.sub.DROPOUT(MIN) where V.sub.OUTX(MAX) can be the output voltage of the current source DAC 300 channel with the higher voltage. Another option may be to assign one channel (for example the higher current channel of the current source DAC 300) to be the master and to use that channel to generate I.sub.CTRL.

(48) Certain applications can require that the power supply powering the current source DAC or the current sink DAC also power one or more additional circuits, including but not limited to, analog-to-digital converters, voltage references, and amplifiers. In some such applications, the minimum power supply voltage V.sub.DDX(MIN) of the current source DAC can be too low to operate these additional circuits. In accordance with this disclosure, a user-programmable minimum voltage V.sub.DDX(PROG) can be used instead of the minimum voltage V.sub.DDX(MIN), such as described below with respect to FIG. 9.

(49) FIG. 9 illustrates another circuit for implementation of the power supply control current I.sub.CTRL for a current source DAC. Some of the components in FIG. 9 are similar to those in FIG. 4 and, for purposes of conciseness, will not be described again. The circuit 900 in FIG. 9 can include a voltage digital-to-analog converter (VDAC) 902 that is being controlled by a user-provided digital control signal, e.g., digital word. The VDAC 902 can generate the minimum power supply voltage V.sub.DDX(PROG).

(50) Each additional circuit that is powered by the same power supply as the current source DAC (or current sink DAC) can have a minimum supply voltage requirement. By programming the minimum power supply voltage V.sub.DDX(PROG) to the highest of these minimum supply voltage requirements, the output voltage of the power supply can be made higher than V.sub.DDX(PROG) voltage at all times, which can guarantee that all the minimum supply voltage requirements for the additional circuits are met. This can allow dynamic adjustment of the current source DAC power supply in the presence of the additional circuits, such that the current source DAC operates at a higher power efficiency compared to the case when no dynamic adjustment is made. It should be noted that the addition of the VDAC 900 in FIG. 9 can be applied to other circuits in this disclosure, such as the circuit shown in FIG. 5.

(51) The approach implemented in FIG. 4 can be extended to implementations in which two or more current source DAC integrated circuits (ICs) are powered from the same power supply, such as shown in FIG. 10

(52) FIG. 10 is a block diagram illustrating a daisy chain connection of three current source DACs powered from the same power supply. As seen in FIG. 10, a power supply 1000 can supply power to current source DAC 1002, current source DAC 1004, and current source DAC 1006. Although three current source DACs are depicted, these techniques are applicable to two current source DACs coupled to the same power supply 1000 or more than three current source DACs coupled to the same power supply 1000.

(53) In the daisy chain configuration shown in FIG. 10, each current source DAC can include two additional pins, namely a power supply control output pin (“PS_CTRL_OUT”) and a power supply control input pin (“PS_CTRL_IN”). The pin PS_CTRL_OUT can act similar to the PS_CTRL pin of FIG. 4.

(54) In FIG. 10, there is only one current source DAC, namely DAC 1002, that has a PS_CTRL_OUT pin directly connected to the power supply feedback (“FB”) node. The other current source DACs 1004, 1006 couple to each other and are able to communicate their needs to the current source DAC 1002 that is coupled to the power supply feedback node of the power supply. Each current source DAC in the chain can generate its own I.sub.CTRL current, as shown as described above with respect to FIG. 4. However, before outputting the I.sub.CTRL current to the PS_CTRL_OUT pin, the current source DAC, such as the current source DAC 1002, can compare the internally generated I.sub.CTRL current to the I.sub.CTRL current that may be present at the PS_CTRL_IN pin.

(55) FIG. 11 illustrates a circuit for implementation of the power supply control current I.sub.CTRL for multiple current source DACs powered from the same power supply. Some of the components in FIG. 11 are similar to those in FIG. 5 and, for purposes of conciseness, will not be described again.

(56) FIG. 11 shows the two pins PS_CTRL_OUT and PS_CTRL_IN for the current source DAC 1002 of FIG. 10, the current ICTRL #1 internally generated by the current source DAC 1002 of FIG. 10, and the current ICTRL #2 present at the PS_CTRL_IN pin of DAC 1002 of FIG. 10 that is received from the PS_CTRL_OUT pin of current source DAC 1004 of FIG. 10. The current source DAC can control a selection of the switches 1102, 1104 which can control selection of the higher of the two currents ICTRL #1 and ICTRL #2 to be output at the PS_CTRL_OUT pin. This can guarantee that the current source DAC with the highest current ICTRL and consequently the highest power supply voltage requirement, will control the power supply, thereby ensuring proper operation for all the current source DAC in the chain, such as in FIG. 10.

(57) Post LDO for Ultra Low Noise Applications

(58) A post LDO (Low Dropout) voltage regulator connected between the DC-DC voltage converter 305 and the current source DAC 600 may be desirable for some low noise applications. A post LDO voltage regulator may be provided to help attenuate or filter out the ripple noise of the DC-DC voltage converter 305 for ultra-low noise current source DAC 600 operation. Both the DC-DC voltage converter 305 and the LDO voltage regulator can optionally be controlled in tandem, where the output of the DC-DC voltage converter 305 and the output of the LDO voltage regulator dynamically increase or decrease by the same amount, such that the current source DAC 600 and the LDO voltage regulator operate more efficiently compared to the case where both the output of the DC-DC voltage converter and LDO voltage regulator are set as constant voltages and no dynamic adjustments are made.

(59) FIG. 6 illustrates a switch mode DC-DC voltage converter 305 followed by a post LDO voltage regulator 605. In FIG. 6, the post LDO voltage regulator 605 can include a voltage setting resistor network formed by LDO feedback resistor R2_LDO 622 and LDO termination resistor R1_LDO 624. The LDO voltage regulator 605 output V.sub.DDX which is the power supply for the output circuit of current source DAC 600 can be set by the voltage setting resistor network of resistors R2_LDO 622 and R1_LDO 624 and can be nominally equal to (1+R2_LDO/R1_LDO).Math.V.sub.ADJ, where V.sub.ADJ is the regulator specific adjustment voltage at node 620. In an example, resistors R2_LDO 622 and R1_LDO 624 can be selected such that (1+R2_LDO/R1_LDO).Math.V.sub.ADJ=V.sub.DDX(MIN) similar to the resistors R2 332 and R1 334 of FIG. 3. Also, the feedback resistor R2 332 and termination resistor R1 334 of the DC-DC converter 305 can then be set such that (1+R2/R1).Math.V.sub.FB=V.sub.DDX(MIN)+V.sub.DROPOUTLDO(MIN), where V.sub.DROPOUTLDO(MIN) is the LDO regulator specific minimum dropout voltage requirement.

(60) In order to be able to adjust the LDO voltage regulator 605 output V.sub.DDX and the DC-DC voltage converter 305 output LDO_IN by the same amount using the two identical copies of I.sub.CTRL current, the LDO feedback resistor 622 resistance value needs to be equal to the feedback resistor 322 resistance value of the DC-DC voltage converter 305, such that R2_LDO=R2. When these conditions are met, both the LDO voltage regulator 605 output V.sub.DDX and DC-DC voltage converter 305 output voltage LDO_IN may be controlled in tandem using two identical copies of the I.sub.CTRL current flowing through two separate pins PS_CTRL 320 and LDO_CTRL 640. A single I.sub.CTRL circuit similar to the implementation of FIG. 4, with two output transconductance stages, can be used to generate the two currents 340 and 650, and these two currents 340 and 650 can be coupled to nodes 330 and 620 respectively to form the HEPSCL. This implementation can help ensure that both the post LDO voltage regulator 605 and the current source DAC 600 operate at a higher power efficiency compared to the case where both the output of the DC-DC voltage converter and LDO voltage regulator are set as constant voltages.

(61) Efficient Control of the DC-DC Voltage Converter for Current Sink DACs

(62) In another configuration, a current sink DAC with a PS_CTRL pin may connect to the feedback (FB) node of an inverting DC-DC voltage converter. For a current sink DAC. PS_CTRL may be a current source output that regulates V.sub.SSX such that

(63) 0$V_{\mathrm{SSX}}=-1.Math.\left(\frac{\mathrm{R2\_INV}}{R{1}^{\prime }\mathrm{\_INV}}\right).Math.V_{\mathrm{REF}}-\mathrm{ICTRL}.Math.R2\mathrm{\_INV},$
where R2_INV 765 is the inverting feedback resistor and the R1′_INV 770 is the inverting termination resistor of the voltage setting resistor network of inverting DC-DC voltage converter 710 and VREF is the reference voltage of the inverting DC-DC voltage converter 710 (voltage at REF pin). The user sets

(64) $-1.Math.\left(\frac{\mathrm{R2\_INV}}{R{1}^{\prime }\mathrm{\_INV}}\right).Math.V_{\mathrm{REF}}=\mathrm{VSSX}\left(\mathrm{MAX}\right)$
so that VSSX=VSSX(MAX)−ICTRL.Math.R2_INV. In this case, V.sub.SSX(MAX)≤0 and is the maximum value of the negative supply voltage for proper current sink DAC operation.

(65) FIG. 7 illustrates a current sink DAC 700 with a PS_CTRL pin 705 that can dynamically adjust the output voltage of an inverting DC-DC voltage converter 710, such that the current sink DAC 700 operates at a higher power efficiency compared to the case when the output of the inverting DC-DC voltage converter is set as a constant voltage and no dynamic adjustments are made. As illustrated in FIG. 7, the current sink DAC 700 can include a low power, precision current output DAC 720 and an output circuit including differential amplifier 725, N channel output FET 730, and variable resistors 735 and 740. The output circuit can have a dedicated power supply pin V.sub.SSX for the exclusive use of the output circuit. Similar to the current source DAC 100 case, the output circuit can be used to amplify the output current of the low power precision current output DAC 720 to a high output current that can be sunk (into the pin) through the OUTX pin. The variable resistors 735 and 740 can also be provided to change the gain of the output circuit similar to the current source DAC 100 of FIG. 2.

(66) In this example, the I.sub.CTRL current source 750 can be connected between VDD.sub.DAC and the PS-CTRL pin 705 and can dynamically adjust the V.sub.SSX voltage such that the current sink DAC 700 operates at a higher power efficiency compared to the case when V.sub.SSX is set as a constant voltage. In the example of FIG. 7, an inverting DC-DC voltage converter 710 may be used. However, other types of DC-DC voltage converters, such as SEPIC or buck/boost can also be used. As illustrated in FIG. 7, the PS_CTRL pin 705 can be coupled to the FB pin of the inverting DC-DC converter chip 760 at node 780 of the voltage setting resistor network of resistors R2_INV (765) and R1_INV (770) to form a HEPSCL that can dynamically adjust the V.sub.SSX voltage when V.sub.OUTX and V.sub.DROPOUT(MIN) vary due to programmed DAC code, process variation, temperature, voltage levels, and time.

(67) Similar to the current source DAC 100 case, the lower power dissipation and higher power efficiency may be achieved when V.sub.SSX is set to the lower of the two voltages V.sub.SSX(MAX) and V.sub.OUTX−V.sub.DROPOUT(MIN), or equivalently V.sub.SSX=min{V.sub.SSX(MAX), V.sub.OUTX−V.sub.DROPOUT(MIN)}, where V.sub.SSX(MAX) is the highest V.sub.SSX voltage that allows functional current sink DAC 700 operation and V.sub.DROPOUT(MIN) is the minimum dropout voltage requirement of the current sink DAC 700. Then, to achieve the higher power efficiency while guaranteeing proper current sink DAC 700 operation, I.sub.CTRL can be set as follows:

(68) $\mathrm{ICTRL}=\begin{array}{cc}0,& \begin{array}{c}\mathrm{for}\mathrm{VOUTX}>\mathrm{VSSX}\left(\mathrm{MAX}\right)+\\ V_{\mathrm{DROPOUT}}\left(\mathrm{MIN}\right)\end{array}\\ \frac{\begin{array}{c}\left[\mathrm{VSSX}\left(\mathrm{MAX}\right)+V_{\mathrm{DROPOUT}}\left(\mathrm{MIN}\right)\right]-\\ \mathrm{VOUTX}\end{array}}{R2\mathrm{\_INV}},& \begin{array}{c}\mathrm{for}\mathrm{VOUTX}\le \mathrm{VSSX}\left(\mathrm{MAX}\right)+\\ V_{\mathrm{DROPOUT}}\left(\mathrm{MIN}\right)\end{array}\end{array}$$\mathrm{then},\mathrm{VSSX}=\begin{array}{cc}\mathrm{VSSX}\left(\mathrm{MAX}\right),& \begin{array}{c}\mathrm{for}\mathrm{VOUTX}>\mathrm{VSSX}\left(\mathrm{MAX}\right)+\\ V_{\mathrm{DROPOUT}}\left(\mathrm{MIN}\right)\end{array}\\ \mathrm{VOUTX}-V_{\mathrm{DROPOUT}}\left(\mathrm{MIN}\right),& \begin{array}{c}\mathrm{for}\mathrm{VOUTX}\le \mathrm{VSSX}\left(\mathrm{MAX}\right)+\\ V_{\mathrm{DROPOUT}}\left(\mathrm{MIN}\right)\end{array}.\end{array}$

(69) I.sub.CTRL also may be implemented for a current sink DAC 700. For example, FIG. 8 illustrates a circuit for implementing the current control signal I.sub.CTRL for a current sink DAC 700, to be used in a HEPSCL that takes as input V.sub.SSX(MAX), V.sub.OUTX and V.sub.DROPOUT(MIN) and outputs I.sub.CTRL current. For example, V.sub.SSX(MAX) is a constant voltage and may be generated using a circuit such as a bandgap voltage reference. On the other hand, V.sub.DROPOUT(MIN) is a voltage that can vary with process variations, temperature and time and may be dynamically tracked by the HEPSCL. Similar to the current source DAC 100 case, this can be achieved by using a smaller scale (e.g., 1/100.sup.th) replica of the current sink DAC 700 output circuit, specifically using smaller scale replicas of the resistor 740 and the N channel output FET 730.

(70) As illustrated in FIG. 8, resistor R.sub.REPLICA 808 may be used as a smaller scale replica of resistor 740 of the output circuit. Similarly, the N channel FET M.sub.REPLICA 810 may be used as a smaller scale replica of the N channel output FET 730 of the output circuit. A replica of the −1.Math.V.sub.SSX(MAX) voltage may be applied to the non-inverting input 802 of differential amplifier 804. The differential amplifier 804 may be connected in a unity gain buffer configuration. This unity gain buffer 804 buffers the −1.Math.V.sub.SSX(MAX).sub.REPLICA voltage and allows it to drive the N channel FET M.sub.REPLICA 810 and the resistor R.sub.REPLICA 808, while also allowing the −1.Math.V.sub.SSX(MAX).sub.REPLICA voltage to remain substantially constant. The drain node of the N channel FET M.sub.REPLICA 810 may be connected to the output of the unity gain buffer formed by amplifier 804. The source node of the N channel FET M.sub.REPLICA 810 may be connected to a first terminal of resistor R.sub.REPLICA 808 and a second terminal of the resistor R.sub.REPLICA 808 may be connected to a first terminal of the current source I.sub.REPLICA 812. The second terminal of the current source I.sub.REPLICA 812 may be connected to GROUND. This series connection of the N channel FET M.sub.REPLICA 810, the resistor R.sub.REPLICA 808, and the current source I.sub.REPLICA 812 is a smaller scale replica (e.g., 1/100.sup.th) of the output circuit of the current sink DAC 700, formed by resistor 740 and the N channel output FET 730, biased by I.sub.REPLICA current which is a scaled down version of the high output current of the current sink DAC 700. The gate node of the N channel FET M.sub.REPLICA 810 may be connected to the most positive voltage in the circuit since the minimum DC resistance of an N channel FET may be achieved when its gate is at the highest voltage possible.

(71) In this configuration, the voltage drop across the N channel FET M.sub.REPLICA 810 and the resistor R.sub.REPLICA 808 or equivalently the voltage difference between nodes 806 and 814, can be made substantially equal to the minimum dropout voltage requirement, V.sub.DROPOUT(MIN) of the output circuit of the current sink DAC 700, and can dynamically track the changes in V.sub.DROPOUT(MIN) due to programmed DAC current, process variations, temperature and time. This may be achieved when I.sub.REPLICA 812 is programmed to be a scaled down version of the high output current of the current sink DAC 700, such that the resistor R.sub.REPLICA 808 and the N channel FET M.sub.REPLICA 810 operate at the same current density as the resistor 740 and the N channel output FET 730 of the output circuit of the current sink DAC 700.

(72) As mentioned before, in the circuit of FIG. 8, the voltage at node 806 may be substantially equal to −1.Math.V.sub.SSX(MAX) and the voltage difference between nodes 806 and 814 may be substantially equal to V.sub.DROPOUT(MIN). By Kirchhoff's voltage law, this results in voltage at node 814 to be substantially equal to −1.Math.V.sub.SSX(MAX)−V.sub.DROPOUT(MIN). Based on the equations for I.sub.CTRL that yield higher power efficiency operation, this voltage at node 814 can be added to V.sub.OUTX and then the sum inverted in order to generate I.sub.CTRL. This can be achieved by using the inverting, attenuating adder circuit formed by the differential amplifiers 826, 818, and 836 and the resistors 864, 866, and 868. The amplifier 826 may be connected in a unity gain buffer configuration and buffers the output voltage V.sub.OUTX of the current sink DAC 700. This results in node 828 being substantially equal to V.sub.OUTX. In a similar fashion, the amplifier 818 may be connected in a unity gain buffer configuration and buffers the node 814. The node 820 may be substantially equal to node 814 which may be equal to −1.Math.V.sub.SSX(MAX)−V.sub.DROPOUT(MIN). The amplifier 836 and the resistors 864, 866, and 868 form an inverting, attenuating adder, such that the output of amplifier 836 at node 838 is substantially equal to

(73) $\frac{\left[\mathrm{VSSX}\left(\mathrm{MAX}\right)+\mathrm{VDROPOUT}\left(\mathrm{MIN}\right)\right]-\mathrm{VOUTX}}{M}.$
The inverting, attenuating adder attenuates or divides the sum voltage by M, which lowers the voltage swing on the node 838 by the same amount. M can be an integer greater than or equal to 5, to substantially attenuate the voltage swing on the node 838. This eases the design of the amplifier 836 since its output voltage swings much less using an inverting, attenuating adder.

(74) The output stage of the circuit in FIG. 8 may be a transconductance stage followed by a current mirror that converts the voltage at node 838 into the current I.sub.CTRL, and then mirrors it, such that the current I.sub.CTRL is sourced. The amplifier 842, N channel output FET 848, resistor 858 and the current mirror devices 860 and 870 form the output stage. I.sub.CTRL may be adjusted to equal

(75) $\frac{\left[\mathrm{VSSX}\left(\mathrm{MAX}\right)+\mathrm{VDROPOUT}\left(\mathrm{MIN}\right)\right]-\mathrm{VOUTX}}{R2\mathrm{\_INV}}$
for higher power efficiency operation. This can be achieved by setting the resistance of resistor 858 to be equal to R2_INV/M, since I.sub.CTRL is equal to the ratio of the voltage at node 838 to the resistance value of resistor 858. The implementation of FIG. 8 takes as inputs −1.Math.V.sub.SSX(MAX), V.sub.OUTX and V.sub.DROPOUT(MIN) and generates I.sub.CTRL required for higher power efficiency operation. By coupling the PS_CTRL pin 705 that I.sub.CTRL flows through to the FB pin and the voltage setting resistor network of an inverting DC-DC converter chip 760 that supplies the V.sub.SSX voltage, the HEPSCL can be implemented. It should be noted that the voltages V.sub.OUTX and V.sub.DROPOUT(MIN) can be dynamically changing due to programmed DAC current, process variation, temperature, voltage levels or time, and the circuit implementation shown in FIG. 8 would allow a HEPSCL to track the changes in V.sub.OUTX and V.sub.DROPOUT(MIN) and dynamically adjust I.sub.CTRL, such that the current sink DAC 700 operates at a higher power efficiency compared to the case when V.sub.SSX voltage is set as a constant voltage.

(76) Though a step-down buck DC-DC converter was used for V.sub.DDX in the current source DAC 100 case, the DC-DC converter described herein may be implemented not only as a buck DC-DC converter but also as a buck/boost, and boost. For the current sink DAC 700 case an inverting DC-DC converter was used but a single-ended primary-inductor converter (SEPIC) or a buck/boost type DC-DC converter may also be used. Also, as described with respect to FIG. 5, multiple DAC channels with a single power supply may be used; however, only the channel with the higher voltage will operate at the higher power efficiency.

(77) The control current that modulates the power supply can be a sub-circuit of the current source DAC or can be built using external components. As a result, the HEPSCL described herein may be applied to existing current source/sink DACs and can be fabricated on the same silicon chip as the current source/sink DACs or can be implemented as an external circuit for controlling the power supply. The HEPSCL also may be applied to a current source/sink DAC with a built-in DC-DC converter such that the DC-DC converter is controlled using the control current (I.sub.CTRL). Also, as described with respect to FIG. 6, the HEPSCL may be applied to a current source/sink DAC with a post LDO following the DC-DC converter such that the DC-DC converter and post LDO are controlled in tandem by identical control currents (I.sub.CTRL).

(78) In addition to applications for optical component biasing (e.g., in fiber modules for lasers), the circuits described herein may be used to control electromagnetic mirrors for LIDAR applications, as well as to control thermoelectric coolers for biosensors. These and other applications will become apparent to those skilled in the art based on this description.

ADDITIONAL DESCRIPTION AND ASPECTS

(79) Aspect 1 can include subject matter (such as a current source DAC) comprising at least one of a current source or a current sink digital-to-analog converter comprising a digital-to-analog converter circuit that converts a digital code to an analog current output, an output circuit that amplifies the analog current output of the digital-to-analog converter circuit to set a desired high current output for application to an output of the at least one current source or current sink digital-to-analog converter, and a power supply circuit that supplies power to the output circuit and a power supply control current to the at least one current source or current sink digital-to-analog converter to adjust an output of the power supply circuit in response to a variation in at least one of an output of the output circuit or a minimum dropout voltage requirement of the output circuit. Advantageously, power efficiency of the at least one current source or current sink digital-to-analog converter can be increased, such as compared to when an output of the power supply circuit is set as a constant voltage and no adjustment is made.

(80) In Aspect 2, the subject matter of Aspect 1 optionally includes the digital-to-analog converter circuit comprising a digital-to-analog converter that provides an analog voltage output and a transconductance circuit, the transconductance circuit converting the analog voltage output to the analog current output of the digital-to-analog converter circuit.

(81) In Aspect 3, the subject matter of Aspects 1 and/or 2 optionally includes a control pin on the current source or current sink digital-to-analog converter that is connected to the power supply control current and is adapted for coupling to the power supply circuit, the power supply control current adjusting the output of the power supply circuit in response to a change in an output voltage of the current source or current sink digital-to-analog converter.

(82) In Aspect 4, the subject matter of one or any combination of Aspects 1-3 optionally includes the power supply control current adjusting the output of the power supply circuit in response to a change in a minimum dropout voltage requirement of the output circuit of the at least one current source or current sink digital-to-analog converter.

(83) In Aspect 5, the subject matter of one or any combination of Aspects 1-4 optionally includes the power supply control current adjusting the output of the power supply circuit in response to a minimum or maximum power supply voltage requirement of the output circuit of the at least one current source or current sink digital-to-analog converter.

(84) In Aspect 6, the subject matter of one or any combination of Aspects 1-5 optionally includes a current control signal circuit that generates the power supply control current, the current control signal circuit comprising a smaller scale replica of the output circuit of the at least one current source or current sink digital-to-analog converter that determines the minimum dropout voltage requirement of the output circuit.

(85) In Aspect 7, the subject matter of one or any combination of Aspects 1-6 optionally includes the smaller scale replica of the output circuit being biased using a current generator that is programmed using the digital code such that the smaller scale replica of the output circuit operates at a same current density as the output circuit of the at least one current source or current sink digital-to-analog converter.

(86) In Aspect 8, the subject matter of one or any combination of Aspects 1-7 where the minimum or maximum power supply voltage requirement of the output circuit is determined by utilizing a bandgap voltage reference.

(87) In Aspect 9, the subject matter of one or any combination of Aspects 1-8 optionally includes the power supply circuit comprising a DC-DC voltage converter, a voltage setting resistor network, and a feedback pin to set an output voltage of the DC-DC voltage converter, the voltage setting resistor network comprising a feedback resistor with a first terminal coupled to the output voltage of the DC-DC voltage converter and a second terminal coupled to the feedback pin, the voltage setting resistor network further comprising a termination resistor with a first terminal coupled to the feedback pin and a second terminal coupled to a substantially constant reference voltage, the DC-DC voltage converter supplying power to the output circuit of a current source digital-to-analog converter, the current source digital-to-analog converter comprising a control pin that is coupled to the feedback pin, the power supply control current being sunk through the control pin, and the current source digital-to-analog converter adjusting the output voltage of the DC-DC voltage converter by adjusting the power supply control current.

(88) In Aspect 10, the subject matter of one or any combination of Aspects 1-9 optionally includes resistance values of the feedback resistor and the termination resistor of the voltage setting resistor network of the DC-DC voltage converter being chosen such that a sum of (1) a feedback voltage of the DC-DC voltage converter and (2) a ratio of a resistance of the feedback resistor and a resistance of the termination resistor multiplied by the feedback voltage of the DC-DC voltage converter is equal to a minimum required supply voltage for the output circuit of the current source digital-to-analog converter.

(89) In Aspect 11, the subject matter of one or any combination of Aspects 1-10 optionally includes the current source digital-to-analog converter adjusting an output of the power supply circuit in response to a variation in at least one of an output of the output circuit or a minimum dropout voltage requirement of the output circuit by utilizing a power supply control loop that accepts at a first input the output voltage of the current source digital-to-analog converter (V.sub.OUTX), at a second input a minimum required supply voltage for the output circuit of the current source digital-to-analog converter (V.sub.DDX(MIN)), and at a third input a minimum dropout voltage requirement of the output circuit of the current source digital-to-analog converter (V.sub.DROPOUT(MIN)), the power supply control loop outputting the power supply control current, the power supply control current having a value of zero when V.sub.OUTX is less than a difference between V.sub.DDX(MIN) and V.sub.DROPOUT(MIN) and otherwise having a value that is a function of a resistance of the feedback resistor of the voltage setting resistor network of the DC-DC converter and a difference between V.sub.OUTX and the difference between V.sub.DDX(MIN) and V.sub.DROPOUT(MIN):

(90) In Aspect 12, the subject matter of one or any combination of Aspects 1-11 optionally includes a current source digital-to-analog converter comprising a plurality of output channels, two or more of the output channels sharing a power supply circuit that supplies power to the output circuit of the two or more current source digital-to-analog converter output channels, the current source digital-to-analog converter further comprising an analog voltage comparator that determines a current source digital-to-analog converter output channel with a higher output voltage at any given time amongst the two or more of the current source digital-to-analog converter output channels sharing the power supply circuit and that selects an output channel voltage to be processed by the power supply control loop to generate the power supply control current that is used to adjust the output voltage of the power supply circuit.

(91) In Aspect 13, the subject matter of one or any combination of Aspects 1-12 optionally includes a current source digital-to-analog converter comprising a plurality of output channels, two or more of the output channels sharing a power supply circuit that supplies power to the output circuit of the two or more current source digital-to-analog converter output channels, where one of the two or more output channels share a power supply circuit that is determined to be a master output channel, the master output channel voltage being selected to be processed by the power supply control loop to generate the power supply control current that is used to adjust the output voltage of the power supply circuit.

(92) In Aspect 14, the subject matter of one or any combination of Aspects 1-13 optionally includes a low dropout (LDO) voltage regulator between the power supply circuit and the at least one current source or current sink digital-to-analog converter, the LDO voltage regulator filtering the noise of the power supply circuit.

(93) In Aspect 15, the subject matter of one or any combination of Aspects 1-14 optionally includes the LDO voltage regulator comprising an LDO voltage setting resistor network and a voltage adjust pin to set an output voltage of the LDO voltage regulator, LDO voltage setting resistor network comprising an LDO feedback resistor with a first terminal coupled to an output voltage of the LDO voltage regulator and a second terminal coupled to the voltage adjust pin of the LDO voltage regulator, the LDO voltage setting resistor network further comprising an LDO termination resistor with a first terminal coupled to the voltage adjust pin of the LDO voltage regulator and a second terminal coupled to a substantially constant reference voltage, the LDO voltage regulator supplying power to an output circuit of a current source digital-to-analog converter, and the current source digital-to-analog converter comprising an LDO control pin that is coupled to the voltage adjust pin of the LDO voltage regulator, the current source digital-to-analog converter further comprising an LDO power supply control current that is substantially equal to the power supply control current of the current source digital-to-analog converter that is sunk through the LDO control pin such that the current source digital-to-analog converter can adjust the output voltage of the LDO voltage regulator by adjusting the LDO power supply control current.

(94) In Aspect 16, the subject matter of one or any combination of Aspects 1-15 optionally includes resistance values of the LDO feedback resistor and the LDO termination resistor of the LDO voltage setting resistor network of the LDO voltage regulator being chosen such that a sum of (1) a voltage at the voltage adjust pin of the LDO voltage regulator and (2) a ratio of a resistance of the LDO feedback resistor and a resistance of the LDO termination resistor multiplied by the voltage at the voltage adjust pin of the LDO voltage regulator is equal to a minimum required supply voltage for the output circuit of the current source digital-to-analog converter.

(95) In Aspect 17, the subject matter of one or any combination Aspects 1-16 optionally includes the power supply circuit supplying power to the LDO voltage regulator comprising a DC-DC voltage converter, an output voltage of the DC-DC voltage converter being adjusted by a current source digital-to-analog converter comprising the power supply control current, the DC-DC voltage converter comprising a voltage setting resistor network and a feedback pin to set the output voltage of the DC-DC voltage converter, the voltage setting resistor network comprising a feedback resistor with a first terminal coupled to the output voltage of the DC-DC voltage converter and a second terminal coupled to the feedback pin, the voltage setting resistor network further comprising a termination resistor with a first terminal coupled to the feedback pin and a second terminal coupled to a substantially constant reference voltage, resistance values of the feedback resistor and the termination resistor of the voltage setting resistor network of the DC-DC voltage convertor being chosen such that a resistance of the feedback resistor and a resistance of the LDO feedback resistor are substantially equal and a sum of (1) a feedback voltage of the DC-DC voltage converter and (2) a ratio of a resistance of the feedback resistor and a resistance of the termination resistor multiplied by the feedback voltage of the DC-DC voltage converter is equal to a sum of a minimum required supply voltage for the output circuit of the current source digital-to-analog converter and a minimum dropout voltage requirement of the LDO voltage regulator.

(96) In Aspect 18, the subject matter of one or any combination of Aspects 1-17 optionally includes the power supply circuit comprising an inverting DC-DC voltage converter that generates a negative voltage with respect to a ground voltage, the inverting DC-DC voltage converter comprising a voltage setting resistor network, a feedback pin, and a reference pin to set an output voltage of the inverting DC-DC voltage converter, the voltage setting resistor network comprising an inverting feedback resistor with a first terminal coupled to the output voltage of the inverting DC-DC voltage converter and a second terminal coupled to the feedback pin, the voltage setting resistor network further comprising an inverting termination resistor with a first terminal coupled to the feedback pin and a second terminal coupled to the reference pin, the inverting DC-DC voltage converter supplying power to an output circuit of a current sink digital-to-analog converter, the current sink digital-to-analog converter comprising a control pin that is coupled to the feedback pin of the inverting DC-DC voltage converter, and the current sink digital-to-analog converter further comprising the power supply control current being sourced through the control pin such that the current sink digital-to-analog converter can adjust the output voltage of the inverting DC-DC voltage converter by adjusting the power supply control current.

(97) In Aspect 19, the subject matter of one or any combination of Aspects 1-18 optionally includes resistance values of the inverting feedback resistor and the inverting termination resistor of the voltage setting resistor network of the inverting DC-DC voltage converter being chosen such that a ratio of a resistance of the inverting feedback resistor and a resistance of the inverting termination resistor multiplied by a voltage at the reference pin of the inverting DC-DC voltage converter is a value having a magnitude that is a negative of a maximum allowed value of the negative supply voltage for the output circuit of the current sink digital-to-analog converter.

(98) In Aspect 20, the subject matter of one or any combination of Aspects 1-19 optionally includes the current sink digital-to-analog converter adjusting an output of the power supply circuit in response to a variation in at least one of an output of the output circuit or a minimum dropout voltage requirement of the output circuit by utilizing a power supply control loop that accepts at a first input the output voltage of the current sink digital-to-analog converter (V.sub.OUTX), at a second input a maximum allowed value of the negative supply voltage for the output circuit of the current sink digital-to-analog converter (V.sub.SSX(MAX)), and at a third input a minimum dropout voltage requirement of the output circuit of the current sink digital-to-analog converter (V.sub.DROPOUT(MIN)), the power supply control loop outputting the power supply control current, the power supply control current having a value of zero when V.sub.OUTX is greater than a sum of V.sub.SSX(MAX) and V.sub.DROPOUT(MIN) and otherwise having a value that is a function of a resistance of the inverting feedback resistor of the voltage setting resistor network of the DC-DC converter and a difference between V.sub.OUTX and a sum of V.sub.SSX(MAX) and V.sub.DROPOUT(MIN).

(99) In Aspect 21, the subject matter of one or any combination of Aspects 1-20 optionally includes the power supply circuit comprising a single ended primary inductor (SEPIC) DC-DC voltage converter.

(100) In Aspect 22, the subject matter of one or any combination of Aspects 1-20 optionally includes the power supply circuit comprising a buck/boost DC-DC voltage converter.

(101) In Aspect 23, the subject matter of one or any combination of Aspects 1-20 optionally includes the power supply circuit comprising a boost DC-DC voltage converter.

(102) Aspect 24 can include subject matter (such as a circuit for biasing a semiconductor optical amplifier (SOA)) comprising an optical component biased at a programmable current, the programmable current supplied by an output of at least one of a current source or current sink digital-to-analog converter, the at least one current source or current sink digital-to-analog converter comprising an output circuit and a power supply control current that is coupled to a power supply circuit that supplies power to the output circuit of the at least one current source or current sink digital-to-analog converter, the power supply control current adjusting an output of the power supply circuit in response to a variation in at least one of an output of the output circuit or a minimum dropout voltage requirement of the output circuit. Advantageously, power efficiency of the at least one current source or current sink digital-to-analog converter can be increased, such as compared to when an output of the power supply circuit is set as a constant voltage and no adjustment is made.

(103) In Aspect 25, the subject matter of Aspect 24 optionally includes the optical component comprising a laser diode used for pumping an Erbium-Doped Fiber Amplifier (EDFA).

(104) In Aspect 26, the subject matter of Aspects 24 and/or 25 optionally includes, the optical component comprising a variable optical attenuator (VOA).

(105) Aspect 27 can include subject matter (such as an integrated circuit) comprising at least one of an integrated current source or current sink digital-to-analog converter, an integrated power supply circuit that supplies power to an output circuit of the at least one integrated current source or current sink digital-to-analog converter, further comprising an integrated power supply control current that is coupled to the integrated power supply circuit that supplies power to the output circuit of the at least one integrated current source or current sink digital-to-analog converter, the integrated power supply control current adjusting an output of the integrated power supply circuit in response to a variation in at least one of an output of the output circuit or a minimum dropout voltage requirement of the output circuit. Advantageously, power efficiency of the at least one current source or current sink digital-to-analog converter can be increased, such as compared to when an output of the power supply circuit is set as a constant voltage and no adjustment is made.

(106) These non-limiting Aspects can be combined in any permutation or combination. The above detailed description includes references to the accompanying drawings, which form a part of the detailed description. The drawings show, by way of illustration, specific embodiments in which the invention can be practiced. These embodiments are also referred to herein as “examples.” All publications, patents, and patent documents referred to in this document are incorporated by reference herein in their entirety, as though individually incorporated by reference. In the event of inconsistent usages between this document and those documents so incorporated by reference, the usage in the incorporated reference(s) should be considered supplementary to that of this document; for irreconcilable inconsistencies, the usage in this document controls.

(107) In this document, the terms “a” or “an” are used, as is common in patent documents, to include one or more than one, independent of any other instances or usages of “at least one” or “one or more.” In this document, the term “or” is used to refer to a nonexclusive or, such that “A or B” includes “A but not B,” “B but not A,” and “A and B,” unless otherwise indicated. In the appended claims, the terms “including” and “in which” are used as the plain-English equivalents of the respective terms “comprising” and “wherein.” Also, in the following claims, the terms “including” and “comprising” are open-ended, that is, a system, device, article, or process that includes elements in addition to those listed after such a term in a claim are still deemed to fall within the scope of that claim. Moreover, in the following claims, the terms “first,” “second,” and “third,” etc. are used merely as labels, and are not intended to impose numerical requirements on their objects. Method examples described herein can be machine or computer-implemented at least in part.

(108) The above description is intended to be illustrative, and not restrictive. For example, the above-described examples (or one or more aspects thereof) may be used in combination with each other. Other embodiments can be used, such as by one of ordinary skill in the art upon reviewing the above description. The Abstract is provided to comply with 37 C.F.R. § 1.72(b), to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Also, in the above Detailed Description, various features may be grouped together to streamline the disclosure. This should not be interpreted as intending that an unclaimed disclosed feature is essential to any claim. Rather, inventive subject matter may lie in less than all features of a particular disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment. The scope of the invention should be determined with reference to any appended claims, along with the full scope of equivalents to which such claims are entitled.