Stacked high barrier III-V power semiconductor diode

Abstract

A stacked high barrier III-V power semiconductor diode having an at least regionally formed first metallic terminal contact layer and a heavily doped semiconductor contact region of a first conductivity type with a first lattice constant, a drift layer of a second conductivity type, a heavily doped metamorphic buffer layer sequence of the second conductivity type is formed. The metamorphic buffer layer sequence has an upper side with the first lattice constant and a lower side with a second lattice constant. The first lattice constant is greater than the second lattice constant. The upper side of the metamorphic buffer layer sequence is arranged in the direction of the drift layer. A second metallic terminal contact layer is arranged below the lower side of the metamorphic buffer layer sequence. The second metallic terminal contact layer is integrally bonded with a semiconductor contact layer.

Claims

1. A stacked high barrier III-V power semiconductor diode comprising: at least a regionally formed first metallic terminal contact layer; a semiconductor contact region of a first conductivity type with a dopant concentration greater than 1×10.sup.18 N/cm.sup.3 and with a first lattice constant; a drift layer of a second conductivity type with the first lattice constant and with a layer thickness greater than 10 microns; a doped intermediate layer of the first conductivity type with a dopant concentration of less than 5×10.sup.18 N/cm.sup.3, with the first lattice constant and with a thickness between 1 micron and 30 microns; a metamorphic buffer layer sequence of the second conductivity type with a layer thickness of more than 0.2 microns and less than 20 microns, the metamorphic buffer layer sequence having an upper side with the first lattice constant and a lower side with a second lattice constant, the upper side being arranged in a direction of the drift layer; and a second metallic terminal contact layer formed below the lower side of the metamorphic buffer layer sequence, wherein the first lattice constant is greater than the second lattice constant, wherein the first metallic terminal contact layer, the semiconductor contact region, the drift layer, the intermediate layer, the metamorphic buffer layer sequence, the second metallic terminal contact layer are arranged in the order mentioned, and wherein at least the semiconductor contact region and the drift layer and the metamorphic buffer layer sequence comprise a III-V compound.

2. The stacked high barrier III-V power semiconductor diode according to claim 1, wherein the metamorphic buffer layer sequence has a dopant concentration greater than 5×10.sup.17 N/cm.sup.3 or greater than 1×10.sup.17N/cm.sup.3 or greater than 3×10.sup.16 N/cm.sup.3 or greater than 1×10.sup.16 N/cm.sup.3.

3. The stacked high barrier III-V power semiconductor diode according to claim 1 or 2, wherein the first metallic terminal contact layer is integrally bonded with the semiconductor contact region and the second metallic terminal contact layer is integrally bonded with the metamorphic buffer layer sequence.

4. The stacked high barrier Ill-V power semiconductor diode according to claim 1 or 2, further comprising: a substrate layer of the first conductivity provided below the metamorphic buffer layer sequence, the substrate layer having the second lattice constant and comprising Ge or GaAs or InP.

5. The stacked high barrier III-V power semiconductor diode according to claim 1 or 2, further comprising: a substrate layer of the first conductivity type provided below the metamorphic buffer layer sequence, the substrate layer having the second lattice constant and comprising a layer sequence made of InP and GaAs.

6. The stacked high barrier III-V power semiconductor diode according to claim 1 or 2, wherein the metamorphic buffer layer sequence forms a semiconductor contact layer integrally bonded with the second metallic terminal contact layer, wherein the stacked high barrier III-V power semiconductor diode further comprises: a first semiconductor layer with the second lattice constant arranged between the metamorphic buffer layer sequence and the second metallic terminal contact layer, the first semiconductor layer being of the second conductivity type and having a dopant concentration greater than 1×10.sup.18N/cm.sup.3 and a layer thickness above 0.1 microns.

7. The stacked high barrier III-V power semiconductor diode according to claim 1, further comprising: a substrate layer of the second conductivity type provided below the metamorphic buffer layer sequence; and a first semiconductor layer formed below the metamorphic buffer layer sequence as a part of the substrate layer, wherein the substrate layer is formed as a semiconductor contact layer of the first conductivity type and has a thickness between 10 microns and 450 microns or between 350 microns and 1000 microns.

8. The stacked high barrier III-V power semiconductor diode according to claim 1 or 2, further comprising: a second semiconductor layer with the first lattice constant, the second semiconductor layer being of the second conductivity type or the first conductivity type and having a dopant concentration greater than 1×10.sup.18 N/cm.sup.3 and a layer thickness of more than 0.1 microns.

9. The stacked high barrier III-V power semiconductor diode according to claim 1 or 2, wherein the semiconductor contact region and the semiconductor layers arranged between the semiconductor contact region and the upper side of the metamorphic buffer layer sequence each comprise an InGaAs compound.

10. The stacked high barrier III-V power semiconductor diode according to claim 1 or 2, wherein the first conductivity type is p and the second conductivity type is n.

11. The stacked high barrier III-V power semiconductor diode according to claim 1 or 2, wherein the semiconductor contact region is formed as a planar layer or is trough-shaped.

12. The stacked high barrier III-V power semiconductor diode according to claim 8, wherein the second semiconductor layer comprises a GaAs compound, and wherein the drift layer and the semiconductor contact region each comprise an InGaAs compound.

13. The stacked high barrier III-V power semiconductor diode according to claim 10, wherein the second semiconductor layer and the drift layer and the semiconductor contact region each comprise an InGaAs compound.

14. The stacked high barrier III-V power semiconductor diode according to claim 1 or 2, wherein the semiconductor contact region and the semiconductor layers are formed monolithically.

15. The stacked high barrier III-V power semiconductor diode according to claim 1 or 2, wherein the drift layer consists of In.sub.xGa.sub.1−xAs with 0.1<x<0.6.

16. The stacked high barrier III-V power semiconductor diode according to claim 1 or 2, wherein the metamorphic buffer layer sequence consists of In.sub.xGa.sub.1−xAs with 0≤x≤1, wherein on a lower side adjacent to the substrate layer, x is between 0 and 0.02, x increases from the lower side to the upper side up to a limit value of x=0.6 or x=0.4 and wherein the increase of x between the individual layers of the buffer layer sequence from the lower side to the upper side of the buffer layer sequence is formed to be stepwise or linear or otherwise increasing.

17. The stacked high barrier Ill-V power semiconductor diode according to claim 1, wherein the drift layer is directly adjacent to the semiconductor contact region.

18. The stacked high barrier III-V power semiconductor diode according to claim 1, wherein the metamorphic buffer layer sequence has dopant concentration greater than 5×10.sup.17 N/cm.sup.3.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus, are not limitive of the present invention, and wherein:

(2) FIG. 1 is a cross-sectional view of an exemplary embodiment of a power semiconductor diode according to the invention,

(3) FIG. 2 is a cross-sectional view of an exemplary embodiment of a power semiconductor diode according to the invention,

(4) FIG. 3 is a cross-sectional view of an exemplary embodiment of a power semiconductor diode according to the invention,

(5) FIG. 4 is a cross-sectional view of an exemplary embodiment of a power semiconductor diode according to the invention,

(6) FIG. 5 is a cross-sectional view of an exemplary embodiment of a power semiconductor diode according to the invention,

(7) FIG. 6 is a cross-sectional view of an exemplary embodiment of a power semiconductor diode according to the invention,

(8) FIG. 7 is a cross-sectional view of an exemplary embodiment of a power semiconductor diode according to the invention,

(9) FIG. 8 is a cross-sectional view of an exemplary embodiment of a power semiconductor diode according to the invention,

(10) FIG. 9 is a cross-sectional view of an exemplary embodiment of a power semiconductor diode according to the invention, and

(11) FIG. 10 is a cross-sectional view of an exemplary embodiment of a power semiconductor diode according to the invention.

DETAILED DESCRIPTION

(12) In all figures, for reasons of clarity, in each case only a sectional view or a cross-sectional view of a III-V power semiconductor diode is shown.

(13) It should be noted, however, that in a plan view, all of the III-V power semiconductor diodes depicted in the sectional view have either a square or a rectangular circumference, or a rectangular circumference with rounded edges or a circular circumference.

(14) In other words, in the plan view, the III-V power semiconductor diode has the same layer sequences as in the respective cross-sectional view.

(15) Also, the semiconductor contact regions and the semiconductor layers in each case comprise a III-V compound or consist of the elements of a III-V compound, wherein each semiconductor region and each semiconductor layer each have an upper side and a lower side.

(16) In this case, the upper side points in the direction of the metallic contact or metallic terminal contact, which is arranged on the upper side of the layer stack, while the lower side in each case points in the direction of the metallic contact or metallic terminal contact, which is arranged on the lower side of the layer stack.

(17) It should also be noted for all embodiments that the term “intermediate layer” is preferably used synonymously with the term “intermediate region”.

(18) However, the term “intermediate region” or the term “semiconductor contact region” generally designates a trough-shaped configuration, whereas the term “intermediate layer” or “semiconductor contact layer” generally denotes in each case a layer having at least a planar lower side and/or a planar upper side.

(19) In particular, the depicted metamorphic buffers include a plurality of III-V semiconductor layers or consist of a plurality of III-V semiconductor layers, wherein the lattice constant generally changes from one III-V semiconductor layer to another.

(20) In the present case, a plurality is understood to mean a number of at least three and a maximum of thirty, or a number of at least five and a maximum of ten semiconductor layers. Further, the metamorphic buffer is formed in each case with as low an impedance as possible, that is, heavily doped.

(21) Furthermore, it is true for all the illustrated embodiments that the III-V power semiconductor diodes comprise an upper side and a lower side, wherein preferably by means of a metallic terminal contact layer formed on the lower side, the III-V power semiconductor diode is arranged as a so-called “die” on a metal frame or metal carrier also called a “lead frame”.

(22) A full-surface formation of the metallic terminal contact layer on the lower side, in particular as large as possible, improves the thermal coupling to the carrier.

(23) The illustration in FIG. 1 shows a stacked high barrier III-V power semiconductor diode LHD in a PN structure.

(24) The power semiconductor diode LHD comprises a regionally formed first metallic terminal contact layer M1 and a p+ heavily doped semiconductor contact region PPL with a dopant concentration greater than 1×10.sup.18 N/cm.sup.3 and a first lattice constant.

(25) The semiconductor contact region PPL is trough-shaped and is preferably prepared by means of a mask and implantation process. In this case, dopants are introduced into a region of the n− drift layer or the p− drift layer, wherein the dopants are preferably activated by a temperature process. The first metallic terminal contact layer M1 and the p+ heavily doped semiconductor contact region PPL are integrally bonded to another.

(26) Between the p+ heavily doped semiconductor contact region PPL and an n− drift layer NMID, a p− intermediate region PMI is arranged in a trough-shaped form, so that the p+ heavily doped semiconductor contact region PPL is spaced apart on all sides from the n-drift layer NMID. The p− doped intermediate region PMI is shown in dashed lines because the p− doped intermediate region PMI is optional, i.e., in a non− illustrated embodiment, the p− intermediate region PMI is not formed. It is understood that without the p− intermediate region PMI, the p+ heavily doped semiconductor contact region PPL is integrally bonded with the n− drift layer NMID.

(27) The p− intermediate region PMI has a doping of less than the p+ heavily doped semiconductor contact region PPL and greater than the n− drift layer NMID and is integrally bonded with the p+ heavily doped semiconductor contact region PPL and the n− drift layer NMID. The p− intermediate region PMI has a dopant concentration of less than 5×10.sup.15 N/cm.sup.3 and the first lattice constant and a thickness between 1 micron and 30 microns.

(28) In addition to the n− drift layer NMID with the first lattice constant and with a layer thickness greater than 10 microns, the III-V power semiconductor diode LHD also comprises an n+ heavily doped metamorphic buffer layer sequence NMP with a dopant concentration greater than 1×10.sup.17 N/cm.sup.3 and a layer thickness above 0.2 microns and smaller than 20 microns. The n-drift layer NMID and the n+ heavily doped metamorphic buffer layer sequence NMP are integrally bonded with one another.

(29) The metamorphic buffer layer sequence NMP has an upper side with the first lattice constant and a lower side with a second lattice constant, wherein the first lattice constant is greater than the second lattice constant. The upper side of the metamorphic buffer layer sequence NMP is arranged in the direction of the n− drift layer NMID.

(30) On the lower side of the metamorphic buffer layer sequence NMP, a second metallic terminal contact layer M2 is formed, so that the second metallic terminal contact layer M2 is integrally bonded with the metamorphic buffer layer sequence NMP.

(31) The aforementioned regions and layers are arranged in the order mentioned.

(32) In an alternative embodiment, not shown, the high barrier III-V power semiconductor diode LHD comprises more III-V semiconductor layers, in particular at the PN junction and/or between a very heavily doped semiconductor layer or semiconductor region, with a dopant concentration above 1×10.sup.17 N/cm.sup.3 and a low doped semiconductor layer or semiconductor region with a dopant concentration below 5×10.sup.17 N/cm.sup.3.

(33) The illustration in FIG. 2 shows a stacked high barrier III-V power semiconductor diode LHD in an n over p structure. The power semiconductor diode LHD has a regionally formed first metallic terminal contact layer M1 and an n+ heavily doped semiconductor contact region NPL with a dopant concentration greater than 1×10.sup.18 N/cm.sup.3 and with a first lattice constant.

(34) The semiconductor contact region NPL is formed to be trough-shaped and is preferably made by means of a mask and implantation process. The first metallic terminal contact layer M1 and the n+ heavily doped semiconductor contact region NPL are integrally bonded with one another.

(35) Between the n+ heavily doped semiconductor contact region NPL and a p− drift layer PMID, an n− intermediate region or n− intermediate layer NMI is arranged in a trough-shaped formation, so that the n+ heavily doped semiconductor contact region NPL is spaced apart on all sides from the p− drift layer PMID. The n− doped intermediate region is illustrated as an optional semiconductor layer with dashed lines, i.e., in a non-illustrated embodiment, the n intermediate region is not formed.

(36) It is understood that without the n− intermediate region NMI, the n+ heavily doped semiconductor contact region NPL is integrally bonded with the p− drift layer PMID.

(37) The n− intermediate region NMI has a doping less than the n+ heavily doped semiconductor contact region NPL and greater than the p− drift layer PMID and is integrally bonded with the n+ heavily doped semiconductor contact region NPL and the p− drift layer PMID. The n− intermediate region NMI has a dopant concentration of less than 5×10.sup.15 N/cm.sup.3 and the first lattice constant and a thickness between 1 micron and 30 microns.

(38) In addition to the p− drift layer PMID with the first lattice constant and with a layer thickness greater than 10 microns, the III-V power semiconductor diode LHD also has a p+ heavily doped metamorphic buffer layer sequence PMP with a dopant concentration greater than 1×10.sup.17 N/cm.sup.3 and a layer thickness above 0.2 microns and less than 20 microns. The p− drift layer PMID and the p+ heavily doped metamorphic buffer layer sequence PMP are integrally bonded with one another.

(39) On the upper side, the p+ metamorphic buffer layer sequence PMP has a first lattice constant, and a second lattice constant on the lower side, wherein the first lattice constant is greater than the second lattice constant. The upper side of the metamorphic buffer layer sequence PMP is arranged in the direction of the drift layer PMID.

(40) On the lower side of the metamorphic buffer layer sequence PMP, a second metallic terminal contact layer M2 is formed, so that the second metallic terminal contact layer M2 is integrally bonded with the metamorphic buffer layer sequence PMP.

(41) The aforementioned regions and layers are arranged in the order mentioned. In an alternative embodiment, not shown, the high barrier III-V power semiconductor diode comprises further III-V semiconductor layers particularly at the PN junction and/or between a very heavily doped semiconductor layer or semiconductor region with a dopant concentration more than 1×10.sup.17 N/cm.sup.3 and a very low doped semiconductor layer or semiconductor region with a dopant concentration below 5×10.sup.17 N/cm.sup.3.

(42) A third embodiment is shown in FIG. 3. In the following, only the differences from the embodiment shown in connection with FIG. 1 will be explained.

(43) The intermediate layer PMI and the p+ heavily doped semiconductor contact layer PPL are each formed in a planar manner. Such layer arrangements are produced by means of epitaxial processes, in particular by means of an MOVPE system. The p-type doped intermediate layer PMI is shown in dashed lines, since the p-type doped intermediate layer PMI is optional, i.e., in a non-illustrated embodiment, the p-type intermediate layer PMI is not formed.

(44) A fourth embodiment is shown in FIG. 4. In the following, only the differences from the embodiment shown in connection with FIG. 2 will be explained.

(45) The intermediate layer NMI and the n+ heavily doped semiconductor contact layer NPL are each formed in a planar manner. Such layer arrangements are produced by means of epitaxial processes, in particular by means of an MOVPE system. The n-type doped intermediate layer NMI is shown in dashed lines, since the n-type doped intermediate layer NMI is optional, i.e., in a non-illustrated embodiment, the n-type intermediate layer NMI is not formed.

(46) A fifth embodiment is shown in FIG. 5. In the following, only the differences from the embodiment shown in connection with FIG. 1 will be explained.

(47) The p− drift layer PMID is integrally bonded with the trough-shaped heavily doped p+ semiconductor contact region PPL, wherein the p+ semiconductor contact region PPL is produced by means of an implantation into the p− drift layer PMID. As a result, the p− drift layer is no longer planar on the upper side.

(48) The p− drift layer PMID is integrally bonded with the n− doped intermediate layer NMI and the heavily doped metamorphic buffer layer sequence NMP, wherein the p− drift layer PMID is planar on the lower side and the n− doped intermediate layer NMI is planar on the upper side and on the lower side, and the heavily doped metamorphic buffer layer sequence NMP is planar on the upper side and on the lower side.

(49) The n− doped intermediate layer NMI is shown in dashed lines since the n− doped intermediate layer NMI is optional, that is, in a non-illustrated embodiment, the n− intermediate layer NMI is not formed. It is understood that without the n− intermediate layer NMI, the lower side of the p− drift layer PMID is integrally bonded with the upper side of the n+ metamorphic buffer layer sequence NMP.

(50) A sixth embodiment is shown in FIG. 6. In the following, only the differences from the embodiment shown in connection with FIG. 2 will be explained.

(51) An n− drift layer NMID is integrally bonded with the trough-shaped heavily doped n+ semiconductor contact region NPL, wherein the n+ semiconductor contact region NPL is produced by means of implantation into the n− drift layer NMID. Thereby, the n− drift layer NMID is no longer formed to be planar on the upper side.

(52) A p− doped intermediate layer PMI and the heavily doped metamorphic buffer layer sequence PMP are integrally bonded with the n− drift layer NMID, wherein the n− drift layer NMID is planar on the lower side and the p− doped intermediate layer PMI is planar on the upper side and on the lower side and the heavily doped metamorphic buffer layer sequence PMP is planar on the upper side and on the lower side.

(53) The p-type doped intermediate layer PMI is shown in dashed lines because the p− doped intermediate layer PMI is optional, that is, in a non-illustrated embodiment, the p− intermediate layer PMI is not formed. It is understood that without the p− intermediate layer PMI, the lower side of the n− drift layer NMID is integrally bonded with the upper side of the p+ metamorphic buffer layer sequence PMP.

(54) FIG. 7 shows a seventh embodiment. In the following, only the differences from the embodiment shown in connection with FIG. 5 will be explained.

(55) The p− drift layer PMID is integrally bonded with the stacked heavily doped p+ semiconductor contact region PPL, wherein the p+ semiconductor contact region PPL is produced by an epitaxial process step. As a result, the p+ semiconductor contact region PPL and the p− drift layer PMID are each formed to be planar.

(56) An eighth embodiment is shown in FIG. 8. In the following, only the differences from the embodiment shown in connection with FIG. 6 will be explained.

(57) The n− drift layer NMID is integrally bonded with the layered heavily doped n+ semiconductor contact region NPL, wherein the n+ semiconductor contact region NPL is produced by an epitaxial process step. As a result, the n+ semiconductor contact region NPL and the n− drift layer NMID are each formed to be planar.

(58) FIG. 9 shows a ninth embodiment of a p over n structure. In the following, only the differences from the embodiment shown in connection with FIGS. 1 and 3 are explained.

(59) The first metallic terminal contact layer M1 regionally formed on the upper side of the stacked power semiconductor diode LHD is integrally bonded with the upper side of a p+ heavily doped semiconductor contact layer PPL consisting of an InGaAs compound. The lower side of the p+ heavily doped semiconductor contact layer PPL is integrally bonded with the upper side of the p− intermediate layer PMI consisting of an InGaAs compound. The p− intermediate layer PMI and the p+ heavily doped semiconductor contact layer PPL are each formed to be planar, wherein the two layer arrangements are preferably produced by means of an epitaxial process, in particular by means of an MOVPE system.

(60) The lower side of the p− intermediate layer PMI is integrally bonded with the upper side of a planar n− drift layer NMID consisting of an InGaAs compound.

(61) The lower side of the n− drift layer NMID is integrally bonded with the upper side of the planar n+ heavily doped metamorphic buffer layer sequence NMP consisting of an InGaAs compound.

(62) It is understood that the upper side of the n+ heavily doped metamorphic buffer layer sequence NMP has the same lattice constant as the InGaAs semiconductor layers resting on the upper side of the n+ heavily doped metamorphic buffer layer sequence NMP. In other words, the resting InGaAs semiconductor layers are lattice matched to one another. Preferably, the InGaAs layers comprise the InP lattice constant.

(63) The lower side of the n+ heavily doped metamorphic buffer layer sequence NMP is integrally bonded with the upper side of an n+ doped GaAs substrate SUB. The n+ doped GaAs substrate is preferably undiluted. For example, a 4″ GaAs wafer has a thickness of approximately 450 microns and a 6″ GaAs wafer has a thickness of about 650 microns.

(64) The lower side of the n+ doped GaAs substrate SUB is integrally bonded with the full-surface second metallic terminal layer M2. The second metallic terminal layer M2 preferably consists of an alloy made from Au and/or Pd and/or Ge.

(65) In a non-illustrated embodiment, the individual semiconductor layers consisting at least partly of an InGaAs compound are not integrally bonded with each other, as further layers consisting of an InGaAs compound are formed therebetween. For example, an additional n-type doped intermediate layer can be arranged between the n− drift layer NMID and the n+ heavily doped metamorphic buffer layer sequence NMP, wherein said additional n-type doped intermediate layer has a thickness between 1 micron and 15 microns. Furthermore, the doping of the additional intermediate layer is greater than the doping of the n− drift layer NMID but less than the doping of the n+ heavily doped metamorphic buffer layer sequence NMP.

(66) It should also be noted that instead of the p over n structure, an n over p structure corresponding to the embodiments illustrated in connection with the illustrations of FIG. 4 or 6 or 8 can also be formed.

(67) A tenth embodiment is shown in FIG. 10. In the following, only the differences from the embodiment shown in connection with FIG. 9 will be explained.

(68) An n+ first heavily doped semiconductor layer NPLS1 of GaAs formed as a semiconductor contact layer is disposed between the n+ heavily doped metamorphic buffer layer sequence NMP and the second metallic terminal contact layer M2. The first heavily doped semiconductor layer NPLS1 has a dopant concentration greater than 1×10.sup.18 N/cm.sup.3 and a layer thickness of more than 0.1 microns and of less than 10 microns or less than 5 microns.

(69) An n+ second heavily doped semiconductor layer NPLS2 of an InGaAs compound is arranged between the n− drift layer NMID and the n+ heavily doped metamorphic buffer layer sequence NMP. It is understood that the lattice constant of the n+ second heavily doped semiconductor layer NPLS2 of the lattice constant corresponds to the overlying n− drift layer NMID, that is, the n+ second heavily doped semiconductor layer NPLS2 and the n− drift layer NMID are lattice matched to each other.

(70) The n+ second heavily doped semiconductor layer NPLS2 has a dopant concentration greater than 1×10.sup.18 N/cm.sup.3 and a layer thickness of more than 0.1 microns.

(71) The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are to be included within the scope of the following claims.