Unit for a bus system, master-slave bus system with a plurality of units, and method for addressing units of a bus system

Abstract

The disclosure relates to a unit for a bus system, a master/slave bus system with such units, and a method for assigning individual unit addresses for units of a bus system, wherein through the use of an enable signal, which is relayed from unit to unit, only one unit is respectively in an allocation mode in which the unit that is respectively in the allocation mode is allocated an individual unit address so that the units of the bus system can each be allocated with the unique individual address one after the other in the sequence of their cabling.

Claims

1. A unit for a bus system having: a bus interface; a control input for receiving an input signal and a control output for sending an output signal; wherein the control input is connected to an input circuit for processing the input signal and the control output is connected to an output circuit for generating the output signal; an address memory, which is embodied to store a collective broadcast address and an individual unit address; and wherein the output circuit is embodied to generate the signal that is present at the control output from a supply voltage of the unit or from an external voltage.

2. The unit according to claim 1, wherein the unit is a slave unit of a master/slave bus system and the unit address is a slave address.

3. The unit according to claim 1, wherein the address memory is embodied to store the collective broadcast address, the individual unit address, and a collective allocation address.

4. The unit according to claim 1, wherein the input circuit, the output circuit, the control input, and the control output are separated from one another on a circuitry level and/or are connected to one another only by way of a higher-level control logic of the unit.

5. The unit according to claim 1, wherein the control input is a digital input and the input circuit is embodied to process a digital signal that is present at the control input or wherein the control input is an analog input and the input circuit is embodied to process an analog signal that is present at the control input.

6. The unit according to claim 1, wherein the control output is a digital output and the output circuit is embodied to generate a digital signal that is present at the control output or wherein the control output is an analog output and the output circuit is embodied to generate an analog signal that is present at the control output or wherein the control output is an open collector and the output circuit is embodied to generate a digital signal that is present at the control output.

7. The unit according to claim 1, further comprising a voltage output that is configured to be connected directly to the control input or also having a voltage output that is configured to be or is connected to the control input via a potentiometer or via a switch.

8. The unit according to claim 1, the unit operable to switch from an operating mode into an addressing mode upon receipt of an addressing command addressed to the broadcast address via the bus interface or upon receipt of another signal, and in the addressing mode, to generate an inhibiting signal with the output circuit and to send the inhibiting signal as an output signal at the control output, and, upon receipt of an enable signal at the control input, to switch from the addressing mode into an allocation mode, in the allocation mode, to store an address, which has been received via the bus interface, as an individual unit address in the address memory and after the storage of the unit address, to switch from the allocation mode into a wait mode, in the wait mode, to generate an enable signal with the output circuit and to send the enable signal as an output signal at the control output.

9. The unit according to claim 8, further comprising an inhibition circuit, wherein by way of the inhibition circuit, the unit is embodied so that it can be switched into the allocation mode only if the control output sends the inhibiting signal and the enable signal is present at the control input.

10. A master/slave bus system with a master and a plurality of units according to claim 1 functioning as slave units, wherein the master is connected by way of at least one bus line to the units of the plurality of units and wherein respective pairs of units of the plurality of units are connected to each other by way of a control line, which connects the control output of a first unit to the control input of a second unit so that each of the units of the plurality of units are connected to one another in series by way of the respective control lines.

11. The master/slave bus system according to the preceding claim 10, wherein the control output of a last unit of the units that are connected to one another in series is connected to the master by way of a last control line.

12. The master/slave bus system according to claim 10, wherein the master is connected by way of a first control line to the control input of a first unit of the units that are connected to one another in series.

13. A method for addressing a plurality of units, which are connected via at least one bus line to a master to form a bus system, wherein each unit of the plurality of units respectively has a bus interface for connecting to the bus line, a control input for receiving an input signal, and a control output for sending an output signal, wherein the control input is connected to an input circuit for processing the input signal and the control output is connected to an output circuit for generating the output signal, wherein each unit also has an address memory, which is embodied to store a collective broadcast address and an individual unit address, and wherein respective pairs of units of the plurality of units are connected to each other by way of a control line, which connects the control output of a first unit to the control input of a second unit so that all of the units of the plurality of units are connected to one another in series by way of the respective control lines from an initial unit to a last unit, and wherein the method comprises at least the following steps: a. Switching of the plurality of units from an operating mode into an addressing mode, wherein in the addressing mode, each of the units generate an inhibiting signal with the output circuit and send the inhibiting signal as an output signal at the control output so that the inhibiting signal is present at the control input of a next unit in the series; b. Switching of the first unit of the units that are connected in series from the addressing mode into an allocation mode by transmission of an enable signal to the control input of the initial unit in the series; c. Allocation of an address to a unit that is in the allocation mode by transmission of an address to the unit via the bus line and storage of the address as an individual unit address in the address memory; d. After the storage of the address, switching of the unit from the allocation mode into a wait mode, wherein in the wait mode, the output circuit of the unit generates a signal that is sent as an output signal in the form of an enable signal at the control output of the unit to the control input of the next unit in the series of units that are connected to one another, as a result of which the next unit in the series is switched into the allocation mode; e. Repetition of steps c. and d. for each unit until all of the units of the plurality of units are in the wait mode; f. Switching of the plurality of units from the wait mode into the operating mode.

14. The method according to claim 13, wherein in order to switch units from the operating mode into the addressing mode, a bus signal is sent by the master via the bus line to all of the units.

15. The method according to claim 13, wherein after the allocation of the address, the unit is switched into the wait mode automatically or by transmission of a bus signal from the master to the unit.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Other advantageous modifications of the disclosure are disclosed in the dependent claims and will be presented in greater detail below together with the description of the preferred embodiment of the disclosure based on the FIGURE.

(2) FIG. 1 shows an exemplary schematic depiction of a master/slave bus system.

DETAILED DESCRIPTION

(3) Each unit 20, 20′, 20″ of the master/slave bus system 1 shown in FIG. 1 respectively has a control input 22 and a control output 23. The control output 23 of the first unit 20 is connected to the control input 22 of the second unit 20′ and the control output 23 of the second unit 20′ is connected to the control input 22 of the third and in this case last unit 20″. The control output 23 of the last unit 20″ can optionally be connected via a last control line 33, which is depicted here with dashed lines and can also be referred to as a reply line, to a control input 11 of the master 10 in order to notify the master 10 of the end of the addressing procedure, which is implemented by the transmission of an enable signal from the last unit 20″ to the master 10. In addition, each of the units 20, 20′, 20″ has a higher-level control logic 21 implemented in the form of a microcontroller, which is embodied to evaluate and process the input signals that are processed by the input circuit and to control the output circuit in order to generate the output signal. Since the units 20, 20′, 20″ are provided as slaves of a master/slave bus system 1, they are also referred to as slave units or slaves.

(4) At the beginning of the method according to the disclosure, the slaves 20, 20′, 20″ are not correctly addressed or are unaddressed and all have the same, incorrect, or unknown individual unit addresses as well as a predetermined and preferably unmodifiable broadcast address.

(5) A message that is sent by the master 10 to the broadcast address is received and processed by all of the slaves 20, 20′, 20″, but does not result in a reply from the slaves 20, 20′, 20″.

(6) For the correct function of the master/slave bus system 1, each slave unit 20, 20′, 20″ must have a unit address that is unique within the bus system so that a communication request by the master 10 or a message transmitted by the master 10 via the bus line 30 is processed and replied to by only one slave 20, 20′, 20″.

(7) Accordingly, an address allocation is required that is as quick and uncomplicated as possible so that communication via the bus system can take place.

(8) First, the slaves 20, 20′, 20″ are switched from their normal operating mode into the addressing mode by means of a command addressed to the broadcast address.

(9) To start the addressing or more precisely, to start the allocation of addresses, the initial and in this case first slave 20 in the series slaves 20, 20′, 20″ that are connected to one another by means of the control line 32 is acted on at its control input 22 with an enable signal, which enables the first slave 20 in the series for the addressing.

(10) In the exemplary embodiment shown in FIG. 1, the enable signal for the first slave 20 can be transmitted from the master 10 or more precisely from a control output 12 of the master 10 to the first slave 20, for example via a first control line 31. Alternatively, the enable signal can also be a voltage signal, wherein in order to produce the voltage signal, the control input 22 is connected to the power supply 24 via a bridge 34 or via a control element that is connected between them. The power supply can be an either constant or variable power supply in the slave itself (e.g. a +10V voltage provided to power the potentiometer) or a variable power supply that can be programmed via the bus system (e.g. a 0-24V variable DC voltage) or a voltage supplied by the master 10. This enable signal can, as is depicted by means of the first control line 31, be embodied so that it can be connected for example directly to the master 10, as a result of which in a corresponding embodiment, the master 10 can initiate the start of the method.

(11) If the slaves 20, 20′, 20″ are switched into the addressing mode by a command addressed to the broadcast address, then at their control output 23, an inhibiting signal is generated, which can, for example, be a predetermined voltage between 0 and 10V.

(12) An inhibition circuit that is respectively provided in the slaves 20, 20′, 20″ results in the fact that by means of an enable signal that is present at their respective control input 22, the slaves 20, 20′, 20″ that are in the addressing mode can be switched into the allocation mode only if and so long as the inhibiting signal is being sent at their control output 23. Conversely, this results in the fact that the slave units 20, 20′, 20″ cannot respectively be switched into the allocation mode if an enable signal is being generated and sent at their respective control output 23.

(13) If the slaves 20, 20′, 20″ are in the addressing mode, then by means of an enable signal that is received at their respective control input 22, they can each be switched into the allocation mode in which an address that is received via the bus interface is stored in the respective slave.

(14) After the allocation of the new unit address, the enable signal of for example 10V is generated for next slave 20′, 20″ in the series, as a result of which this next slave is switched into the allocation mode.

(15) Optionally, the successful addressing can be controlled for example by a reading back of the slave address from the address memory of the respective slave unit 20, 20′, 20″, which in the allocation mode can be reached via the allocation address that is provided for this purpose or by means of the unit address that has been allocated to it by the bus system.

(16) If it is specified that a slave 20, 20′, 20″ that is in the allocation mode is to be addressed with a new unit address by means of a command sent to an optional allocation address, then the master 10 communicates with a slave 20, 20′, 20″ that is respectively in the allocation mode by addressing a message to the above-mentioned allocation address, which upon receipt of the command, executes the allocation of the address and replies to the master.

(17) If no other slave unit 20, 20′, 20″ is found that is enabled for the addressing or more precisely is in the allocation mode, then the addressing is concluded.

(18) Optionally, the method can be concluded when a particular number of slave units 20, 20′, 20″ that are to be addressed has been reached.

(19) Also optionally, the method can be concluded when the master 10 receives the enable signal from the control output of the last slave via the last control line 33 at a control input 11 of the master 10.

(20) If all of the slaves 20, 20′, 20″ have been allocated an address, i.e. one of the conditions for the conclusion of the method has been fulfilled, then the slaves 20, 20′, 20″ are switched from the addressing mode into their operating mode, which can be initiated by means of a message sent by the master 10 to the broadcast addresses or to the individual, newly assigned addresses.

(21) In terms of its embodiment, the disclosure is not limited to the preferred exemplary embodiments disclosed above. Instead, there are a number of conceivable variants, which make use of the solution presented, even with fundamentally different embodiments.