Low power logic circuit

Abstract

The disclosure relates to a logic circuit. The logic circuit comprises a first thin film transistor, TFT, having a gate connected to an input of the logic circuit, and a drain connected to an output of the logic circuit. The logic circuit further comprises a second TFT having a source connected to the output of the logic circuit. The logic circuit further comprises a third TFT having a gate connected to the input of the logic circuit, a source connected to the source of the second TFT, and a drain connected to a gate of the second TFT. The logic circuit further comprises a fourth TFT having a gate connected to the output of the logic circuit, and a source connected to the gate of the second TFT and the drain of the third TFT.

Claims

1. A logic circuit comprising: a first thin film transistor (TFT) having a first drain, a first gate, and a first source; a second TFT having a second drain, a second gate, and a second source; a third TFT having a third drain, a third gate, and a third source; and a fourth TFT having a fourth drain, a fourth gate, and a fourth source, wherein the second source, the fourth gate, the third source, and the first drain form a first node, wherein the fourth drain and the second drain form a second node, wherein the fourth source, the second gate, and the third drain form a third node, and wherein the third gate and the first gate form a fourth node.

2. The logic circuit according to claim 1, wherein the first source forms a fifth node with a first power supply.

3. The logic circuit according to claim 2, wherein a second power supply additionally forms the second node with the fourth drain and the second drain.

4. The logic circuit according to claim 3, wherein the first TFT is the only current path from the second power supply to the first power supply through the logic circuit.

5. The logic circuit according to claim 3, wherein the first power supply is ground and the second power supply is a positive supply voltage.

6. The logic circuit according to claim 1, wherein the first TFT has a first threshold voltage that is greater than a second threshold voltage of the second TFT.

7. The logic circuit according to claim 1, wherein the second TFT is a depletion mode transistor.

8. The logic circuit according to claim 1, wherein the first TFT is an enhancement mode transistor.

9. The logic circuit according to claim 1, wherein one or more of the first TFT, the second TFT, the third TFT, or the fourth TFT comprises a backgate.

10. The logic circuit according to claim 1, the first TFT comprising a backgate and being configured to receive an adjustment signal at the backgate.

11. The logic circuit according to claim 1, the second TFT comprising a backgate and being configured to receive an adjustment signal at the backgate.

12. The logic circuit according to claim 1, wherein the first TFT is adapted to turn on in response to receiving a logic high signal at the first gate and to turn off in response to receiving a logic low signal at the first gate.

13. The logic circuit according to claim 1, wherein the fourth TFT is adapted to provide feedback from the first node to the third node.

14. The logic circuit according to claim 1, wherein the third TFT is adapted to turn off the second TFT in response to receiving a logic high input signal at the third gate.

15. A method of operating the logic circuit of claim 1, the method comprising: providing an input signal to the fourth node; and transitioning the input signal from logic high to logic low, thereby turning on the second TFT and the fourth TFT and turning off the first TFT and the third TFT.

16. The method of claim 15, wherein transitioning the input signal from logic high to logic low comprises transitioning the input signal from logic high to logic low, thereby causing the first node to transition from logic low to logic high.

17. The method claim 15, further comprising providing a supply voltage between the first source and the second drain.

18. A method of operating the logic circuit of claim 1, the method comprising: providing an input signal to the fourth node; and transitioning the input signal from logic low to logic high, thereby turning off the second TFT and the fourth TFT and turning on the first TFT and the third TFT.

19. The method of claim 18, wherein transitioning the input signal from logic low to logic high comprises transitioning the input signal from logic low to logic high, thereby causing the first node to transition from logic high to logic low.

20. The method claim 18, further comprising providing a supply voltage between the first source and the second drain.

Description

BRIEF DESCRIPTION OF THE FIGURES

(1) The above, as well as additional, features will be better understood through the following illustrative and non-limiting detailed description of example embodiments, with reference to the appended drawings.

(2) FIG. 1 is a schematic diagram of a logic circuit, according to an example embodiment.

(3) FIG. 2a is a schematic diagram of a logic circuit operating in diode logic load mode, according to an example embodiment.

(4) FIG. 2b is a schematic diagram of a logic circuit operating in zero-V.sub.GS mode, according to an example embodiment.

(5) All the figures are schematic, not necessarily to scale, and generally only show parts which are necessary to elucidate example embodiments, wherein other parts may be omitted or merely suggested.

DETAILED DESCRIPTION

(6) Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings. That which is encompassed by the claims may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided by way of example. Furthermore, like numbers refer to the same or similar elements or components throughout.

(7) FIG. 1 illustrates a logic circuit 100 according to an embodiment of the present disclosure. The logic circuit 100 comprises a first thin film transistor (TFT) 110 which has a gate 110a connected to an input 101 of the logic circuit, and a drain 110b connected to an output 102 of the logic circuit 100. The first TFT may be referred to as a drive transistor. The logic circuit 100 comprises a second TFT 120 which has a source 120c connected to the output 102 of the logic circuit 100. The second TFT may be referred to as a load transistor. The logic circuit comprises a third TFT 130 which has a gate 130a connected to the input 101 of the logic circuit 100, a source 130c connected to the source 120c of the second TFT 120, and a drain 130b connected to a gate 120a of the second TFT 120. The logic circuit comprises a fourth TFT 140 which has a gate 140a connected to the output 102 of the logic circuit 100, and a source 140c connected to the gate 120a of the second TFT 120 and the drain 130b of the third TFT 130.

(8) The first TFT 110 has a source 110c which is connected to a first power supply rail which according to an embodiment is ground, i.e. a zero-volt potential (alternatively, the source of the first TFT 110 is connected to V.sub.DD should the logic circuit 100 be implemented by means of p-type TFTs instead of n-type TFTs as illustrated in FIG. 1). The second TFT 120 has a drain 120b and the fourth TFT 140 has a drain 140b which are connected to a second power supply rail, which according to an embodiment is a positive supply voltage V.sub.DD, such as 3 V, 5 V or 12 V in order to provide power for operation of the logic circuit.

(9) The present disclosure implements the logic circuit according to a circuit topology which can be referred to as crossover logic since it can combine the advantages of diode load logic and zero-V.sub.GS logic in real time. Diode load logic typically uses a diode-connected transistor as a load for the drive transistor. In diode load logic topology, the gate and the drain of the load transistor are shorted. If the sizes of the load and drive transistor are properly selected, a logic circuit with small delay and high speed can be achieved. However, due to the relatively high static current flowing through the load transistor, the static power consumption of diode load logic is high. In zero-V.sub.GS-load logic, the gate and source of the load transistor are shorted. Therefore, the load transistor acts as a current source at a constant V.sub.GS voltage of zero volts. In comparison with diode load logic, the static current flowing through the load transistor is much smaller (typical >2 order of magnitude) which, at the cost of a slower operational speed, provides a logic circuit with lower power consumption.

(10) The operation mechanism of the logic circuit according to the present disclosure crosses over from the high-speed operation of diode load logic to the low-power operation of zero-V.sub.GS load logic in response to the signal received at its input. With reference to FIGS. 2a and 2b, the operation of the logic circuit as an inverter will be described for a logical low input signal and a logical high input signal, respectively.

(11) When the input is a logical low signal (as indicated by V.sub.in=0), as seen in FIG. 2a, the logic circuit 200 operates like diode load logic. Due to the logical low input signal at the gate 210a and the gate 230a, the first transistor 210 and third transistor 230 are inactive (as indicated by being crossed-out in FIG. 2a) save a possible small leakage current, and the output is pulled high by the second transistor 220 (the load transistor). The static power consumption is determined by the leakage current of the first transistor 210. Therefore, the first transistor 210 can be designed with a high (positive) threshold voltage V.sub.T, which results in a very small static power consumption of the logic circuit 200. Since the output signal is fed back to the second transistor 220 via the fourth transistor 240, the pull-up is strong and the speed is high, because the gate 220a of the second transistor 220 is connected to the positive power supply via the low-impedance channel of the fourth transistor 240, which is active.

(12) When the input is a logical high signal (as indicated by V.sub.in=1), as seen in FIG. 2b, the logic circuit 200 operates like zero-V.sub.GS logic. The first transistor 210 (the drive transistor) receives the high input signal at the gate 210a and is hence active, which provides a strong pull down resulting in high speed, thereby generating a logical low signal at the output of the logic circuit 200. The logical high input signal is also provided to the gate 230a of the third transistor 230, which renders the third transistor 230 active thereby providing a low-impedance path between the drain 230b and the source 230c. The gate 220a of the second transistor 220 (acting as load) is hence connected to the source 220c via the third transistor 230, which renders the second transistor 220 inactive in the sense that only a small zero-V.sub.GS current, depending on the threshold voltage V.sub.T, is flowing through the transistor (as indicated by being crossed-out in FIG. 2b). The second transistor 220 acts as a high-impedance block between the supply rail and the drain 210b of the first transistor 210. The fourth transistor 240 receives the logical low output signal at its gate 240a and is hence inactive (as indicated by being crossed-out in FIG. 2b). The fourth transistor 240 acts as a high-impedance block between the supply rail and the drain 230b of the third transistor 230, thereby preventing a current from flowing from the positive rail via the fourth, third, and first transistors to ground. Since the pull-down by the first transistor 210 is very strong, the power consumption is determined by the small zero-V.sub.GS leakage current of the second transistor 220. Thus, the static power consumption of the logic circuit 200 is very small.

(13) As can be understood from the discussion above, a benefit of the crossover logic is that all current flowing through the logic circuit flows through the first transistor 210. There are hence no separate branches (for biasing purposes) allowing current to flow from the positive supply rail to ground. This will effectively reduce the static power consumption since the current through the circuit is basically cut off when the input receives a logical low signal rendering the first transistor inactive (except for a possible small leakage current flowing through the first transistor 210). Likewise, due to the feedback from the output to the fourth transistor 240, and the connection of the third transistor 230, the current flowing through the logic circuit is basically cut off when the input receives a logical high signal (except for a small zero-V.sub.GS current flowing through the second transistor 220).

(14) Switching between diode load and zero-V.sub.GS load is done by a resistive divider made by the third transistor 230 and the fourth transistor 240. When the input is a logical low signal as seen in FIG. 2a, the output is a logical high signal, and the fourth transistor 240 is rendered active via the feedback from the output to the gate 240a of the fourth transistor 240. The third transistor 230 receives the logical low input signal at its gate 230a and is inactive. Seen as a resistive divider, the third transistor 230, which is inactive, presents an impedance between its drain 230b and source 230c that is much higher than the impedance seen between the drain 240b and source 240c of the fourth transistor 240, which is active. Thus, the gate 220a of the second transistor 220 is virtually connected to the supply through the fourth transistor 240 while the third transistor 230 is inactive and does not pull down the gate potential at the second transistor 220.

(15) When the input is a logical high signal as seen in FIG. 2b, the output is a logical low signal, and the fourth transistor 240 is rendered inactive via the feedback from the output to the gate 240a of the fourth transistor 240. The third transistor 230 receives the logical high input signal at its gate 230a and is active. Seen as a resistive divider, the third transistor 230, which is active, presents an impedance between its drain 230b and source 230c that is much lower than the impedance seen between the drain 240b and source 240c of the fourth transistor 240, which is inactive. Thus, the gate 220a of the second transistor 220 is virtually connected to the source 220c of the second transistor (and the output) through the third transistor 230, enabling zero-V.sub.GS operation, while the fourth transistor 240 is inactive and does not pull up the gate potential at the second transistor 220.

(16) When the input signal changes from a logical high signal to a logical low signal (i.e., from 1 to 0) the output is initially at a logical low signal level which is fed back to the gate 240a of the fourth transistor 240, rendering it inactive. This means that the second transistor 220 is in high-impedance mode (zero-V.sub.GS mode) since the fourth transistor 240 is not able to increase the gate-source voltage, V.sub.GS, of the second transistor 220. In order for the logical circuit 200 to switch states, a leakage current through the second transistor 220 has to recharge the output until the feedback flips the operation mode of the second transistor 220 (i.e. from zero-V.sub.GS-load to diode load). Therefore, there is a trade-off between speed and power consumption, set by the leakage current of the second transistor 220, which is set by its threshold voltage V.sub.T. A higher off-current can recharge the output node more rapidly, but also leaks more when the input is high, thereby increasing the static power consumption.

(17) The fourth transistor 240 and the third transistor 230 can be minimized to gain area, since they generally only need to charge the gate capacitance of the second transistor 220.

(18) In conclusion, a new topology for thin-film technology with low power consumption, crossover logic, has been disclosed. The topology uses elements from diode load logic and zero-V.sub.GS logic, to combine the speed of diode load logic with the low static power properties of zero-V.sub.GS logic. By way of example, with respect to diode load logic with backgate, the static noise margin has been measured to increase from 0.475 V to 1.572 V for a 5V supply. Additionally, the power consumption has been measured to be reduced by a factor 5, while the decrease in speed is limited to a factor of 2.1. The new logic style is also fully compatible with diode load logic.

(19) While some embodiments have been illustrated and described in detail in the appended drawings and the foregoing description, such illustration and description are to be considered illustrative and not restrictive. Other variations to the disclosed embodiments can be understood and effected in practicing the claims, from a study of the drawings, the disclosure, and the appended claims. The mere fact that certain measures or features are recited in mutually different dependent claims does not indicate that a combination of these measures or features cannot be used. Any reference signs in the claims should not be construed as limiting the scope.