Layered vertical field effect transistor and methods of fabrication

Abstract

A III-nitride vertical field effect transistor comprises a base plate; a mask layer overlaying said base plate and having opening windows for partial exposure of said base plate; a drain grown epitaxially onto regions of said base plate exposed by the opening windows of said mask layer; an insulation layer grown epitaxially onto said drain; a source grown epitaxially onto said insulation layer; a vertical nitride stack grown epitaxially onto the side faces of said drain, said insulation layer and said source, overlaying said mask layer and providing at least one vertical conducting channel to connect said source to said drain; a current flowing from said source to said drain through a conducting channel can be modulated by an electrical voltage that is applied to the side face of said vertical nitride stack. There are preferably also electrodes and edge terms.

Claims

1. A III-nitride vertical field effect transistor comprising: a base plate; a mask layer overlaying said base plate and having opening windows for partial exposure of said base plate, said mask layer having a top surface; a drain grown epitaxially from the opening windows of said mask layer onto said base plate, said drain having a top surface and a side face; an insulation layer grown epitaxially onto said drain top surface, said insulation layer having a top surface and a side face; a source grown epitaxially onto said insulation layer top surface, said source having a top surface and a side face; a vertical nitride stack grown epitaxially onto the side face of said drain, said insulation layer and said source, such that the stack overlies said mask layer, the stack providing a conducting channel connecting said source and said drain, wherein said conducting channel terminates on said top surface of said mask layer; and a source electrode, a drain electrode and a gate electrode are in contact or in series with said source, said drain and said vertical nitride stack, respectively.

2. The vertical field effect transistor according to claim 1, wherein the drain at least partially overlies the mask layer.

3. The vertical field effect transistor according to claim 1, wherein said mask layer comprises at least one of SiO.sub.2, Si.sub.xN, spin-on-glass, spin-on-dielectric, Ti, W, carbon and flowable oxide.

4. The vertical field effect transistor according to claim 1, wherein said drain comprises at least one of In.sub.yAl.sub.xGa.sub.1-x-yN where 0y0.4 and 0x0.4 with a n-type doping concentration of 110.sup.17 cm.sup.3 to 310.sup.20 cm.sup.3.

5. The vertical field effect transistor according to claim 1, wherein said insulation layer comprises at least one of In.sub.yAl.sub.xGa.sub.1-x-yN where 0y0.2 and 0x1, and has a thickness of 300 nm to 30 m.

6. The vertical field effect transistor according to claim 1, wherein said source comprises at least one of In.sub.yAl.sub.xGa.sub.1-x-yN, where 0y0.4, 0x0.4, with a n-type doping concentration of 110.sup.17 cm.sup.3 to 310.sup.20 cm.sup.3.

7. The vertical field effect transistor according to claim 1, wherein said vertical nitride stack comprises at least one layer of n-type where 0x0.4 as a conducting channel, which has a thickness of 20 nm to 300 nm, and a n-type doping concentration of 110.sup.15 cm.sup.3 to 110.sup.20 cm.sup.3.

8. The vertical field effect transistor according to claim 1, wherein said vertical nitride stack provides at least one vertical 2-dimensional electron gas conducting channel by comprising at least one layer of In.sub.yAl.sub.xGa.sub.1-x-yN where 0y0.4, 0x1, which is between 0.5 nm to 100 nm in thickness, when said drain, said insulation layer and said source comprises non-polar nitride layers.

9. The vertical field effect transistor according to claim 1, said drain electrode is on top side of said base plate.

10. The vertical field effect transistor according to claim 1, said drain electrode is on back side of said base plate.

11. The vertical field effect transistor according to claim 1, the vertical location of said gate electrode is below the boundary between said source and said insulation layer, and above the boundary between said insulation layer and said drain.

Description

4. BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 schematically shows across-section of a III-nitride vertical field effect transistor in accordance with an embodiment of the present invention, comprising: base plate (1); mask layer (2); drain (3); insulation layer (4); source (5); vertical nitride stack (6); drain electrode (7); gate electrode (8); edge terms (9); source electrode (10). (Arrows indicate electron flow direction).

(2) FIG. 2 schematically shows a process for forming a double width growth mask that allows ELOG growth to occur within it: base plate (1); bottom mask layer (2); top mask layer (3) and III-nitride (4), which is grown laterally onto the bottom mask layer but confined and protected by the top mask layer to avoid cross-deposition.

(3) FIG. 3 schematically shows a process for forming a mask that allows ELOG growth to occur within it: base plate (1); negative photoresist (2); mask layer (3); and III-nitride with overgrown III-nitride (4).

(4) FIG. 4 schematically shows a process for forming a narrow gate electrode: base plate (1); drain (2); insulation layer (3); source (4); vertical nitride stack (5); mask layer (6); negative photoresist (7); first control layer (8); gate electrode (9); second control layer (10).

(5) FIG. 5 schematically shows a cross-section view of a VFET in accordance with an embodiment of the present invention, having a Mg-doped, semi-insulating GaN as an insulation layer, which comprises: non-polar Si:GaN (1) as base plate; Si:GaN (2) as drain; semi-insulating Mg-doped semi-insulating GaN (3) as insulation layer; Si:GaN (4) as source; GaN/AlN/Al.sub.0.23Ga.sub.0.77N (5) as vertical III-nitride stack; dielectric layer Si.sub.3N.sub.4 (6) as mask layer; drain electrode (7); gate electrode (8); edge terms (9); source electrode (10).

(6) FIG. 6 shows a flow chart showing a formation process for a VFET with a Mg-doped semi-insulating GaN as an insulation layer: non-polar Si:GaN (1) as base plate; Si:GaN (2) as drain; semi-insulating Mg-doped GaN (3) insulation layer; Si:GaN (4) as source; GaN/AlN/Al.sub.0.25Ga.sub.0.75N (5) as vertical nitride stack. Si.sub.3N.sub.4 (6) and SiO.sub.2 (6a) as mask layer; drain electrode (7); gate electrode (8); edge terms (9); source electrode (10).

(7) FIG. 7 schematically shows a VFET in accordance with an embodiment of the present invention that has a 2DEG conducting channel on N-face and a layer of Al.sub.0.25Ga.sub.0.75N as an insulation layer: Si:GaN (1) on R-plane sapphire substrate (1a) as base plate; Si:GaN (2) and Si:Al.sub.0.15Ga.sub.0.85N (2a) as drain; Al.sub.0.25Ga.sub.0.75N (3) as insulation layer; Si:Al.sub.0.15Ga.sub.0.85N (4a) and Si:GaN (4) as source; Al.sub.0.25Ga.sub.0.75N (3 nm)/AlN (1 nm)/GaN (30 nm) (5) as vertical III-nitride stack; SiO.sub.2 (6) as insulation layer; drain electrode (7); gate electrode (8); edge terms (9); source electrode (10).

5. DESCRIPTION OF THE EMBODIMENTS

(8) 1. Case 1

(9) I) FIG. 5 schematically shows the cross-section of a device that comprises:

(10) a non-polar (11-20) Si:GaN free-standing (FS) substrate (0.4 mm thick) that acts a base plate with its +C direction (i.e. [0001]) parallel its top polished surface; since such a template is expensive, non-polar III-nitride templates grown by MOVPE or MBE on a number of foreign substrates such as Si, Sapphire, SiC etc can also be used. Although there is a high density of defects in the nitride layers, the defects cannot penetrate a conducting channel with the methods provided by this invention. Hence, the electron mobility of the conducting channel is guaranteed. C-plane nitrides, either FS substrates or templates grown on foreign substrates, may also be used; but 2DEG is not available and n-type doped InGaN can be used for the vertical nitride stack as alternative conducting channels;

(11) a mask layer consisting of a high-temperature Si.sub.3N.sub.4 layer (400 nm) and has strip-shaped opening windows of 50 m along [0001] and 250 m along [1-100] ([1-100] is normal to the cross-section) to define the bottom size of the drain and to separate the gate region from the base; Other mask materials prepared at a lower temperature (<600 C.) such as SiO.sub.2, Si.sub.xN, spin-on-glass, spin-on-dielectric, Ti, carbon, W, and flowable oxide are easy to make to be used as a mask layer. They have a high etching rate in a HF solution; but this issue has been addressed by providing two methods (FIGS. 2 and 3) for the fabrication of double-width masks to accommodate the possible device growth processes. The opening windows can be as long as the dimension of the base plate, and in this case, device fabrication involves an isolation process to divide a long strip into individual devices. For non-polar and C-plane templates, the opening windows are oriented so that the resulting side face can have a high growth rate;

(12) a drain consisting of a layer of Si:GaN (1.5 m, doping concentration: 210.sup.+18 cm.sup.3) that has ELOG-grown Si:GaN on Ga-face side (1 m); Si:Al.sub.xGa.sub.1-xN (0x0.4) may also be used as a replacement; but Si:In.sub.xGa.sub.1-xN is advantageous since it is more conductive than Si:GaN and Si:Al.sub.xGa.sub.1-xN;

(13) an insulation layer that consists of a Mg-doped semi-insulating GaN layer (4 m, resistivity: 10.sup.+7 .Math.cm, Mg-doping concentration: 6-910.sup.17 cm.sup.3) grown on the Si:GaN drain layer; Unintentionally-doped (UID) GaN can also be used as an insulation layer. Although it is not so resistive as Mg:GaN, avoided is the potential Mg diffusion into a conducting channel that could reduce the electron mobility. Further, Al.sub.xGa.sub.1-xN (0x0.4) may also be used as a replacement, provided that a UID GaN layer in a vertical nitride stack, which will grow onto the side face of the insulation layer, is fully relaxed;

(14) a Si:GaN layer (2 m) on top of the insulation layer as source; It can has the same alternatives as the drain; but it tope surface may be finished with a 10 nm highly-doped Si:GaN (510.sup.+19 cm.sup.3) to reduce the metal-GaN contact resistance; and

(15) a vertical nitride stack that consists of a UID GaN layer (30 nm) to optimise the Ga-faces (i.e. side face) of the drain, the insulation layer and the source, a layer of AlN (1 nm) and an Al.sub.0.25Ga.sub.0.75N layer (30 nm) barrier layer. So, a 2DEG conducting channel is formed at the interface between the UID GaN and the barrier layer. The UID GaN may be replaced with Si:GaN (210.sup.+18 cm.sup.3) to reduce the serial resistance between the conducting channel and the drain and that between the conducting channel and the source. Instead of a 2DEG conducting channel, Si:In.sub.xGa.sub.1-xN can also be used as a conducting channel.

(16) There are also associated parts such as edge terms that consists of SiO.sub.2, and all the necessary electrodes that include a drain electrode on the base plate, a source electrode on top of the source and a gate electrode (or a gate) on the vertical nitride stack.

(17) This device operates like this: When a high voltage is applied between the source and the drain, electrons can be driven to flow from the source to the drain through the 2DEG conductive channel that is filled with electrons. So, it is a normally-on transistor. In order to turn the transistor off, a negative voltage (8 V) is needed to apply to the gate or the vertical nitride stack to deplete the electrons in the conductive channel and consequently, the electrons from the source cannot reach the drain. So, it behaves as a switch controlled by a voltage.

(18) But it can become a normally-off device when the insulation layer consists of AlN (5 nm)/Mg:GaN (300 nm, doping concentration: 410.sup.+19 cm.sup.3)/AlN (5 nm). The Mg:GaN depletes the 2DEG gas at the interface locally. In this case, a positive voltage is needed to apply onto the Mg:GaN layer to turn on the transistor.

(19) II) A formation process for such a structure is illustrated in FIG. 6:

(20) 1) Providing a FS Si:GaN non-polar (11-20) wafer (Si doping concentration: >810.sup.17 cm.sup.3). Since it is conductive, one side of the wafer can be used for electrode formation and the other side is used for the formation of device structure. Since FS wafers are expensive, a template consisting of non-polar (11-20) Si:GaN layer (2.0 m) grown on a (1102) sapphire substrate may be used and in such a case, the drain electrode and the device are on the same side of the template.

(21) 2) Depositing a high-temperature dielectric Si.sub.3N.sub.4 layer of 400 nm on the wafer in a MOVPE reactor, followed by a SiO.sub.2 layer of 5 m with electron beam evaporation. These materials have good adhesion to GaN surface and are often stress free. But the former has a smaller etching rate in a BOE (buffer-oxide-etching, mixture of HF and NH.sub.4F) solution.

(22) 3) Opening rectangular opening windows (50 m250 m) with ICP (Inductively Coupled Plasma) etching to expose the Si:GaN substrate surface. This process also involves fabrication of a Cr etching mask (200 nm thick) with a lift-off process. Finally, the template is dipped into a BOE solution to etch the SiO.sub.2 layer laterally by 300 nm whilst the Si.sub.3N.sub.4 is hardly etched, as shown in FIG. 2. So, a double width growth mask is formed.

(23) 4) Inside opening windows, first growing Si:GaN as the drain with ELOG growth conditions (i.e. high-temperature, low-pressure and a high ammonia flow) to make sure that its side Ga-face is confined by the double width mask, then grow Mg-lightly-doped GaN as the insulation layer and part of the source (Si:GaN), and finally grow the rest of the source vertically above the mask layer using vertical growth conditions such as relatively low ammonia flow, a relatively high pressure and a relatively low temperature. The source and the drain are doped with Si (410.sup.+18 cm.sup.3). The insulation layer is doped lightly with Mg (610.sup.+17 cm.sup.3) to neutralize the background electrons to form a semi-insulating III-nitride and other dopants such as C or/and Fe may also be used.

(24) 5) Dissolving the SiO.sub.2 in a HF:NHF.sub.3:H.sub.2O buffer-oxide-etching (BOE) solution to expose the side faces of the drain, the source and the insulation layer, and most of the Si.sub.3N.sub.4 layer remains due to the etching selectivity between electron-beam-evaporated SiO.sub.2 and high-temperature Si.sub.3N.sub.4. This process can also be carried out with ICP etching. The remaining Si.sub.3N.sub.4 layer is used not only as a growth mask for the growth of the vertical nitride stack but also as the insulation layer between a gate electrode and the drain.

(25) 6) Treating the side faces of the insulation layer, the source and the drain in an ICP etcher at 120 C. with a Cl2 gas purge to remove Si contaminated surface layer.

(26) 7) Growing a GaN buffer layer (30 nm) on the Ga-face with ELOG growth conditions to optimise the electron mobility in the channel, followed by depositing a layer of AlN (1 nm) and an Al.sub.0.25Ga.sub.0.75N barrier layer (30 nm). The GaN layer cannot be thick since it will increase the serial resistance. So, a 2DEG of free electrons and a 2DEG conducting channel are formed. There will be some deposition on the top of the source during this process, but it can be etched away with ICP etching during forming electrodes and edge terms.

(27) 8) Device fabrication: The process, in general, comprises: a) mesa and isolation formation with ICP etching and filling the gap with SiO.sub.2 to establish individual device region; b) edge term etching and filling up with SiO.sub.2; c) Spin-coating of negative photoresist, exposing the gate side face and the insulation layer, and depositing a gate electrode; In order to reduce the possible gate leakage current, a layer of SiO.sub.2 layer may be deposited onto the side face of the vertical nitride stack with electron beam evaporation before a gate electrode is deposited. d) forming a source electrode; e) forming a drain electrode.

(28) 9) Packaging: This may comprise a process of clamping or depositing heat conductive materials such as Cu, diamond etc, to extract the heat.

(29) 2. Case 2

(30) 1) FIG. 7 schematically shows the cross-section of another embodiment that has an AlGaN layer as an insulation layer due to its wide band-gap and high resistivity and a vertical nitride stack on the N-face. In detail, it comprises:

(31) a base plate comprising a non-polar (11-20) Si:GaN layer (4.5 m, doping concentration: 410.sup.+18 cm.sup.3), which is grown by MOVPE on a R-plane sapphire substrate; In order to form an ohmic contact for the drain electrode, the top surface of the Si:GaN layer may be highly doped (410.sup.+19 cm.sup.3);

(32) a drain (bottom size: 50 m250 m) comprising a Si:GaN layer of 1 m and a Si:Al.sub.0.15Ga.sub.0.85N layer (0.3 m, doping concentration: 810.sup.+18 cm.sup.3), which have overgrown GaN and AlGaN (200 nm) on the N-face side;

(33) an Al.sub.0.25Ga.sub.0.75N layer (3.5 m) as an insulation layer;

(34) a source comprising a Si:Al.sub.0.15Ga.sub.0.85N layer (0.2 m) and a Si:GaN layer (2.0 m) on top of the insulation layer;

(35) a vertical nitride stack comprising an Al.sub.0.25Ga.sub.0.75N of 3 nm, an AlN layer of 1 nm and a channel layer of GaN (30 nm) on the N-face; 6) a SiO.sub.2 layer (1 m) to separate the gate layer from the base.

(36) There are also edge terms that consist of SiO.sub.2, all the necessary electrodes. So, inside vertical nitride stack, there is a conducting channel between the Al.sub.0.25Ga.sub.0.75N layer and the GaN channel layer, extending to both the source and the drain by using two Si:Al.sub.0.15Ga.sub.0.85N layers, respectively, to eliminate the hotspots.

(37) This device operates like this: when a high voltage is applied between the source and the drain, electrons flow from Si:GaN of the source to Si:Al.sub.0.15Ga.sub.0.85N of the source, to the 2DEG conducting channel, to the Si:Al.sub.0.15Ga.sub.0.85N of the drain and finally to Si:GaN of the drain. To turn off the device, a negative voltage is applied to push electrons towards the AlGaN insulation layer. So, it behaves as a switch that is controlled by a voltage.

(38) But it can become a normally-off device when the insulation layer consists of AlN (5 nm)/Mg:Al.sub.0.25Ga.sub.0.75N (300 nm, doping concentration: 410.sup.+19 cm.sup.3)/AlN (5 nm). The Mg:Al.sub.0.25Ga.sub.0.75N depletes the 2DEG gas at the interface locally. In this case, a positive voltage is needed to apply onto the Mg:Al.sub.0.25Ga.sub.0.75N layer to turn on the transistor.

(39) A process for forming the device comprising:

(40) 1) Providing a base plate that comprises a layer of (11-20) Si:GaN (4 m, doping concentration: 410.sup.+18 cm.sup.3) grown on a R-plane sapphire substrate.

(41) 2) Forming a double-width mask layer with opening windows (50 m250 m). The longest edge of the windows is oriented 4 away from the (1-100) direction. The double width growth mask is formed with these procedures: i) spin-coating a layer of negative photoresist (8.0 m) and exposing the region with photolithography where the SiO.sub.2 will be deposited; ii) etching into the Si:GaN layer by a depth of 1 m with ICP etching and the negative photoresist as the etching mask; iii) depositing SiO.sub.2 (7.0 m) with electron beam evaporation; iv) conducting a lift-off process to expose the intact (11-20) template surface for further growth of the drain; and v) dipping the sample into a solution BOE (2o:1) for 4 minutes so that the opening windows are enlarged by 300 nm on all sides. Finally, the sample is loaded into an electron beam evaporator so that 90% of the side wall of the mask faces a tungsten (W) source crucible whilst the surface of the base plate is shaded, and a layer of W (50 nm) is deposited.

(42) 3) Growing a layer of Si:GaN (0.5 m) and a layer of Si:Al.sub.0.15Ga.sub.0.85N (0.5 m) to complete drain with an ELOG process, i.e. it grows both vertically along [11-20] and horizontally along C (i.e. [000-1], normal to N-face) by employing such conditions as a relatively high growth temperature, a relatively low reactor pressure and a relatively high ammonia flow (which depend on model of MOVPE reactor).

(43) 4) Growing the Al.sub.0.25Ga.sub.0.75N insulation layer (3.5 m) and the Si:Al.sub.0.15Ga.sub.0.85N (200 nm) of the source inside the double width mask layer with ELOG growth conditions.

(44) 5) Growing a Si:GaN vertically to complete the drain. The growth conditions include a relatively low growth temperature, a relatively high reactor pressure and a relatively low ammonia flow.

(45) 6) Dipping the as-grown sample into a solution BOE (5:1) to reduce the thickness of growth (SiO2) to 1 m.

(46) 7) Growing an Al.sub.0.25Ga.sub.0.75N of 3 nm, an AlN layer of 1 nm on the N-face and a GaN layer (30 nm) onto the N-face to complete the structures.

(47) 8) Fabricating devices with a common process.

(48) 3. Case 3

(49) A narrow gate electrode (800 nm) can be easily made, as illustrated in FIG. 4 whilst the control layers are SiO.sub.2 and the gate electrode is Ni/Au. The process comprises:

(50) i. providing an as-grown device structure which is shown in FIG. 7;

(51) ii. depositing a SiO.sub.2 layer as a first control layer on the gate side by: I) covering the device structure with negative photoresist; 2) exposing the N-face that has the vertical nitride stack with a photolithographic process; iii) deposing SiO.sub.2 (3 m thick) with electron beam evaporation. During the evaporation, the mask layer (hereafter the horizontal surface) faces directly toward a SiO.sub.2 source crucible. So the SiO.sub.2 layer that is deposited on the horizontal surface is much thicker than the layer of SiO.sub.2 (<200 nm) that is deposited on the N-face face of vertical nitride stack (the vertical surface);

(52) iii. removing the SiO.sub.2 on the vertical surface in a 10:1 BOE solution by controlling etching time (a few minutes). The SiO.sub.2 layer on the horizontal surface is also etched with a similar thickness, but it could be 2.5 m. This layer controls the distance from the gate edge to the drain;

(53) iv. depositing a gate electrode (such as Ni (20 nm)/Au (100 nm)) in a multi-crucible electron beam evaporator. During evaporation, the sample is tilted so that both the vertical surface and the horizontal surface face the crucibles at angles of 45. Consequently, the metal layer on the horizontal surface is nearly equivalent to what is on the vertical surface.

(54) v. repeat step 2 except that the thickness of SiO2 is reduced by a half;

(55) vi. exposing the top part of the gate electrode with ICP etching when the sample is tilted by an angle of 15 not only to remove the SiO.sub.2 on the vertical surface, but also to thin the SiO.sub.2 on the horizontal surface to 800 nm;

(56) vii. removing the exposed electrode in an aqua regia solution; and

(57) viii. removing the photoresist, as well as the SiO.sub.2 and metals on top of the device through a so-called lift-off process.