METHOD FOR FORMING A TRANSITION METAL DICHALCOGENIDE - GROUP III-V HETEROSTRUCTURE AND A TUNNELING FIELD EFFECT TRANSISTOR

Abstract

A method for forming a Transition Metal Dichalcogenide (TMD)Group III-V semiconductor heterostructure comprises forming an insulating layer on an upper surface of a substrate, wherein the upper surface of the substrate is formed by a (111)-surface of a group IV semiconductor, forming a first aperture in the insulating layer, the aperture exposing a portion of the upper surface of the substrate, forming in a first epitaxial growth process, a semiconductor structure formed by a group III-V semiconductor comprising a pillar extending through the first aperture and a micro disc extending horizontally along a first portion of the upper surface of the insulating layer, and forming in a second epitaxial growth process, a TMD layer on an upper surface of the micro disc.

Claims

1. A method for forming a transition metal dichalcogenidegroup III-V semiconductor heterostructure, comprising: forming an insulating layer on an upper surface of a substrate, wherein the upper surface of the substrate is a (111)-surface of a group IV semiconductor; forming a first aperture in the insulating layer, the aperture exposing a portion of the upper surface of the substrate; forming, in a first epitaxial growth process, a semiconductor structure of a group III-V semiconductor comprising a pillar extending through the first aperture and a micro disc extending horizontally along a first portion of an upper surface of the insulating layer; and forming, in a second epitaxial growth process, a transition metal dichalcogenide layer on an upper surface of the micro disc, whereby a transition metal dichalcogenidegroup III-V semiconductor heterostructure is obtained.

2. The method of claim 1, further comprising, prior to the second epitaxial growth process: forming a first layer on a second portion of the upper surface of the insulating layer, whereby a side surface of the micro disc is covered.

3. The method of claim 2, further comprising, prior to the second epitaxial growth process: passivating the upper surface of the micro disc using a material selected from the group consisting of S, Se, Te, and combinations thereof, whereby a passivated upper surface of the micro disc is obtained.

4. The method of claim 3, wherein the first epitaxial growth process is adapted such that a growth rate in a horizontal plane is greater than a growth rate in a vertical direction during a part of the first epitaxial growth process in which the micro disc is grown.

5. The method of claim 3, further comprising: masking an upper surface of the transition metal dichalcogenide layer; forming a second aperture extending through the first layer, the second aperture exposing a side surface of the micro disc; forming, in a third epitaxial growth process, a laterally extended portion of the micro disc in the second aperture; forming a third aperture extending through the first layer, the third aperture exposing another side surface of the micro disc; recessing, from the third aperture, a portion of the micro disc to form a protruding portion of the transition metal dichalcogenide layer from the passivated upper surface of the micro disc; forming a gate insulating layer in contact with the passivated upper surface; forming a gate contact on the gate insulating layer; forming a source contact in contact with the laterally extended portion of the micro disc; and forming a drain contact in contact with the protruding portion of the of the transition metal dichalcogenide layer, whereby a tunneling field effect transistor is obtained.

6. The method of claim 5, wherein the laterally extended portion of the micro disc is epitaxially grown such that the growth rate in a horizontal plane is greater than a growth rate in a vertical direction.

7. The method of claim 5, wherein the laterally extended portion of the micro disc is doped.

8. The method of claim 5, wherein the first layer comprises a lower layer of a first material and an upper layer of a second material, wherein the second aperture is formed by forming an opening extending through an upper layer of the first layer of material, and selectively etching, from the opening, the lower layer to form a recess extending to the side surface of the micro disc.

9. The method of claim 8, wherein the first material is an amorphous material.

10. The method of claim 5, wherein the transition metal dichalcogenide layer comprises a material selected from the group consisting of WSe.sub.2, WS.sub.2, WTe.sub.2, MoS.sub.2, MoSe.sub.2, MoTe.sub.2, HfS.sub.2, HfSe.sub.2, HfTe.sub.2, ZrS.sub.2, ZrSe.sub.2, ZrTe.sub.2, and combinations thereof.

11. A tunnel field effect transistor device, comprising: a substrate, wherein an upper surface of the substrate is a (111)-surface group IV semiconductor material; an insulating layer arranged in contact with an upper surface of the substrate; a group III-V semiconductor structure comprising a pillar extending through the insulating layer and abutting the upper surface of the substrate and a micro disc arranged in contact with an upper surface of the insulating layer; a transition metal dichalcogenide layer arranged in contact with an upper surface of a first portion of the micro disc; a gate oxide layer arranged in contact with an upper surface of a first portion of the transition metal dichalcogenide layer; a gate contact arranged in contact with an upper surface of the gate oxide layer; a source contact arranged in contact with an upper surface of a second portion of the micro disc, wherein the second portion of the micro disc is doped; and a drain contact arranged in contact with an upper surface of a second portion of the transition metal dichalcogenide layer.

12. The tunnel field effect transistor device of claim 11, wherein the transition metal dichalcogenide layer comprises a material selected from the group consisting of WSe.sub.2, WS.sub.2, WTe.sub.2, MoS.sub.2, MoSe.sub.2, MoTe.sub.2, HfS.sub.2, HfSe.sub.2, HfTe.sub.2, ZrS.sub.2, ZrSe.sub.2, ZrTe.sub.2, and combinations thereof.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The above, as well as additional objects, features and advantages of the embodiments, will be better understood through the following illustrative and non-limiting detailed description, with reference to the appended drawings. In the drawings like reference numerals will be used for like elements unless stated otherwise.

[0034] FIGS. 1A, 1B, 2A, 2B, 3A, 3B, 4A, 4B, 5A, 5B, 6A, 6B, 7A, 7B, 8A, 8B, 9A, 9B, 10A, 10B, 11A, and 11B schematically illustrate a method for forming a TMDIII-V semiconductor heterostructure.

[0035] FIGS. 12A, 12B, 13A, 13B, 14A, 14B, 15A, 15B, 16A, 16B, 17A, 17B, 18A, 18B, 19A, 19B, 20A, 20B, 21A, 21B, 22A, 22B, 23A, 23B, 24A, 24B, 25A, 25B, 26A, 26B, 27A, 27B, 28A, and 28B schematically illustrate a method for a TFET device after forming a TMDIII-V semiconductor heterostructure as described in the previous figures.

DETAILED DESCRIPTION

[0036] A method for forming a TMDIII-V heterostructure and a TFET device including such heterostructure will now be disclosed in connection with the figures. Each one of the figures shows a cross-sectional side view (figure number followed by A) of the structure and a top down view (figure number followed by B). The cross-sectional view in figure A is taken along the geometrical line indicated in the correspondingly numbered figure B (i.e. line AA). In the figures the axis Z denotes a vertical direction, corresponding to a normal direction with respect to an upper surface 100a of a substrate 100. The axes X and Y refer to mutually orthogonal first and second horizontal directions, i.e. directions being parallel to the main plane of extension of the substrate 100 (or correspondingly the upper surface 100a thereof). It should be noted that the relative dimensions of the shown elements, such as the relative thickness of the layers of structures, is merely schematic and may, for the purpose of illustrational clarity, differ from a physical structure.

[0037] FIGS. 1A, 1B illustrate a semiconductor substrate 100. The semiconductor substrate 100 may be single material substrate or be formed of a combination of different materials, such as of various layers stacked on top of each other. In any case at least an upper surface 100a of the substrate 100 is formed of an elemental group IV semiconductor or compound group IV semiconductor. The upper surface may be formed by a [111] face of silicon (Si). Possible substrate 100 structures include a Si substrate or a silicon-on-insulator (SOI) substrate. The upper surface 100a of the substrate 100 may be referred to as a front side surface of the substrate 100.

[0038] In FIGS. 2A, 2B a pillar 102 has been formed on the upper surface 100a of the substrate 100. The pillar 102 may be formed by masking a portion of the upper surface 100a of the substrate 100 and etching a portion of an unmasked portion of the substrate 100. The etching process may be formed by wet etching or dry etching.

[0039] In FIGS. 3A, 3B an insulating layer 104 has been formed on the upper surface 100a of the substrate 100. The insulating layer 104 covers the upper surface 100a. The insulating layer 102 may be an oxide layer such as SiO.sub.2. The insulating layer 104 may also be a dielectric layer of for instance a high-K dielectric material such as aluminum oxide or some other CMOS compatible gate dielectric. The insulating layer 104 may be deposited on the surface 100a by any suitable and conventional deposition technique, such as chemical vapor deposition (CVD) or atomic layer deposition (ALD), or by thermal oxidation. The insulating layer may be etched back to expose an upper surface 102a of the pillar 102. The etching process may be performed by wet or dry etching processes such as plasma etching. The etching may also be performed by chemical mechanical polishing of the upper surface of the insulating layer 104.

[0040] In FIGS. 4A, 4B the pillar 102 has been etched forming a first aperture 106 in the insulating layer 104. As indicated in FIGS. 4A, 4B a bottom surface of the first aperture 106 exposes the upper surface 100a of the substrate 100. The first aperture has been formed by e.g. using the insulating layer 104 as a mask. Any conventional wet or dry etching process allowing etching of the Si pillar 102 may be employed such as tetramethylammonium hydroxide (TMAH) etching. The first aperture 106 may by way of example be formed with a dimension in the range of 20-100 nm.

[0041] In FIGS. 5A, 5B, a semiconductor structure 108 has been formed in an epitaxial growth process to include a group III-V semiconductor pillar 110 and a group III-V semiconductor micro disc 112. The pillar 110 is formed in the first aperture 106. The micro disc 112 is formed above the insulating layer 104. The pillar 110 has a bottom portion 110b abutting (i.e. in contact with) the upper surface of the substrate 100a. The pillar 110 may an upper portion 110a protruding from the first aperture 106 above an upper surface 104a of the insulating layer 104. The micro disc part 112 extends from the upper portion 110a of the pillar 110, horizontally or laterally along the upper surface 104a (i.e. in the horizontal plane defined by the axes X and Y). The micro disc 112 is accordingly formed to enclose the upper portion 110a of the pillar 110 in a horizontal plane, or in other words enclose in a circumferential direction with respect to the pillar 110. The semiconductor structure 108 may be formed by vapor phase epitaxy.

[0042] It should be noted that the particular polygonal shape of the disc part 112 illustrated in FIG. 5B merely is one example and that other shapes, such as generally hexagonal shape, also are possible. The specific shape typically may depend on the growth conditions and the orientation of the growth surfaces.

[0043] A semiconductor structure 108 may be formed of any one of InSb, GaAs, GaSb, InAs, InGaAs or InGaSb. The process conditions of the epitaxial process may be controlled such that the at least the micro disc 112 is formed of monocrystalline material, for instance monocrystalline InSb, GaAs, GaSb, InAs, InGaAs or InGaSb.

[0044] The epitaxial growth process may be adapted such that, for the group III-V semiconductor micro disc 112, a growth rate in a horizontal plane (i.e. along the first and second horizontal directions X and Y) is greater than a growth rate in a vertical direction Z. The lateral/horizontal growth rate may for instance be (at least) a factor 10 greater than the vertical growth rate. This may be implemented during at least a part of the epitaxial growth process in which the micro disc 112 is grown. However, as the lateral growth inside the first aperture 106 will be limited by the lateral dimensions of the first aperture 106 a lateral growth may be promoted throughout the epitaxial growth of the full semiconductor structure 108.

[0045] For instance, a lateral growth of a group III-V semiconductor material may be obtained by controlling a growth temperature to be in the range of 500 C. to 650 C. A total pressure (in the growth chamber) may be in the range of 20 mbar to 150 mbar. The process conditions during the growth may be controlled such that a lateral growth rate in the range of 1 nm/s to 5 nm/s, and a vertical growth rate in or below the range 0.1 nm/s to 0.5 nm/s is obtained. The upper surface 112a of the epitaxial grown micro disc 112 may be terminated with the group V material forming a (111)B-terminated surface. The micro disc 112 may be doped either in situ or via an implantation process.

[0046] In FIGS. 6A, 6B, a first material 114 has been deposited on the upper surface of the micro disc 112a and the remaining upper surface of the insulating layer 104a not covered by the micro disc 112. The first material 114 may be conformally deposited such that it covers the entire upper surface of the insulating layer 104a and the micro disc 112a as well as all the side surfaces of the micro disc 112. The first material 114 may be deposited by e.g. a chemical vapor deposition. The first material 114 may be formed of amorphous Si (a-Si).

[0047] In FIGS. 7A, 7B, a top portion of the first material 114 has been removed exposing the upper surface 112a of the micro disc 112. Hence, the first material 114 covers the side surfaces of the micro disc 112. The removal of the first material 114 may be performed using e.g. a Chemical Mechanical Polishing (CMP) step. The polishing may be controlled such that the first material 114 removal is stopped when exposing the upper surface of the micro disc 112a. Subsequently, a further top portion of the first material 114 may be additionally removed by further recessing, as shown in FIGS. 8A and 8B. Such recessing may hence provide an access to only side surfaces of the micro disc 112. In FIGS. 9A, 9B, a second material 116 has been deposited on the upper surface of the micro disc 112a and the upper surface 114a of the first material 114. The second material may be conformally deposited such that it covers the entire upper surface of the first material 114a and the micro disc 112a as well as all the remaining portion of the side surfaces of the micro disc 112 not covered by the first material 114. The second material may be the same material as the insulating layer 104 and may be deposited in the same way. In FIGS. 10A, 10B, a top portion of the second material 116 has been removed exposing the upper surface 112a of the micro disc 112. Hence, the second material 116 covers the remaining side surfaces of the micro disc 112 not covered by the first material 114. Selection of the first material 114 and the second material 116 may in some embodiments be such that one may be selectively etched i.e. etching the first material 114 but not the second material 116 to provide access to a side portion of the micro disc 112. The removal of the thickness portion of the second material 116 may be performed using e.g. a CMP step. The first material 114 and the second material 116 may respectively form a lower layer and an upper layer of a first layer.

[0048] In FIGS. 11A, 11B, a TMD layer 118 has been formed on the upper surface of the micro disc 112a. The TMD layer 118 may be epitaxially grown such that a thickness of the TMD layer 118 may be in the range from 1.2 to 12 nm (1 to 10 MLs), allowing 2D growth of the TMD layer 118. The crystalline structure of the upper surface of the micro disc 112 provide a template for the epitaxial growth of the TMD layer 118 allowing the growth of the TMD materials in layer format. The epitaxial growth of the TMD layer 118 may be performed using physical or chemical vapor deposition approaches. The TMD layer may comprise one or more TMD materials for instance in a stack structure. Examples of such TMD material are MoS.sub.2, WSe.sub.2. Prior to the growth of the TMD layer 118, the upper surface 112a of the (111)B-terminated micro disc 112 may be passivated using e.g. S, Se, or Te. Such passivation step may be performed in the same reactor used for the TMD growth. The passivation step may for instance be performed at initial stage of the TMD growth by performing an annealing step under H.sub.2X flow where X may be S, Se, or Te. The epitaxial growth of the TMD layer may hence be performed by changing the growth condition after the passivation step e.g. precursors and growth temperature. The epitaxial growth of the TMD layer 118 on the passivated upper surface 112a of the micro disc 112 may lead to epitaxial growth of high crystalline quality TMD layer 118 having large grain sizes. In addition, the passivation of the upper surface 112a of the micro disc 112 may reduce the dangling bonds and interface states and hence improve the heterointerface between the III-V micro disc 112 and the TMD layer 118.

[0049] Up to here, a TMDIII-V semiconductor heterostructure has been formed. In the following, an exemplary method for forming a TFET device including such heterostructure will be disclosed in conjunction with the remaining figures.

[0050] In FIGS. 12A, 12B, a layer 120 similar to the second material 116 has been formed on the upper surface 118a of the TMD layer 118 and the upper surface 116a of the second material 116. The layer 120 may be formed in the same way as the second material layer 116. The formation of such layer 120 may protect the TMDIII-V heterostructure during further processing steps.

[0051] In FIGS. 13A, 13B, a mask layer 122 has been formed on the upper surface 120a of the layer 120. The mask layer 122 may be formed by deposition of a mask material, such as a photo-resist based mask material or any other typical lithographic stack compatible material. The mask layer 122 may subsequently be defined by patterning the mask layer 122 using a conventional patterning technique to define a second aperture 124. A first portion of the second aperture 124 may be formed by removing a portion of the mask material defined through the patterning. A second portion of the second aperture 124 i.e. the portion formed of the second material 116 and 120 may subsequently be removed exposing a portion of an upper surface of the insulating layer 104, as shown in FIGS. 14A and 14B.

[0052] In FIGS. 15A, 15B, a third portion of the second aperture 124 has been formed by selective etching of the first material 114 from the second portion 124b of the second aperture 124. This may hence form a recess extending to a side surface of the III-V micro disc. Afterwards, the mask layer 122 may be removed, finalizing the second aperture 124, ready for a subsequent epitaxial growth step, as shown in FIGS. 16A and 16B. The mask layer 122 may be removed in a chemical process e.g. using a solvent to dissolve the mask material.

[0053] In FIGS. 17A, 17B, a laterally extended portion 112c of the micro disc 112 has been epitaxially grown in the second aperture 124. The laterally extended portion 112c of the micro disc 112 may be grown in the same way as the micro disc 112. The laterally extended portion 112c of the micro disc 112 may have the same material composition as the micro disc 112 or may be formed of another type of III-V semiconductor material different from the micro disc 112. The laterally extended portion 112c of the micro disc 112 may be doped either in situ or via an implantation process. The epitaxial growth parameters used for the growth of the extended portion 112c of the micro disc 112 may be tuned similar to the growth parameters used for the micro disc 112 allowing a higher growth rate in the horizontal plane than the growth rate in the vertical direction.

[0054] In FIGS. 18A, 18B, another mask layer 126 has been formed on the upper surface 120a of the layer 120. The mask layer 126 may be formed in the same way as the mask layer 122. The mask layer 126 may subsequently be defined by patterning the mask layer 126 using a conventional patterning technique to define a third aperture 128. A first portion of the third aperture 128 may be formed by removing a portion of the mask material defined through the patterning. A second portion of the third aperture 128 i.e. the portion formed of the second material 116 and 120 may subsequently be removed exposing a portion of an upper surface of the TMD layer 118 and a portion of an upper surface of the first material 114, as shown in FIGS. 19A and 19B.

[0055] In FIGS. 20A, 20B, a third portion of the third aperture 128 has been removed by selective etching of the first material 114 from the second portion of the third aperture 128. This may hence allow an access to another side surface of the micro disc 112. In FIGS. 21A, 21B, a portion of the exposed side surface of the micro disc 112 has been recessed from the third aperture 128 such that a portion 118c of the TMD layer 118 may protrude from the upper surface 112a of the micro disc 112. The protrude portion 118c of the TMD layer 118 may or may not collapse on the upper surface 104a of the insulating layer 104. In the remaining figures, the protruding portion 118c of the TMD layer 118 has been exemplified in a collapsed embodiment.

[0056] The mask layer 126 and the second material layers 116 and 120 have been removed in FIGS. 22A and 22B. The removal of the mask material for the mask layer 126 may be performed in the same way of the removal of the mask layer 122. The removal of the second material layers 116 and 120 may be performed in the same way as the etching of the insulating layer 104.

[0057] In FIGS. 23A, 23B, a gate contact mask 130 has been formed to cover a portion of the TMD layer 118 including the protrude portion 118c of the TMD layer 118, the upper surface of the laterally extended portion 112c of the micro disc 112 and the upper surface of the remained portion of insulating layer 104 not covered by the heterostructure. The gate contact mask 130 may for instance be a resist-based mask or a PMMA mask. A gate contact opening 132 has been defined in the mask 130, exposing a portion of the upper surface 118a of the TMD layer 118. The mask opening 132 may have a rectangular top view as shown in FIG. 23B. The mask opening may have another top views such as square or circular shape.

[0058] In FIGS. 24A, 24B, a gate insulating layer 134 has been formed in contact with the upper surface of the TMD layer 118 inside the mask opening 132. The gate insulating layer 134 may be formed of a high-K dielectric material such as hafnium oxide or some other CMOS compatible gate dielectric. The gate insulating layer 134 may be deposited by any suitable and conventional deposition technique, such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). A thickness of such gate insulating layer 134 may be in a range from 1 to 10 nm such that the thickness of the gate insulating layer 134 may not fill the mask opening 132. Afterwards, a gate contact layer 136 may be formed in contact with an upper surface of the gate insulating layer 134. The gate contact layer 136 may be a metal or a metal alloy. The gate contact layer 136 may be deposited by any conventional deposition technique, such as by ALD, CVD or physical vapor deposition (PVD). The material may be deposited to fill the mask opening 132. In FIGS. 25A, 25B, the gate contact mask 130 has been removed. The removal of such mask may be performed in the same way as the way of the removal of the mask layers 122 and 126.

[0059] In FIGS. 26A, 26B, a source/drain contact mask 138 has been formed to cover an entire upper surface of the structure except two areas: a portion of the upper surface of the laterally extended portion 112c of the micro disc 112 and a portion of an upper surface of the protrude portion 118c of the TMD layer 118. Respective mask openings 140a and 140b have been formed exposing such two areas for forming a source and a drain contact. The mask may be formed in the same way as the gate contact mask 130 and may have similar or different geometries.

[0060] In FIGS. 27A, 27B, a source contact layer 142 and a drain contact layer 144 have been formed. The source contact layer 142 and the drain contact layer 144 may be formed in the same way as the gate contact layer 136 and may be formed of a similar or different materials. The source contact layer 142 and the drain contact layer 144 may be deposited to fill the respective mask openings 140a and 140b.

[0061] In FIGS. 28A, 28B, the source/drain contact mask 138 has been removed illustrating schematic illustrations of a fabricated TFET with a channel forming in the heterostructure. FIGS. 28A and 28B show only one example of such TFET device. The TFET device may be designed with a different layout for instance by patterning the micro disc 112 into a nanowire. The nanowire geometry allows to use a substrate surface area more efficiently when desired, since a plurality of the TMDIII-V heterostructures with the nanowire geometry may be packed on the same substrate surface area, compared to the micro disc geometry.

[0062] Further embodiments of the present disclosure will become apparent to a person skilled in the art after studying the description above. Even though the present description and drawings disclose embodiments and examples, the disclosure is not restricted to these specific examples. Numerous modifications and variations can be made without departing from the scope of the present disclosure, which is defined by the accompanying claims. Any reference signs appearing in the claims are not to be understood as limiting their scope.

[0063] While the disclosure has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative or exemplary and not restrictive. The disclosure is not limited to the disclosed embodiments. Variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed disclosure, from a study of the drawings, the disclosure and the appended claims.

[0064] All references cited herein are incorporated herein by reference in their entirety. To the extent publications and patents or patent applications incorporated by reference contradict the disclosure contained in the specification, the specification is intended to supersede and/or take precedence over any such contradictory material.

[0065] Unless otherwise defined, all terms (including technical and scientific terms) are to be given their ordinary and customary meaning to a person of ordinary skill in the art, and are not to be limited to a special or customized meaning unless expressly so defined herein. It should be noted that the use of particular terminology when describing certain features or aspects of the disclosure should not be taken to imply that the terminology is being re-defined herein to be restricted to include any specific characteristics of the features or aspects of the disclosure with which that terminology is associated. Terms and phrases used in this application, and variations thereof, especially in the appended claims, unless otherwise expressly stated, should be construed as open ended as opposed to limiting. As examples of the foregoing, the term including should be read to mean including, without limitation, including but not limited to, or the like; the term comprising as used herein is synonymous with including, containing, or characterized by, and is inclusive or open-ended and does not exclude additional, unrecited elements or method steps; the term having should be interpreted as having at least; the term includes should be interpreted as includes but is not limited to; the term example is used to provide exemplary instances of the item in discussion, not an exhaustive or limiting list thereof; adjectives such as known, normal, standard, and terms of similar meaning should not be construed as limiting the item described to a given time period or to an item available as of a given time, but instead should be read to encompass known, normal, or standard technologies that may be available or known now or at any time in the future; and use of terms like preferably, preferred, desired, or desirable, and words of similar meaning should not be understood as implying that certain features are critical, essential, or even important to the structure or function of the invention, but instead as merely intended to highlight alternative or additional features that may or may not be utilized in a particular embodiment of the invention. Likewise, a group of items linked with the conjunction and should not be read as requiring that each and every one of those items be present in the grouping, but rather should be read as and/or unless expressly stated otherwise. Similarly, a group of items linked with the conjunction or should not be read as requiring mutual exclusivity among that group, but rather should be read as and/or unless expressly stated otherwise.

[0066] As used in the claims below and throughout this disclosure, by the phrase consisting essentially of is meant including any elements listed after the phrase, and limited to other elements that do not interfere with or contribute to the activity or action specified in the disclosure for the listed elements. Thus, the phrase consisting essentially of indicates that the listed elements are required or mandatory, but that other elements are optional and may or may not be present depending upon whether or not they affect the activity or action of the listed elements.

[0067] Where a range of values is provided, it is understood that the upper and lower limit, and each intervening value between the upper and lower limit of the range is encompassed within the embodiments.

[0068] With respect to the use of substantially any plural and/or singular terms herein, those having skill in the art can translate from the plural to the singular and/or from the singular to the plural as is appropriate to the context and/or application. The various singular/plural permutations may be expressly set forth herein for sake of clarity. The indefinite article a or an does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage. Any reference signs in the claims should not be construed as limiting the scope.

[0069] It will be further understood by those within the art that if a specific number of an introduced claim recitation is intended, such an intent will be explicitly recited in the claim, and in the absence of such recitation no such intent is present. For example, as an aid to understanding, the following appended claims may contain usage of the introductory phrases at least one and one or more to introduce claim recitations. However, the use of such phrases should not be construed to imply that the introduction of a claim recitation by the indefinite articles a or an limits any particular claim containing such introduced claim recitation to embodiments containing only one such recitation, even when the same claim includes the introductory phrases one or more or at least one and indefinite articles such as a or an (e.g., a and/or an should typically be interpreted to mean at least one or one or more); the same holds true for the use of definite articles used to introduce claim recitations. In addition, even if a specific number of an introduced claim recitation is explicitly recited, those skilled in the art will recognize that such recitation should typically be interpreted to mean at least the recited number (e.g., the bare recitation of two recitations, without other modifiers, typically means at least two recitations, or two or more recitations). Furthermore, in those instances where a convention analogous to at least one of A, B, and C, etc. is used, in general such a construction is intended in the sense one having skill in the art would understand the convention (e.g., a system having at least one of A, B, and C would include but not be limited to systems that have A alone, B alone, C alone, A and B together, A and C together, B and C together, and/or A, B, and C together, etc.). In those instances where a convention analogous to at least one of A, B, or C, etc. is used, in general such a construction is intended in the sense one having skill in the art would understand the convention (e.g., a system having at least one of A, B, or C would include but not be limited to systems that have A alone, B alone, C alone, A and B together, A and C together, B and C together, and/or A, B, and C together, etc.). It will be further understood by those within the art that virtually any disjunctive word and/or phrase presenting two or more alternative terms, whether in the description, claims, or drawings, should be understood to contemplate the possibilities of including one of the terms, either of the terms, or both terms. For example, the phrase A or B will be understood to include the possibilities of A or B or A and B.

[0070] All numbers expressing quantities used in the specification are to be understood as being modified in all instances by the term about. Accordingly, unless indicated to the contrary, the numerical parameters set forth herein are approximations that may vary depending upon the desired properties sought to be obtained. At the very least, and not as an attempt to limit the application of the doctrine of equivalents to the scope of any claims in any application claiming priority to the present application, each numerical parameter should be construed in light of the number of significant digits and ordinary rounding approaches.