Method of controlling amplifiers, corresponding circuit and device

Abstract

A differential amplifier generates an output voltage waveform exhibiting a slew rate over a rise time. The amplifier is powered from a dc voltage input and includes a set of differential pairs having a bias current flowing therethrough and a Miller compensation capacitance. A comparator functions to compare a voltage at the dc voltage input against a reference voltage in order to detect when the voltage drops below the reference voltage. A gain stage controls the gain of the differential amplifier and a bias current control circuit controls the bias current of the differential amplifier. In response to the detection by the comparator of the voltage dropping below the reference voltage, the gain stage and the bias current control circuit decrease the gain of the amplifier and jointly decrease the bias current in order to maintain a value of the rise time.

Claims

1. A method of controlling the gain of a differential amplifier in generating an output voltage waveform, wherein said differential amplifier includes a dc voltage input, a set of differential pairs having a bias current flowing therethrough and a Miller compensation capacitance, wherein said differential amplifier exhibits a slew rate over a rise time, wherein said slew rate is a function of said bias current and said Miller capacitance, the method including: comparing a voltage at said dc voltage input against a reference voltage to detect whether the voltage drops below said reference voltage; and as a result of detecting that said voltage has dropped below said reference voltage, jointly decreasing a gain of said differential amplifier and decreasing said bias current in a manner where said rise time is maintained compared to said rise time when the voltage was above said reference voltage, wherein jointly decreasing comprises: generating a multi-bit digital control signal including a first plurality of control bits and a second plurality of control bits as a function of an outcome of comparing said voltage at said dc voltage input against said reference voltage; controlling said gain of the differential amplifier as a function of the first and second pluralities of control bits of said multi-bit digital control signal; and controlling said bias current as a function of only the first plurality of control bits of said multi-bit digital control signal.

2. The method of claim 1, wherein the first plurality of control bits are the most significant bits of said multi-bit digital control signal.

3. The method of claim 1, wherein controlling the bias current comprises varying said bias current as a function of said gain of said differential amplifier.

4. The method of claim 3, wherein varying comprises proportionally varying.

5. A circuit, including: a differential amplifier configured to generate an output voltage waveform, said differential amplifier including a dc voltage input, a set of differential pairs having a bias current flowing therethrough and a Miller compensation capacitance, wherein said differential amplifier exhibits a slew rate over a rise time, wherein said slew rate is a function of said bias current and said Miller capacitance, a comparator configured to compare a voltage at said dc voltage input against a reference voltage to detect a drop of the voltage below said reference voltage and generate a multi-bit digital control signal including a first plurality of control bits and a second plurality of control bits as a function of the comparison of said voltage at said dc voltage input against said reference voltage, a gain stage configured to control a gain of said differential amplifier as a function of the first and second pluralities of control bits of said multi-bit digital control signal, and a bias current control circuit configured to control said bias current of said differential amplifier as a function of only the first plurality of control bits of said multi-bit digital control signal, wherein said gain stage and said bias current control circuit are coupled with said comparator and configured to jointly decrease the gain of said amplifier and decrease said bias current if said comparator detects that said voltage has dropped below said reference voltage in a manner where said rise time is maintained compared to said rise time when the voltage was above said reference voltage.

6. The circuit of claim 5, wherein the first plurality of control bits are the most significant bits of said multi-bit digital control signal.

7. The circuit of claim 5, wherein said gain stage and said bias current control circuit are coupled with said comparator and configured to jointly decrease the gain of said amplifier and decrease said bias current by varying said bias current as a function of said gain.

8. The circuit of claim 7, wherein varying comprises proportionally varying.

9. The circuit of claim 5, further including a load coupled with the output of said differential amplifier to receive said output voltage waveform from said differential amplifier.

10. The circuit of claim 9, wherein said load includes a piezoelectric actuator.

11. The circuit claim 5, wherein the circuit is a component of a haptic driver.

12. A circuit, comprising: a voltage amplifier having an inverting input and a non-inverting input and further having an amplifier output, the voltage amplifier further including a digital-to-analog converter circuit having an input and further having a converter output; a Miller capacitor having a first terminal connected to the amplifier output and a second terminal connected to the converter output; a gain stage having an input and further having an output connected to the inverting input of the voltage amplifier; and a comparator configured to compare an input voltage against a reference voltage and generate a multi-bit digital control signal as a function of the comparison of said voltage against said reference voltage for application to the input of the gain stage for setting a gain of the voltage amplifier and for application to the input of the digital-to-analog converter circuit for setting a tail current applied to the Miller capacitor.

13. The circuit of claim 12, wherein the multi-bit digital control signal includes a first plurality of control bits and a second plurality of control bits; wherein the first and second pluralities of control bits of said multi-bit digital control signal are applied to the input of the gain stage for setting the gain of the voltage amplifier; and wherein only the first plurality of control bits of said multi-bit digital control signal are applied to the input of the digital-to-analog converter circuit for setting the tail current applied to the Miller capacitor.

14. The circuit of claim 13, wherein the first plurality of control bits are the most significant bits of said multi-bit digital control signal.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) One or more embodiments will now be described, by way of example only, with reference to the annexed figures, wherein:

(2) FIG. 1 is block diagram exemplary of one or more embodiments;

(3) FIG. 2 is a circuit diagram exemplary of possible characteristics of embodiments;

(4) FIG. 3 is a diagram exemplary of a possible time behaviour of certain signals in one or more embodiments;

(5) FIG. 4 is a flow chart exemplary of possible operation of one or more embodiments;

(6) FIG. 5 is a flow chart exemplary of possible operation of one or more embodiments; and

(7) FIG. 6 is a circuit diagram exemplary of possible characteristics of embodiments.

DETAILED DESCRIPTION

(8) In the ensuing description, one or more specific details are illustrated, aimed at providing an in-depth understanding of examples of embodiments of this description. The embodiments may be obtained without one or more of the specific details, or with other methods, components, materials, etc. In other cases, known structures, materials, or operations are not illustrated or described in detail so that certain aspects of embodiments will not be obscured.

(9) Reference to an embodiment or one embodiment in the framework of the present description is intended to indicate that a particular configuration, structure, or characteristic described in relation to the embodiment is comprised in at least one embodiment. Hence, phrases such as in an embodiment or in one embodiment that may be present in one or more points of the present description do not necessarily refer to one and the same embodiment. Moreover, particular conformations, structures, or characteristics may be combined in any adequate way in one or more embodiments.

(10) The references used herein are provided merely for convenience and hence do not define the extent of protection or the scope of the embodiments.

(11) By way of general background, haptic technology, or haptics, is a method of providing a tactile feedback response to a designated input. Derived from the Greek word haptikos, haptics is the scientific discipline that is concerned with touch. It may be resorted to in electronic devices to recreate the sense of touch to a user, e.g., through vibrations or forces. The basic components for producing and regulating haptic feedback may include a microcontroller, a mechanical driver and an actuator.

(12) Piezoelectric actuators (or, simply, piezo actuators) may include thin layers of piezoelectric materials that bend back and forth quickly when a voltage is applied, causing vibration. This bending of piezo actuators may involve applying thereto a relatively high voltage input from a driver, usually between 50 and 150 volts. To provide this high voltage, the system may include a piezo-specific haptic driver.

(13) The designation throttle mechanism denotes the mechanism by means of which a battery voltage drop is detected and the battery current consumption automatically reduced.

(14) FIG. 1 is a block diagram exemplary of a circuit 10 intended to be fed with a dc (e.g., battery) supply voltage VBAT and to generate a (high) voltage waveform VOUT which may be used, e.g., to generate vibration in a piezo actuator PA (which per se may be a distinct element from the embodiments).

(15) A throttle block 12 may sense the voltage level of the battery VBAT on a sensing input 12a, and compare it with a reference voltage (VTH), that may be user-programmable, e.g., via a reference input 12b.

(16) A logic signal generated as a result of such a comparison may be processed (in a manner known per se) by internal control logic of the throttle block 12 to produce over an output line 12c a control signal CS to control (e.g., reduce) automatically the (voltage) gain of a processing block (channel) 14 which produces the signal VOUT (when the device 10 is operative in an active state with output enabled).

(17) The block 14 may include a digital-to-analog converter (DAC) 16 to convert an input digital stream DS on an input 16a (from a digital generator referred to a digital supply voltage Vdd, not visible in the figures) into an analog drive signal applied to an (e.g., positive, non-inverting) input VINP of a (high) voltage amplifier 18 (e.g., a high-voltage operational amplifierHV OPAMP). In one or more embodiments the amplifier 18 may thus apply a corresponding (high-voltage) signal VOUT to the load PA (e.g., a piezo actuator).

(18) A gain stage 20 sensitive to the control signal CS may be coupled to an (e.g. negative, inverting) input VINN of the amplifier 18 in order to vary the gain of the amplifier 18 as a function of the battery voltage VBAT detected by the throttle block 12. The control signal CS for the block 14 (e.g. the gain stage 20) may include four bits, e.g. Bit_gain<3:0>.

(19) The amplifier 18 may include a high voltage amplifier to drive the piezo actuator PA with an internal slew rate which may be limited.

(20) The block (channel) 14 may generate a step function with, e.g., 90 Vpp amplitude and with a constant rise time of, e.g., 87 microseconds (1 microsecond=110.sup.6 s), with rise time calculated from 10% to 90% of the output voltage.

(21) As exemplified in FIG. 2 such an internal slew rate may be determined by a current represented as Itail (this is in fact a bias current flowing through the differential pairs of the high voltage amplifier 18) and by a internal (compensation) Miller capacitance C.sub.MILLER.

(22) The bias current Itail for the differential pairs of the amplifier 18 may be derived, e.g., from VBOOST, the supply voltage for the high voltage amplifier.

(23) As schematically represented in the diagram of FIG. 3, during a positive step function generation, when a controlled slew rate SR is desirable, the tail current Itail may flow through the Miller capacitance C.sub.MILLER and the following equation may apply:
SR=VOUT/T=Itail/C.sub.MILLER

(24) where: the slew rate SR may be is calculated, e.g., between the 10% and 90% of the output voltage; VOUT is the output voltage value; and T is the rise time.

(25) As a result of a battery voltage drop being detected by the throttling block 12, the output voltage VOUT may be reduced due to the action of the gain stage 20. In this situation, if both Itail and C.sub.MILLER are assumed to be fixed, the rise time T will change proportionally to VOUT, e.g., with the rise time T changing following the variations of VOUT, e.g.:
T=VOUT/Itail/C.sub.MILLER=VINPGAINC.sub.MILLER/Itail

(26) As a result of a drop in the battery voltage VBAT being detected by the throttle block 12, the tail current Itail may decrease proportionally to VOUT:
Itail=VINPGAINC.sub.MILLER/T

(27) One may observe that in the equation above, if the input signal voltage VINP, the compensation capacitance C.sub.MILLER and the rise time T are assumed fixed by design, only the gain value (GAIN) will change in the equation, due to the throttling block 12 and its internal logic.

(28) The flowchart of FIG. 4 is generally exemplary of throttling control, where the following designations apply to the blocks shown: 100: off state; 102: switching to active state with check as to VBAT<VTH; if check outcome is negative (NO), back to upstream of step 102; 104: gain control (decrease) as a result of check in step 102 yielding a positive outcome (Y); 106: check as to whether active state is to be maintained; if outcome is positive (Y), back to upstream of step 104; if negative (N) back to off state of block 100.

(29) The flowchart of FIG. 5 is exemplary of gain control (with joint control of the tail current Itail) according to one or more embodiments, where the following designations apply to the blocks shown: 104: gain control (decrease)see FIG. 4followed by check in step 1040 if control signal CS has changed (which information may be conveyed, e.g., as bit_gain<3:2>, as discussed in the following); 1042: if outcome of check in step 1040 negative (N): current Itail kept fixed, back to upstream of step 1040; 1044: if outcome of check in step 1040 is positive (Y): current Itail kept controlled (decreased), back to upstream of step 1040.

(30) In one or more embodiments, the circuit 10 may thus exhibit a fixed rise time T due to the fact that the tail current Itailwhich in conventional arrangements is fixed, thus leading to the dependency of T on VOUT as discussed previouslyis made variable, e.g., may be changed as a function (e.g. proportionally) to the gain value, e.g., via a control signal applied over a line 182a (not present in conventional arrangements).

(31) The table below is exemplary of possible values in operation as exemplified above

(32) TABLE-US-00001 VBAT Bit_gain<3:2> Gain (dB) Itail >VTH 1111 40 ITAIL1 <VTH 1110 39.5 ITAIL1 <VTH 1101 39 ITAIL1 <VTH 1100 38.5 ITAIL1 <VTH 1011 38 ITAIL2 <VTH 1010 37.5 ITAIL2 <VTH 1001 37 ITAIL2 <VTH 1000 36.5 ITAIL2 <VTH 0111 36 ITAIL3 <VTH 0110 35.5 ITAIL3 <VTH 0101 35 ITAIL3 <VTH 0100 34.5 ITAIL3 <VTH 0011 34 ITAIL4 <VTH 0010 33.5 ITAIL4 <VTH 0001 33 ITAIL4 <VTH 0000 32.5 ITAIL4

(33) FIG. 6 is a circuit diagram further exemplary of possible characteristics of embodiments. In FIG. 6, parts or elements already introduced in connection with FIGS. 1 and 2 are indicated with the same references, thus making it unnecessary to repeat a description thereof.

(34) As exemplified in FIG. 6, in one or more embodiments the two most significant bits of the bit_gain <3:0>signal CS, e.g., bit_gain<3:2>, as conveyed, e.g., over the line 182a to a digital-to-analog converter (DAC) 182, e.g., in the amplifier 18 to change the tail current Itail in the amplifier 18, while setting at the same time the rise time T (e.g., to maintain it at a substantially constant value, without being affected by VOUT).

(35) The following tables are exemplary of values/parameters which may be used/obtained in one or more embodiments:

(36) TABLE-US-00002 Parameter Value Unit Comment Bit_gain<3:0> 4 bit 4 bit used VBOOST 116 V HV OPAMP Supply voltage C.sub.MILLER 10.8 pF Miller capacitor VINP 0.9 V Output DAC T 86.4 microsec Fixed Rise Time

(37) TABLE-US-00003 Itail bit_gain<3> bit_gain<2> bit_gain<1> bit_gain<0> GAIN VOUT (microA) 0 0 0 0 100 90 10 0 0 0 1 94.4061 84.9 10 0 0 1 0 89.1251 80.2 10 0 0 1 1 84.1395 75.7 10 0 1 0 0 79.4328 71.5 8 0 1 0 1 74.9894 67.5 8 0 1 1 0 70.7946 63.7 8 0 1 1 1 66.8344 60.2 8 1 0 0 0 63.0957 56.8 6 1 0 0 1 59.5662 53.6 6 1 0 1 0 56.2341 50.6 6 1 0 1 1 53.0884 47.6 6 1 1 0 0 50.1187 45.1 5 1 1 0 1 47.3151 42.6 5 1 1 1 0 44.6684 40.2 5 1 1 1 1 42.1697 37.9 5

(38) It will be otherwise understood that the values/parameters reported in the foregoing are merely exemplary and should not construed, even indirectly, as limitative of the embodiments.

(39) This applies, e.g., to the choice of using two bits to change the current Itail in the amplifier 18. In one or more embodiments, e.g., all of the four bits of the control signal CS may be used to change the current Itail, thus increasing control resolution.

(40) One or more embodiments may thus provide a method of controlling the gain (e.g., at 20) of a differential amplifier (e.g., 18) in generating an output voltage waveform (e.g., VOUT), wherein said amplifier includes a dc voltage input (e.g., VBAT at 12a), a set of differential pairs having a bias current (Itail, 182) flowing therethrough and a Miller compensation capacitance (e.g., C.sub.MILLER), wherein said amplifier exhibits a slew rate (e.g., SR) over a rise time (e.g., T), wherein said slew rate is a function of said bias current and said Miller capacitance, the method including: comparing (e.g., within 12) the voltage at said dc voltage input against a reference voltage (e.g., VTH) to detect the voltage at said dc voltage input dropping below said reference voltage; and as a result of detecting said voltage at said dc voltage input dropping below said reference voltage, decreasing the gain of said amplifier jointly with said bias current wherein said rise time is maintained.

(41) One or more embodiments may include: generating a gain control signal (e.g., CS; bit_gain<3:0>) indicative of the outcome of comparing said voltage at said dc voltage input against said reference voltage, and controlling (e.g., 182; bit_gain<3:2>) said bias current as a function of said gain control signal.

(42) One or more embodiments may include: generating said gain control signal as a multi-bit digital signal (e.g., bit_gain<3:0>), and controlling (e.g., 182) said bias current as a function of at least one part (e.g., bit_gain<3:2>) of the bits in said multi-bit digital signal, said at least one part optionally including the most significant bits of said multi-bit digital signal.

(43) In one or more embodiments, said decreasing the gain of said amplifier jointly with said bias current may include varying said bias current as a function of, optionally proportionally to, said gain of said amplifier.

(44) One or more embodiments may provide a circuit (e.g., 10), including: a differential amplifier for generating an output voltage waveform, said amplifier including a dc voltage input, a set of differential pairs having a bias current flowing therethrough and a Miller compensation capacitance, wherein said amplifier exhibits a slew rate over a rise time, wherein said slew rate is a function of said bias current and said Miller capacitance, the circuit including: a comparator block for comparing the voltage at said dc voltage input against a reference voltage to detect the voltage at said dc voltage input dropping below said reference voltage, a gain stage controlling (e.g., VINN) the gain of said differential amplifier, a bias current control module controlling said bias current of said differential amplifier,

(45) wherein said gain stage and said bias current control module are coupled with said comparator block and configured for decreasing the gain of said amplifier jointly with said bias current as a result of said comparator block detecting said voltage at said dc voltage input dropping below said reference voltage, wherein said rise time is maintained.

(46) One or more embodiments may include: said comparator block configured for generating a gain control signal indicative of the outcome of comparing said voltage at said dc voltage input against said reference voltage, and said bias current control module configured for controlling said bias current as a function of said gain control signal.

(47) One or more embodiments may include: said comparator block configured for generating said gain control signal as a multi-bit digital signal, and said bias current control module configured for controlling said bias current as a function of at least one part of the bits in said multi-bit digital signal, said at least one part optionally including the most significant bits of said multi-bit digital signal.

(48) In one or more embodiments said gain stage and said bias current control module may be coupled with said comparator block and configured for decreasing the gain of said amplifier jointly with said bias current by varying said bias current as a function of, optionally proportionally to, said gain of said amplifier.

(49) One or more embodiments may provide a device, including: a circuit according to one or more embodiments, and a load (e.g. PA) coupled with the output of said differential amplifier to receive said output voltage waveform from said differential amplifier.

(50) In one or more embodiments said load may include a piezoelectric actuator.

(51) In one or more embodiments the device may include a haptic driver.

(52) Without prejudice to the underlying principles, the details and embodiments may vary, even significantly, with respect to what has been disclosed by way of example only, without departing from the extent of protection.