Resistive memory cell structures and methods

Abstract

Resistive memory cell structures and methods are described herein. One or more memory cell structures comprise a first resistive memory cell comprising a first resistance variable material and a second resistive memory cell comprising a second resistance variable material that is different than the first resistance variable material.

Claims

1. A method of forming an array of resistive memory cells, the method comprising: forming an uninterrupted covering of conductive material in a first and a second region of the array; forming a first resistance variable material in the first and the second regions on the uninterrupted covering of conductive material; forming a first cap material in the first and the second regions on the first resistance variable material; removing the first resistance variable material and the first cap material from the second region; forming a second resistance variable material on the first cap material of the first region and on the uninterrupted covering of the conductive material of the second region; forming a second cap material in the first and second regions on the second resistance variable material; removing the second resistance variable material and the second cap material from the first region; and forming separate cell stacks corresponding to a respective first and second number of resistive memory cells, wherein forming the separate cell stacks comprises: removing portions of the uninterrupted covering of the conductive material from the first region and the second region; removing a portion of the first resistance variable material from the first region; removing a portion of the first cap material from the first region; removing a portion of the second resistance variable material from the second region; and removing a portion of the second cap material from the second region.

2. The method of claim 1, wherein forming the array comprises: forming the first number of resistive memory cells in the first region of the array, the first number of cells comprising the first resistance variable material; and forming the second number of resistive memory cells in the second region of the array, the second number of cells comprising the second resistance variable material that is different than the first resistance variable material.

3. The method of claim 1, wherein the first and second cap materials serve as bit lines for the respective first and second number of resistive memory cells.

4. The method of claim 2, wherein the first and second resistance variable materials include different chalcogenide alloys.

5. The method of claim 1, further comprising: forming the first resistance variable material having a first electrothermal property on the uninterrupted covering of the conductive material; and forming the second resistance variable material having a second electrothermal property different than the first electrothermal property on the first cap material of the first region and on the uninterrupted covering of the conductive material of the second region.

6. The method of claim 1, further comprising removing the first resistance variable material and the first cap material from the second region via an etch process.

7. The method of claim 1, further comprising removing the second resistance variable material and the second cap material from the first region via an etch process.

8. The method of claim 1, further comprising forming the uninterrupted covering of the conductive material over a dielectric material and a plurality of conductive plugs in each of the first region and the second region.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a schematic diagram of a portion of a resistive memory array in accordance with a number of embodiments of the present disclosure.

(2) FIGS. 2A-2E illustrate various process stages associated with forming an array of resistive memory cells in accordance with a number of embodiments of the present disclosure.

(3) FIGS. 3A-3F illustrate various process stages associated with forming an array of resistive memory cells in accordance with a number of embodiments of the present disclosure.

(4) FIGS. 4A-4I illustrate various process stages associated with forming an array of resistive memory cells in accordance with a number of embodiments of the present disclosure.

(5) FIGS. 5A-5E illustrate various process stages associated with forming an array of resistive memory cells in accordance with a number of embodiments of the present disclosure.

DETAILED DESCRIPTION

(6) Resistive memory cell structures and methods are described herein. As an example, an array of resistive memory cells can include a first resistive memory cell comprising a first resistance variable material and a second resistive memory cell comprising a second resistance variable material that is different than the first resistance variable material.

(7) In a number of embodiments, an array of resistive memory cells includes a first region, e.g., portion, comprising memory cells formed to provide increased speed, e.g., program throughput, and longer endurance, e.g., increased cycling ability, as compared to a second, e.g., different, region of the array. The second region of the array can comprise cells formed to provide an increased reliability, e.g., temperature retention capability, as compared to the cells of the first region of the array. As an example, the first region of the array may be more suitable for data manipulation, while the second region may be more suitable for code storage, e.g., storage of sensitive data, or for data backup.

(8) A region with increased retention capability, as compared to a different region, can also include the region specified to retain data at a higher temperature at a given time than the different region, as well as the region specified to retain data at a give temperature for an increased time period than the different region.

(9) In a number of embodiments, the cells of the first region of the array can comprise a different resistance variable material, e.g., a different chalcogenide alloy, than the cells of the second region. For instance, the cells of the first region may comprise a phase change material, such as, Ge.sub.8Sb.sub.5Te.sub.8, which may be more suited to a higher retention than the cells of the second region, which may comprise a phase change material, such as Ge.sub.2Sb.sub.2Te.sub.6, which may be more suited to increased throughput, e.g., faster set-ability.

(10) In a number of embodiments, the memory cells of the first region and of the second region can comprise the same resistance variable material. In some such embodiments, different reactant materials can be formed on the resistance variable materials of the cells of the respective first and second regions, which can provide for different cell characteristics, e.g., retention capability and/or cycling ability, between the cells of the respective first and second regions. In a number of embodiments, the cell characteristics between the cells of the respective first and second regions of the array can be different due to forming a particular reactant material to a different thickness on the cells of the first region as compared to the cells of the second region.

(11) In one or more embodiments in which the same resistance variable material is used to form the memory cells of the first and second regions of the array, the electrothermal properties of the resistance variable materials of the first and/or second regions can be modified, e.g., via ion implantation, such that the cell characteristics of the cells of the respective first and second regions are different. As such, embodiments of the present disclosure can provide benefits such as providing the ability to tailor the cell characteristics of different regions of a memory array to achieve desired cell characteristics, among other benefits.

(12) In the following detailed description of the present disclosure, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration how one or more embodiments of the disclosure may be practiced. These embodiments are described in sufficient detail to enable those of ordinary skill in the art to practice the embodiments of this disclosure, and it is to be understood that other embodiments may be utilized and that process, electrical, and/or structural changes may be made without departing from the scope of the present disclosure.

(13) The figures herein follow a numbering convention in which the first digit or digits correspond to the drawing figure number and the remaining digits identify an element or component in the drawing. Similar elements or components between different figures may be identified by the use of similar digits. For example, 102 may reference element 02 in FIG. 1, and a similar element may be referenced as 202 in FIG. 2. As will be appreciated, elements shown in the various embodiments herein can be added, exchanged, and/or eliminated so as to provide a number of additional embodiments of the present disclosure. In addition, the proportion and the relative scale of the elements provided in the figures are intended to illustrate various embodiments of the present disclosure and are not to be used in a limiting sense.

(14) FIG. 1 is a schematic diagram of a portion of a resistive memory array 102 in accordance with one or more embodiments of the present disclosure. The resistive memory array 102 includes a number of memory cells 104, each including a select device 132 coupled to a resistive storage element 112. The memory cells 104 can be formed in accordance with embodiments described herein.

(15) The resistive storage elements 112 can include a resistance variable material, e.g., a phase change material. The phase change material can be a chalcogenide, e.g., a GeSbTe (GST) material such as Ge.sub.8Sb.sub.5Te.sub.5, Ge.sub.2Sb.sub.2Te.sub.5, Ge.sub.1Sb.sub.2Te.sub.4, Ge.sub.1Sb.sub.4Te.sub.7, etc., among other resistance variable materials. The hyphenated chemical composition notation, as used herein, indicates the elements included in a particular mixture or compound, and is intended to represent all stoichiometries involving the indicated elements. Other phase change materials can include GeTe, InSe, SbTe, GaSb, InSb, AsTe, AlTe, GeSbTe, TeGeAs, InSbTe, TeSnSe, GeSeGa, BiSeSb, GaSeTe, SnSbTe, InSbGe, TeGeSbS, TeGeSnO, TeGeSnAu, PdTeGeSn, InSeTiCo, GeSbTePd, GeSbTeCo, SbTeBiSe, AgInSbTe, GeSbSeTe, GeSnSbTe, GeTeSnNi, GeTeSnPd, and GeTeSnPt, for example.

(16) The select devices 132 may be field effect transistors, e.g., metal oxide semiconductor field effect transistors (MOSFETs), ovonic threshold switches (OTS), bipolar junction transistors (BJTs) or diodes, among other types of select devices. Although the select device 132 shown in FIG. 1 is a three terminal select device, the select devices can be two terminal select devices, for instance.

(17) In the example illustrated in FIG. 1, the select device 132 is a gated three terminal field effect transistor. As shown in FIG. 1, a gate of each select device 132 is coupled to one of a number of access lines 105-1, 105-2 . . . , 105-N, i.e., each access line 105-1, 105-2, . . . , 105-N is coupled to a row of memory cells 104. The access lines 105-1, 105-2, . . . , 105-N may be referred to herein as word lines. The designator N is used to indicate that the resistive memory array 102 can include a number of word lines.

(18) In the example illustrated in FIG. 1, each resistive storage element 112 is coupled to one of a number of data/sense lines 107-1, 107-2, . . . , 107-M, i.e., each data line 107-1, 107-2, . . . , 107-M is coupled to a column of memory cells 104. The data lines 107-1, 107-2, . . . , 107-M may be referred to herein as bit lines. The designator M is used to indicate that the resistive memory array 102 can include a number of bit lines. The designators M and N can have various values. For instance, M and N can be 64, 128, or 256. In some embodiments, a bit line direction is perpendicular to a word line direction, e.g., the rows of memory cells 104 and the columns of memory cells 104 are perpendicular to one another.

(19) In a number of embodiments, data lines 107-1 and 107-2 can be grouped into a sub-array 136, and other data lines (e.g., data line 107-M) can be grouped into a sub-array 134. In the example illustrated in FIG. 1, a memory cell coupled to bit line 107-1 is adjacent to a memory cell coupled to bit line 107-2. Embodiments are not limited to a particular number of word lines and/or bit lines or a particular number of sub-arrays.

(20) The select devices 132 can be operated, e.g., turned on/off, to select/deselect the memory cells 104 in order to perform operations such as data programming, e.g., writing, and/or data reading operations. In operation, appropriate voltage and/or current signals, e.g., pulses, can be applied to the bit lines and word lines in order to program data to and/or read data from the memory cells 104. As an example, the data stored by a memory cell 104 of array 102 can be determined by turning on a select device 132, and sensing a current through the resistive storage element 112. The current sensed on the bit line corresponding to the memory cell 104 being read corresponds to a resistance level of the resistance variable material of resistive storage element 112, which in turn may correspond to a particular data state, e.g., a binary value. The resistive memory array 102 can have an architecture other than that illustrated in FIG. 1, as will be understood by one of ordinary skill in the art.

(21) FIGS. 2A-2E illustrate various process stages associated with forming an array 202 of resistive memory cells in accordance with a number of embodiments of the present disclosure. In a number of embodiments, the resistive memory cells may be coupled to a same bit line. The memory cells of array 202 can be resistive memory cells such as resistive memory cells 104, as described above. As an example, the array 202 can be an array of phase change memory cells.

(22) FIG. 2A illustrates a first region 234 and a second region 236 of array 202. In the example shown in FIG. 2A, regions 234 and 236 include conductive plugs 230-1, . . . , 230-4 formed between a heater material 210, e.g., a conductive material, and a substrate 232. The conductive plugs 230-1, . . . , 230-4 are separated by a dielectric material 222 formed on substrate 232. The dielectric material 222 can be a material such as silicon dioxide or silicon nitride, for instance. The substrate 232 can be a silicon substrate, silicon on insulator (SOI) substrate, or silicon on sapphire (SOS) substrate, for instance, and can include various doped and/or undoped semiconductor materials.

(23) Although not shown in FIG. 2A, select devices corresponding to the memory cells of regions 234 and 236 can be formed in substrate 232. As described further herein, resistive memory cells of region 234 can be formed so as to exhibit different cell characteristics as compared to the resistive memory cells of region 236. For instance, the cells of the respective regions 234 and 236 may comprise resistance variable materials having different characteristics, e.g., different electrothermal properties, such that cell characteristics of the cells of the respective regions 234 and 236 are different.

(24) The heater material 210 is formed on plugs 230-1, . . . , 230-4 and can be various conductive materials such as a metal nitride, e.g., tungsten nitride and/or titanium nitride, among other conductive materials. In a number of embodiments, heater material 210 is limited in a direction perpendicular to the rows of memory cells (not shown) prior to a material, e.g., a resistance variable material, being formed on the heater material 210. As used herein, a material being formed on another material is not limited to the materials being formed directly on each other. For instance, a number of intervening materials can be formed between a first material formed on a second material, in various embodiments.

(25) FIG. 2B illustrates a process stage subsequent to that shown in FIG. 2A and associated with forming array 202. A resistance variable material 212, e.g., a phase change material, is formed on heater material 210. That is, the heater material 210 of regions 234 and 236 includes resistance variable material 212 formed thereon.

(26) As illustrated in FIG. 2B, a reactant material 214 is formed on the resistance variable material 212 in regions 234 and 236. The reactant material 214 can be a metal reactant, such as, for example, a reactant comprising titanium, cobalt, and/or tungsten, for instance. Reactant material 214 can serve as a portion of a cap formed on resistance variable material 212.

(27) FIG. 2C illustrates a portion of reactant material 214 removed from region 234 of array 202. The reactant material 214 can be removed from region 234 via an etch process, for instance, without removing the reactant material 214 from region 236.

(28) FIG. 2D illustrates a process stage subsequent to that shown in FIG. 2C and associated with forming array 202. FIG. 2D illustrates a reactant material 216 formed on regions 234 and 236. As such, reactant material 216 is formed on resistance variable material 212 in region 234 and on reactant material 214 in region 236. Reactant material 216 can be a metal reactant, such as, for example, a reactant comprising titanium, cobalt, and/or tungsten, among others. Reactant material 216 can be the same material as reactant material 214, or it can be a different reactant material. Also, reactants 214 and 216 may be formed to the same or different thicknesses.

(29) Providing different reactant materials, e.g., reactant materials 214 and 216, in different regions, e.g., regions 234 and 236, of an array can be used to form memory cells having different cell characteristics, e.g., electrothermal properties, within the respective array regions. For instance, reactant material 214 can react with resistance variable material 212 in region 236, and a different reactant material 216 can react with resistance variable material 212 in region 234. In a number of embodiments, the reactions are thermally activated. The reactants 214 and 216 react differently with the resistance variable material 212 in the respective regions 236 and 234. As such, the electrothermal properties of the resistance variable material 212 in regions 234 and 236 can be modified with respect to each other. Therefore, resistive memory cells formed in region 234 can exhibit different cell characteristics as compared to the cell characteristics of cells formed in region 236.

(30) In a number of embodiments, the reactant materials 214 and 216 can be the same material. In such embodiments, a thickness of the reactant material 214/216 formed in the respective regions 234 and 236 can be different. Providing different thickness of a same reactant material 214/216 in different regions of an array can also affect the cell characteristics within the respective regions, e.g., regions 234 and 236. For instance, cells formed in a region, e.g., region 236, having a thicker reactant material may exhibit a higher retention as compared to cells formed in a region, e.g., region 234, having a thinner reactant material. Cells formed in a region, e.g., region 234, having a thinner reactant material may exhibit a higher programming throughput as compared to cells formed in a region, e.g., region 236, having a thicker reactant material.

(31) FIG. 2D also illustrates a cap material 218, e.g., a conductive material, formed on reactant material 216 in regions 234 and 236. The cap material 218 can comprise a metal nitride such as titanium nitride and/or tungsten nitride, among various other cap materials.

(32) FIG. 2E illustrates a process stage subsequent to that shown in FIG. 2D and associated with forming array 202. As shown in FIG. 2E, individual resistive memory cells 213-1 and 213-2 can be defined by removing portions of materials 210, 212, 214, 216, and 218. In a number of embodiments, resistance variable material 212 is between two conductive elements, e.g., between a conductive cap material 218 and a heater material 210. In this example, the memory cells 213-1 and 213-2 are self-aligned and can be formed via a number of masking and etching processes, for instance.

(33) Although the example shown in FIGS. 2A-2E is for an array of phase change memory cells, embodiments are not so limited. For instance, in a number of embodiments, the array 202 can be an array of RRAM cells or other resistive memory cells having separate regions with different cell characteristics.

(34) FIGS. 3A-3F illustrate various process stages associated with forming array 302 of resistive memory cells in accordance with a number of embodiments of the present disclosure. The memory cells of array 302 can be resistive memory cells such as resistive memory cells 104, as described above. As an example, the array 302 can be an array of phase change memory cells.

(35) FIG. 3A illustrates a first region 334 and a second region 336 of array 302. In the example shown in FIG. 3A, regions 334 and 336 include conductive plugs 330-1, . . . , 330-4 formed between a heater material 310, e.g., a conductive material, and a substrate 332. In a number of embodiments, heater material 310 is limited in a direction perpendicular to the rows of memory cells (not shown) prior to a material, e.g., a resistance variable material, being formed on the heater material 310.

(36) The conductive plugs 330-1, . . . , 330-4 are separated by a dielectric material 322 formed on substrate 332. The dielectric material 322 can be a material such as silicon dioxide or silicon nitride, for instance. The substrate 332 can be a silicon substrate, silicon on insulator (SOI) substrate, silicon on sapphire (SOS) substrate, for instance, and can include various doped and/or undoped semiconductor materials. A heater material 310 is formed on plugs 330-1, . . . , 330-4 and can be various conductive materials, such as metal nitride, e.g., titanium nitride, tungsten nitride, among other conductive materials.

(37) FIG. 3B illustrates a process stage subsequent to that shown in FIG. 3A and associated with forming array 302. A resistance variable material 312-1, e.g., a phase change material, is formed on heater material 310. That is, the heater material 310 of regions 334 and 336 includes resistance variable material 312-1 formed thereon. As is further illustrated in FIG. 3B, a cap material 318-1 is formed on resistance variable material 312-1 in regions 334 and 336.

(38) FIG. 3C illustrates a portion of resistance variable material 312-1 and cap material 318-1 removed from region 334 of array 302. The portions of materials 312-1 and 318-1 can be removed from region 334 via an etch process, for instance, without removing portions of materials 312-1 and 318-1 in region 336 of array 302.

(39) FIG. 3D illustrates a process stage subsequent to that shown in FIG. 3C and associated with forming array 302. FIG. 3D illustrates resistance variable material 312-2 formed on heater material 310 in region 334 and cap material 318-1 in region 336 of array 302. FIG. 3D also illustrates cap material 318-2, e.g., a conductive material, formed on resistance variable material 312-2 in regions 334 and 336.

(40) FIG. 3E illustrates a portion of resistance variable material 312-2 and cap material 318-2 removed from region 336 of array 302. Removing resistance variable material 312-2 from region 336 of array 302 can result in a smooth region, including heater material 310, resistance variable material 312-1, and cap material 318-1 in region 336 of array 302. Region 334 of example array 302 can also be a smooth region, including heater material 310, resistance variable material 312-2, and cap material 318-2. In a number of embodiments, cap materials 318-1 and 318-2 can serve as bit lines for the resistive memory cells.

(41) Providing different materials, e.g., resistance variable materials 312-1 and 312-2, in different regions, e.g., regions 334 and 336, of an array can be used to form memory cells having different cell characteristics, e.g., electrothermal properties, within the respective array regions. For example, resistance variable material 312-1 can act differently within region 336 of array 302 than 312-2 acts within region 334 of array 302. As such, properties of the resistance variable materials 312-1 and 312-2 in regions 336 and 334 may be different, and resistive memory cells formed in region 334 can exhibit different cell characteristics as compared to the cell characteristics of cells formed in region 336.

(42) FIG. 3F illustrates a process stage subsequent to that shown in FIG. 3E and associated with forming array 302. As shown in FIG. 3F, individual resistive memory cells 313-1 and 313-2, e.g., separate cell stacks, can be defined by removing portions of materials 310, 312-1, 318-1, 312-2, and 318-2. In a number of embodiments, resistance variable materials 312-1 and 312-2 are between two conductive elements, e.g., between a conductive cap material 318-1 and/or 318-2 and a heater material 310. In this example, the memory cells 313-1 and 313-2 are self-aligned and can be formed via a number of masking and etching processes, for instance.

(43) Although the example shown in FIGS. 3A-3F is for an array of phase change materials, embodiments are not so limited. For instance, in a number of embodiments, the array 302 can be an array of RRAM cells or other resistive memory cells having separate regions with different cell characteristics.

(44) FIGS. 4A-4I illustrate various process stages associated with forming an array 402 of resistive memory cells in accordance with a number of embodiments of the present disclosure. The memory cells of array 402 can be resistive memory cells such as resistive memory cells 104, as described above with respect to FIG. 1. As an example, the array 402 can be an array of phase change memory cells, but is not so limited.

(45) FIG. 4A illustrates a first region 434 and a second region 436 of array 402. In the example shown in FIG. 4A, regions 434 and 436 of array 402 include conductive plugs 430-1, . . . , 430-4 separated by a dielectric material 422 formed on a substrate material 432. The dielectric material 422 can be a material such as silicon dioxide or silicon nitride, for instance. The substrate 432 can be a silicon substrate, silicon on insulator (SOI) substrate, silicon on sapphire (SOS) substrate, for instance, and can include various doped and/or undoped semiconductor materials.

(46) FIG. 4B illustrates a process stage subsequent to that shown in FIG. 4A and associated with forming array 402. A via 420-1 is formed in a portion of region 436, within dielectric material 422. Via 420-1 can be aligned with a conductive plug in region 436, e.g., plug 430-3.

(47) FIG. 4C illustrates a process stage subsequent to that shown in FIG. 4B and associated with forming array 402. A resistance variable material 412-1 is formed on dielectric 422 in region 434 and region 436 of array 402. As further illustrated in FIG. 4C, resistance variable material 412-1 fills via 420-1. A cap material 418-1, e.g., a conductive material, is formed on resistance variable material 412-1 and can comprise a number of conductive materials, including, for example, tungsten.

(48) FIG. 4D illustrates a portion of resistance variable material 412-1 and a portion of cap material 418-1 removed from region 434 of array 402. The materials 412-1 and 418-1 can be removed from region 434 via an etch process, for instance, without removing materials 412-1 and 418-1 from region 436.

(49) FIG. 4E illustrates a process stage subsequent to that shown in FIG. 4D and associated with forming array 402. A via 420-2 is formed in a portion of region 434, within dielectric material 422. Via 420-2 can be aligned with a conductive plug in region 434, e.g., plug 430-1.

(50) FIG. 4F illustrates a process stage subsequent to that shown in FIG. 4E and associated with forming array 402. A resistance variable material 412-2 is formed on dielectric 422 in regions 434 and on cap material 418-1 in region 436 of array 402. As further illustrated in FIG. 4F, resistance variable material 412fills via 420-2. A cap material 418-2 is formed on resistance variable material 412-2 in regions 436 and 434 and can comprise a number of conductive materials, including, for example, tungsten.

(51) FIG. 4G illustrates a portion of resistance variable material 412-2 and a portion of cap material 418-2 removed from region 436 of array 402. The materials 412-2 and 418-2 can be removed from region 436 via an etch process, for instance, without removing materials 412-2 and 418-2 from region 434.

(52) FIG. 4H illustrates a portion of resistance variable material 412-2 and a portion of cap material 418-2 removed from region 434 of array 402 and a portion of resistance variable material 412-1 and a portion of cap material 418-1 removed from region 436 of array 402. Materials 412-1, 412-2, 418-1, and 418-2 can be removed from regions 434 and 436 via an etch process, such that a portion of resistance variable material 412-1 is confined to and not removed from via 420-1, and a portion of resistance variable material 412-2 is confined to and not removed from via 420-2.

(53) Providing different resistance variable materials, e.g., materials 412-1 and 412-2, in different regions, e.g., regions 434 and 436, of an array can be used to form memory cells having different cell characteristics, e.g., electrothermal properties, within the respective array regions. For instance, the performance characteristics of resistance variable material 412-1 in via 420-1 of region 436 may be different than the performance characteristics of resistance variable material 412-2 in via 420-1 of region 434. As such, resistive memory cells formed in region 434 can exhibit different cell characteristics as compared to cells formed in region 436.

(54) FIG. 4I illustrates a process stage subsequent to that shown in FIG. 4H and associated with forming array 202. A metal material 424, e.g., a copper material, is formed on resistance variable material 412-1 and resistance variable material 412-2. Metal material 424 can be formed using a damascene process, and in a number of embodiments, metal material 424 can serve as a cap material, an electrode, and/or a bit line. In a number of embodiments, resistance variable materials 412-1 and 412-2 are between two conductive elements, e.g., between a conductive cap material 318-1 and/or 318-2 and a conductive plug 430-1 and/or 430-2.

(55) Although not shown in FIG. 4I, metal material 424 may also interact with a separate bit line. In a number of embodiments, a barrier material (not shown) can be formed between resistance variable materials 412-1 and 412-2 and metal material 424. The barrier can comprise, for example, a metal nitride, such as, for example, titanium nitride and/or tantalum nitride.

(56) Although the example shown in FIGS. 4A-4H is for an array of phase change memory cells, embodiments are not so limited. For instance, in a number of embodiments, the array 402 can be an array of RRAM cells or other resistive memory cells having separate regions with different cell characteristics. In the example shown in FIGS. 4A-4H, resistance variable materials 412-1 and 412-2 can comprise phase change materials formed on the conductive plugs, e.g., plugs 430-3 and 430-1. As such, the conductive plugs can serve as heaters for array 402.

(57) FIGS. 5A-5E illustrate various process stages associated with forming an array 502 of resistive memory cells in accordance with a number of embodiments of the present disclosure. The memory cells of array 502 can be resistive memory cells such as resistive memory cells 104, as described above. As an example, the array 502 can be an array of phase change memory cells.

(58) FIG. 5A illustrates a first region 534 and a second region 536 of array 502. In the example shown in FIG. 5A, regions 534 and 536 include conductive plugs 530-1, . . . , 530-4 formed between a heater material 510, e.g., a conductive material, and a substrate 532. In a number of embodiments, heater material 510 is limited in a direction perpendicular to the rows of memory cells (not shown) prior to a material, e.g., a resistance variable material, being formed on the heater material 510.

(59) The conductive plugs 530-1, . . . , 530-4 are separated by a dielectric material 522 formed on substrate 532. The dielectric material 522 can be a material such as silicon dioxide or silicon nitride, for instance. The substrate 532 can be a silicon substrate, silicon on insulator (SOI) substrate, silicon on sapphire (SOS) substrate, for instance, and can include various doped and/or undoped semiconductor materials. The heater material 510 is formed on plugs 530-1, . . . , 530-4 and can be various conductive materials such as metal nitride, e.g., tungsten nitride and/or titanium nitride, among other conductive materials.

(60) FIG. 5B illustrates a process stage subsequent to that shown in FIG. 5A and associated with forming array 502. A resistance variable material 512, e.g., a phase change material, is formed on heater material 510. That is, the heater material 510 of regions 534 and 536 includes resistance variable material 512 formed thereon.

(61) As illustrated in FIG. 5B, a cap material 518, e.g., a conductive material, is formed on the resistance variable material 512 in regions 234 and 236. The cap material 518 can comprise, for example, a metal nitride such as titanium nitride and/or tungsten nitride, among various other cap materials.

(62) FIG. 5C illustrates a process stage subsequent to that shown in FIG. 5B and associated with forming array 502. Arrows 526 represent ion implantation on at least a portion of region 536. In a number of embodiments, as a result of the ion implantation, an electrothermal property of resistance variable material 512 is modified in at least a portion of region 536.

(63) FIG. 5D illustrates a process stage subsequent to that shown in FIG. 5C and associated with forming array 502. Arrows 528 represent ion implantation on at least a portion of region 534. In a number of embodiments, as a result of the ion implantation, an electrothermal property of resistance variable material 512 is modified in at least a portion of region 534. It may be sufficient, in various embodiments, to perform ion implantation on at least a portion of region 536, but not region 534, (and vice versa) to differentiate electrothermal properties between resistance variable material 512 in each of regions 534 and 536.

(64) In a number of embodiments, ion implantation processes, e.g., as represented by arrows 526 and/or 528, can include implantation of different types of ions in the respective regions 536 and 534. The ions can be implanted through cap material 518, for example, and can include implantation of ions such as arsenic, phosphorus, and/or boron, among other ions. In a number of embodiments, the implanted ions can be metal ions. The implantation processes 526 and 528 can have different associated ion concentrations, different associated ion energies, and/or different numbers of ions.

(65) As such, although the same resistance variable material 512 is formed in regions 534 and 536, the ion implantation processes 526 and/or 528 can be used to modify the electrothermal properties of the material 512 within the respective regions 536 and 534. Therefore, the memory cells formed in regions 536 and 534 can have different cell characteristics associated therewith. In a number of embodiments, modifying the electrothermal properties of the material 512 can include thermal activation to modify the electrothermal properties of the resistance variable material 512 within regions 536 and 534. The thermal activation can apply to ion implantation processes 526 and/or 528, and thermal activation can also apply to a reactant material processes.

(66) FIG. 5E illustrates a process stage subsequent to that shown in FIG. 5D and associated with forming array 502. As shown in FIG. 5E, individual resistive memory cells 513-1 and 513-2 can be defined by removing portions of materials 510, 512, and 518. In a number of embodiments, resistance variable material 512 is between two conductive elements, e.g., between a conductive cap material 518 and a heater material 510.

(67) Although specific embodiments have been illustrated and described herein, those of ordinary skill in the art will appreciate that an arrangement calculated to achieve the same results can be substituted for the specific embodiments shown. This disclosure is intended to cover adaptations or variations of various embodiments of the present disclosure. It is to be understood that the above description has been made in an illustrative fashion, and not a restrictive one. Combination of the above embodiments, and other embodiments not specifically described herein will be apparent to those of skill in the art upon reviewing the above description. The scope of the various embodiments of the present disclosure includes other applications in which the above structures and methods are used. Therefore, the scope of various embodiments of the present disclosure should be determined with reference to the appended claims, along with the full range of Equivalents to which such claims are entitled.

(68) In the foregoing Detailed Description, various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the disclosed embodiments of the present disclosure have to use more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment.