Variable gain amplifiers for communication systems

Abstract

The present invention is directed to electrical circuits and techniques thereof. In various embodiments, the present invention provides a variable gain amplifier architecture that includes a continuous-time linear equalizer (CTLE) section and a variable gain amplifier (VGA) section. The CTLE section provides both a pair of equalized data signals and a common mode voltage. A DAC generates a control signal based on a control code. The VGA section amplifies the pair of equalized data signals by an amplification factor using a transistor whose resistance value is based on both the common mode voltage and the control signal. There are other embodiments as well.

Claims

1. A variable-gain amplifier device comprising: an equalizer section comprising: a first transistor and a second transistor, the first transistor comprising a first gate terminal coupled to a first input signal and a first drain terminal coupled to a first output node, the second transistor comprising a second gate terminal coupled to a second input signal and a second drain terminal coupled to a second output node; a first common mode resistor coupled to the first output node; a second common mode resistor coupled to the second output node and the first common mode resistor; a common node configured between the first common mode resistor and the second common mode resistor, the common node is characterized by a common mode voltage; an amplifier section comprising: a third transistor and a fourth transistor, the third transistor comprising a third gate terminal coupled to the first output node and a third drain node coupled to a third output node, the fourth transistor comprising a fourth gate terminal coupled to the second output node and a fourth drain terminal coupled to a fourth output node; and a fifth transistor comprising a fifth gate terminal coupled to a control voltage and the common node between the first common mode resistor and the second common resistor, the fifth transistor being characterized by a resistance value configured between the third transistor and the fourth transistor, the resistance value based on the control voltage and the common node voltage.

2. The device of claim 1 further comprising: a first load resistor coupled to the first output node; a second load resistor coupled to the second output node.

3. The device of claim 2 further comprising a current source coupled to a source terminal of the first transistor.

4. The device of claim 2 further comprising a voltage supply coupled to the first load resistor.

5. The device of claim 1 further comprising: a first load capacitor coupled to the third output node; a second load capacitor coupled to the fourth output node.

6. The device of claim 1 wherein a sum of a common voltage and the control voltage is greater than a threshold voltage of the fifth transistor.

7. The device of claim 6 wherein the fifth transistor comprises a triode region transistor.

8. The device of claim 6 wherein the threshold voltage is associated with a gate-source voltage differential.

9. The device of claim 1 wherein a gain control code is calibrated based at least on a voltage of the common node.

10. The device of claim 9 further comprising a digital-to-analog (DAC) configured to generate the control voltage based the gain control code.

11. A variable gain amplifier device comprising: a first transistor and a second transistor, the first transistor comprising a first gate terminal coupled to a first input signal and a first drain terminal coupled to a first output node, the second transistor comprising a second gate terminal coupled to a second input signal and a second drain terminal coupled to a second output node; a first common mode resistor coupled to the first output node; a second common mode resistor coupled to the second output node and the first common mode resistor; a common node configured between the first common mode resistor and the second common mode resistor, the common node is characterized by a common mode voltage; a third transistor and a fourth transistor, the third transistor comprising a third gate terminal coupled to the first output node and a third drain node coupled to a third output node, the fourth transistor comprising a fourth gate terminal coupled to the second output node and a fourth drain terminal coupled to a fourth output node; and a fifth transistor comprising a fifth gate terminal coupled to a control voltage and the common node between the first common mode resistor and the second common resistor, the fifth transistor being configured between the third transistor and the fourth resistor, the resistance value based on the control voltage and the common node voltage.

12. The device of claim 11 wherein the first transistor comprises a PMOS transistor.

13. The device of claim 11 wherein the third transistor comprises a PMOS transistor.

14. The device of claim 11 further comprising a digital-to-analog converter (DAC) for generating the control voltage based on a code word.

15. The device of claim 11 wherein the common node voltage is greater than the control voltage.

16. A serializer/deserializer (SerDes) apparatus comprising: a data communication interface for receiving a first input signal and a second input signal; a continuous-time linear equalizer (CTLE) section configured for providing a common mode voltage and a first equalized signal and a second equalized signal based at least on the first input signal and the second input signal, the CTLE section comprising a pair of common mode resistors, the common mode voltage being configured between the pair of common mode resistors; a digital-to-analog (DAC) section configured for generating a control signal based on a control code; a variable gain amplifier (VGA) section comprising a transistor and configured to generate a first amplified signal and a second amplified signal based on the first equalized signal and the second equalized signal, the VGA section being characterized by a gain ratio being at least based on a degeneration resistance value of the transistor, the degeneration resistance value being a function of the common mode voltage and the control signal; and a clock data recovery module being configured to generate a clock signal using at least the first equalize signal and the second equalized signal.

17. The apparatus of claim 16 further comprising a loss of signal detection module, wherein the clock data recovery module operates in a standby mode if the loss of signal detection module fails to detect signal presence.

18. The apparatus of claim 16 wherein the data communication interface is coupled to a wired communication lane.

19. The apparatus of claim 16 wherein data communication interface is coupled to one or more input inductors.

20. The apparatus of claim 16 wherein the data communication interface is coupled to one or more input resistors.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The following diagrams are merely examples, which should not unduly limit the scope of the claims herein. One of ordinary skill in the art would recognize many other variations, modifications, and alternatives. It is also understood that the examples and embodiments described herein are for illustrative purposes only and that various modifications or changes in light thereof will be suggested to persons skilled in the art and are to be included within the spirit and purview of this process and scope of the appended claims.

(2) FIG. 1 is a simplified block diagram illustrating a communication system according to embodiments of the present invention.

(3) FIG. 2A is a simplified diagram illustrating a conventional VGA.

(4) FIG. 2B is a simplified diagram illustrating a triode region transistor that can be used to implement a variable resistor.

(5) FIG. 2C is a diagram illustrating a conventional VGA.

(6) FIG. 3 is a simplified diagram illustrating a VGA according to embodiments of the present invention.

(7) FIG. 4 is a simplified diagram illustrating operation of VGA architecture 300 according to embodiments of the present invention.

(8) FIG. 5 is a graph illustrating VGA gain in relation to the DAC gain control code according to embodiments of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

(9) The present invention is directed to electrical circuits and techniques thereof. In various embodiments, the present invention provides a variable gain amplifier architecture that includes a continuous-time linear equalizer (CTLE) section and a variable gain amplifier (VGA) section. The CTLE section provides both a pair of equalized data signals and a common mode voltage. A DAC generates a control signal based on a control code. The VGA section amplifies the pair of equalized data signals by an amplification factor using a transistor whose resistance value is based on both the common mode voltage and the control signal. There are other embodiments as well.

(10) As explained above, variable gain amplifiers (VGA) have a wide range of applications. For example, VGAs are often used in communication applications. For example, as a part of a serializer/deserializer (SerDes) system, a VGA can be used to amplify amplitude of received analog signal before other processing techniques (e.g., clock recovery, ADC conversion, etc.) are performed. Depending on actual application and implementation of VGAs, there are various desirable VGA characteristics, such as low noise, small parasitic capacitance on the output nodes, and high linearity.

(11) It is to be appreciated that according to various embodiments of the present invention, VGAs are implemented in conjunction with continuous time linear equalizers. Continuous time linear equalizers are typically included in various types of communication and data processing systems. For example, a SerDes system includes both a transmitter module and a receiver module. Received analog signals, transmitted as a differential pair, are first processed by a continuous-time linear equalizer (CTLE) and then amplified by a VGA. In various embodiments of the presentation invention, VGAs are implemented in conjunction with CTLE. Additionally, one or more digital-to-analog converters (DAC) are used to provide control signal for both the CTLE and the VGA.

(12) FIG. 1 is a simplified block diagram illustrating a communication system according to embodiments of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. In FIG. 1, the transmitter (TX) transits data signal, as a differential signal, to the receiver (RX) via a pair of communication channels. For example, the communication channels can be existing copper wires. At the receiver, the input signals are received at the input terminals with inductor coils and input resistors that improve signal quality. The CTLE module is implemented as a part of the receiver. Input signals are equalized by the CTLE before further processing. For example, loss of signal detection (LOSD) module determines whether there is signal being received. Once it is determined that there are signal coming from the transmitting entity (TX), equalization is performed by the CTLE module. On the other hand, if the LOSD module fails to detect signal presence (or detecting a lack of signal presence), signal processing is not performed. For example, the CTLE module is used as a component of an analog front end portion of the communication device. The equalized signal, which is a differential pair, is then provided to the VGA as show. The VGA is specifically configured to amplify the received signal by a predetermined amount, and the VGA operates in conjunction with CLTE. For example, compared to conventional VGAs implemented with switchable resistor array, VGA implementations according to embodiments of the present invention offer improved performance by taking advantage of the CTLEs. It is to be appreciated that the use of CTLEs with VGAs takes advantage of the fact that CTLEs are essential front end circuit of the receiver devices. For example, receivers are generally implemented with CTLEs followed by one or more VGAs. For example, the VGA is configured to enable constant output voltage swing at the output for a different set of channel lengths by adjusting the gain control code. It is to be appreciated that VGAs according to embodiment of the present invention help maintain linearity. The available signal swing at the output stage can be adjusted using VGAs. For ADC based communication links, automatic gain control often allows for reduced resolution and full-scale range requirement of the ADCs. As mentioned above, VGAs according to the present invention provide high SNR, fine tunability (e.g., 5 to 8 bits), and small parasitic capacitance at the critical nodes.

(13) As shown in FIG. 1, after equalization is performed by the CTLE module and adjusted by the VGA, signal processing such as clock data recovery (CDR), analog to digital conversion (ADC), and/or other processes are then performed. It is to be appreciated that the receiver illustrated in FIG. 1 can be used in a variety of applications and systems. For example, the receiver can be a part of a transceiver device. In various embodiments, receivers are implemented as parts of SerDes system.

(14) As mentioned above, conventional VGAs are often implemented with a switchable resistor array. FIG. 2A is a simplified diagram illustrating a conventional VGA. A conventional VGA includes a pair of input transistors for receiving differential input signals. As shown, input INP is coupled to the gate terminal of transistor M.sub.1A, and input INN is coupled to the gate terminal of transistor M.sub.1B. A switchable resistor array section is coupled to the source terminals of transistors M.sub.1A and M.sub.1B. Outputs at the drain terminals of transistors M.sub.1A and M.sub.1B are coupled to load resistors R.sub.L and load capacitor C.sub.L. Supply voltage is provided at terminal V.sub.dd. Tail current source is provided through transistors M.sub.T.

(15) To change the output gain, control signal is applied to the switch transistors M.sub.SW. Ideally, output gain is linearly proportional to the amplitude of control signal within a large operating frequency range. Unfortunately, the performance of conventional VGA architecture illustrated in FIG. 1 is far from ideal. Among other things, capacitance at node X and Y would limit the frequency response. Additional, this capacitance may cause undesirable phase shift and group delay described be Equation 1 below:

(16) $\begin{array}{cc}\mathrm{Frequency}\mathrm{dependent}\mathrm{amplifier}\mathrm{gain}=\frac{g_{m1}}{1+\frac{g_{m1}{R}_{\mathrm{deg}}}{2+{\mathrm{SC}}_P{R}_{\mathrm{deg}}}}\frac{R_L}{1+{\mathrm{SC}}_L{R}_L}& \mathrm{Equation}1\end{array}$

(17) Depending on the implementation, the parasitic capacitance can increase with number of gain steps and gain range (i.e., depending on the number of switches). More specifically, when increasing number of gain steps, number of switches increases accordingly (e.g., 32 for 5-bits gain control). The increased number of switches introduces a lot of undesirable coupling capacitance in the signal path in the circuit physical layout. The coupling capacitance usually leads to impaired frequency response for the VGA.

(18) In addition to switch resistor array configuration illustrated in FIG. 2A, conventional systems also provide for variable resistor implementation. For example, the switch resistors array illustrated in FIG. 2A can be replaced by one or more variable resistors. FIG. 2B is a simplified diagram illustrating a triode region transistor that can be used to implement a variable resistor. For example, the drain-to-source resistance of the triode region transistor changes continuously with gate voltage change. Even for a wide range of gain variations, a single transistor may be sufficient, thus eliminating the need for having multiple resistors and switches. The reduced number of resistive elements can effectively reduce the undesirable parasitic capacitance associated with switches. For example, the resistance value of the triode region transistor in FIG. 2B can be described by Equation 2 below:

(19) $\begin{array}{cc}{R}_{\mathrm{ds}}=\frac{1}{u_n{C}_{\mathrm{ox}}\frac{W}{L}\left(V_{\mathrm{gs}}-V_{\mathrm{th}}\right)}& \mathrm{Equation}2\end{array}$

(20) For example, the resistance value R.sub.ds can be adjusted by changing the voltage applied to the gate of the triode region transistor. A gain control module is coupled to the triode region transistor and applies the gate voltage accordingly. Unfortunately, the use of triode region transistors in lieu of resistor arrays has its own drawbacks. The gain control transistor needs to operate in triode region during the entire signal swing. Otherwise, the triode region transistor would behave as a current source as opposed to the intended resistor which limits gain and linearity.

(21) FIG. 2C is a diagram illustrating a conventional VGA. Triode region transistor M.sub.GC operates as a variable gain resistor, and its resistance value is based its gate voltage at point Z. The gate voltage is provided by a DAC, which coverts gain control code to the gate voltage. As mentioned above, transistor M.sub.GC needs to operate in triode region for the VGA to work, and that means the gate voltage at node Z need to be higher than voltage at node X, and the voltage difference should be great than the transistor threshold voltage V.sub.th. Triode region voltage can be expressed by Equation 3 below:
V.sub.Z>V.sub.X+V.sub.thEquation 3:

(22) To maintain voltage V.sub.Z, the DAC output voltage needs to be maintained. For example, the DAC gain control code can be preprogrammed to avoid voltage V.sub.Z dropping too low. A major drawback for VGA in FIG. 2C is thus the dependence on the DAC output. For example, deviations from the DAC output could cause transistor M.sub.GC to enter non-triode mode and result in VGA non-linearity. It is to be appreciated that embodiments of the present invention implement efficient VGA structures with few of the conventional VGA drawbacks.

(23) The following description is presented to enable one of ordinary skill in the art to make and use the invention and to incorporate it in the context of particular applications. Various modifications, as well as a variety of uses in different applications will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to a wide range of embodiments. Thus, the present invention is not intended to be limited to the embodiments presented, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

(24) In the following detailed description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the present invention may be practiced without necessarily being limited to these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the present invention.

(25) The reader's attention is directed to all papers and documents which are filed concurrently with this specification and which are open to public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference. All the features disclosed in this specification, (including any accompanying claims, abstract, and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features.

(26) Furthermore, any element in a claim that does not explicitly state means for performing a specified function, or step for performing a specific function, is not to be interpreted as a means or step clause as specified in 35 U.S.C. Section 112, Paragraph 6. In particular, the use of step of or act of in the Claims herein is not intended to invoke the provisions of 35 U.S.C. 112, Paragraph 6.

(27) Please note, if used, the labels left, right, front, back, top, bottom, forward, reverse, clockwise and counter clockwise have been used for convenience purposes only and are not intended to imply any particular fixed direction. Instead, they are used to reflect relative locations and/or directions between various portions of an object.

(28) As mentioned above, VGAs according to embodiments of the present invention are implemented in conjunction with CTLEs. FIG. 3 is a simplified diagram illustrating a VGA according to embodiments of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. As shown, the VGA architecture 300 includes a CTLE section 310 and a VGA section 320. For example, CTLE section 310 and VGA section 320 are both parts of a large device, such as a receiver or a SerDes front end. Among other things, CTLE section 310 provides equalized differential signals that is to be amplified by the VGA section 320. CTLE section 310 additionally provides control signal for transistor M.sub.GC, which functions as a voltage controlled variable resistor. By injecting controlled amount of current into the CTLE section 310, VGA architecture ensures the adequate gate voltage for transistor M.sub.GC which is sufficiently above the threshold voltage keep transistor M.sub.GC operating in its triode region.

(29) As shown in FIG. 3, input signals are received by the input transistors at the CTLE section 310. Positive input signal INP is provided at the gate of transistor M.sub.1C, and the negative input signal INN is provided at the gate of transistor M.sub.1D. The source terminals of transistors M.sub.1C and M.sub.1D are coupled to current sources. CTLE output signals V.sub.op1 and V.sub.on1 of the CTLE are provided at the drain terminals of transistors M.sub.1C and M.sub.1D. The drain terminals of transistors M.sub.1C and M.sub.1D are additionally coupled to load resistors 311 and 312. A pair of common mode resistors 313 and 314 are provided between the two output signals to sense the common mode voltage. CTLE output signals V.sub.op1 and V.sub.on1 are provided to the input transistors of VGA section 320. Supply voltage for both CTLE section 310 and VGA section 320 is provided at terminal V.sub.dd as shown.

(30) The amplification of the VGA architecture, which determines swing magnitude of output signals V.sub.op2 and V.sub.on2, is based on the resistance value (between point X and point Y) of transistor M.sub.GC. To change the resistance value of transistor M.sub.GC, the control voltage applied to the gate of transistor M.sub.GC (or node Z) is adjusted. The control voltage at node Z is a function of both output of DAC 301 and common node voltage between resistors 313 and 314. The common node voltage between resistors 313 and 314 ensures that a minimum voltage level is provided, as the voltage of control signal provided by DAC 301 is added on top of the common voltage at node W.

(31) Output signals V.sub.op1 and V.sub.on1 of CTEL section 310 are equalized signals used as input signals for VGA section 320. As an example, VGA section 320 is implemented with both differential inputs and differential outputs. Differential inputs are provided at gate terminals of transistors M.sub.1A and M.sub.1B. For example, transistors M.sub.1A and M.sub.1B are implemented using PMOS devices, but it is to be appreciated that other types of transistor devices are possible as well. Transistors M.sub.1A and M.sub.1B amplify V.sub.op1 and V.sub.on1 received at their respective gate terminals. The amount of amplification largely depends on the resistance between node X and node Y. For example, transistor M.sub.GC is a triode region biased in transistor, and it operates as a resister as long as the voltage at node Z is above the threshold voltage V.sub.th of transistor M.sub.GC. The common mode node W, as explained above, can be configured to have a voltage level that is always higher than the threshold voltage of transistor M.sub.GC. In various embodiments, common mode resistors 313 and 314 are specifically configured to have a much higher resistance value than the load resistors 311 and 312. In various embodiments, at CTLE section 310 the common mode resistor value is at least ten times greater than the load resistor value to avoid loading on the CTLE due to the invention. For example, the resistance of common resistor 314 is around 10K, while the resistance of load resistor 312 is about 150.

(32) In various embodiments, the control voltage from DAC 301 is specifically calibrated relative to the common mode voltage at node W. Digital control codes used as input for DAC 301 are calibrated according to common mode voltage at node W and the threshold voltage of the triode transistor M.sub.GC. It is to be understood while the threshold voltage of the triode transistor M.sub.GC is device specific and stays constant for the device, common mode voltage at node W may change due to different supply voltage at V.sub.dd or voltage of input signals. In certain implementations, a control module (not shown in FIG. 3) determines what gain control code to be fed into DAC 301 based on the supply voltage V.sub.dd and voltage swing of input signals INP and INN.

(33) Depending on the implementation, the gain control code for the DAC 301 can be set in various ways. For example, a feedback mechanism may be used to determine the common mode voltage at node W, and a control generates gain control accordingly. In various embodiments, swing of input voltage is predetermined to be within a range, and the gain control code is calibrated accordingly. For example, the gain control code may be stored at a lookup table.

(34) At the VGA section 320, output signals are provided at V.sub.op2 and V.sub.op2, where the signals received from the CTLE section 310 are amplified by a factor based on the resistance value of transistor M.sub.GC. At the VGA section 320, output nodes V.sub.op2 and V.sub.on2 are also coupled to load resistors and load capacitors. For example, V.sub.op2 is coupled to load resistor 321 and load capacitor 323; V.sub.on2 is coupled to load resistor 322 and load capacitor 324. In various implementations, use and arrangement of load resistors and capacitors may be modified.

(35) FIG. 4 is a simplified diagram illustrating operation of VGA architecture 300 according to embodiments of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The voltages of the nodes X, Y, and Z of VGA architecture 300 are shown. For the purpose of illustration, a 10 GHz sine wave differential signal is used as the input signal. The common mode voltage is about 500 mV, which is applied to node Z. The swing voltages of the output signals V.sub.op1 and V.sub.on1 around the common mode voltage of about 500 mV. In comparison, signals at nodes X and Y swing around 290 mV. This translates to at least 200 mV V.sub.gs, the voltage differential between gate voltage and the source/drain voltage, for the transistor M.sub.GC. The output of the DAC 301 is added to the 200 mV V.sub.gs, and the 200 mV functions as a buffer that prevents transistor M.sub.GC from moving out of its triode region. It is to be appreciated that while the DAC output voltage may change during operation, the common node voltage at the CTLE section 310 provides a buffer voltage that keeps transistor M.sub.GC in its triode region.

(36) FIG. 5 is a graph illustrating VGA gain in relation to the DAC gain control code according to embodiments of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, a 6-bits gain control code is used for DAC 301 in FIG. 3. The 6-bits of gain control code translates to 64 steps (2.sup.6), as shown in the horizontal axis. The VGA gain for VGA architecture 300 is adjusted from about 2.5 dB to about 6.5 dB. It is to be appreciated that the relationship between the VGA gain and the DAC code is substantially linear over the entire range, and there is no spikes caused by triode region transistors moving in and out of its triode region.

(37) While the above is a full description of the specific embodiments, various modifications, alternative constructions and equivalents may be used. Therefore, the above description and illustrations should not be taken as limiting the scope of the present invention which is defined by the appended claims.